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---------------------------------------------------------------------
----                                                             ----
----  OpenCores ATA/ATAPI-5 Host Controller                      ----
----  PIO Timing Controller (common for all OCIDEC cores)        ----
----                                                             ----
----  Author: Richard Herveille                                  ----
----          richard@asics.ws                                   ----
----          www.asics.ws                                       ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2001, 2002 Richard Herveille                  ----
----                          richard@asics.ws                   ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
----                                                             ----
---------------------------------------------------------------------
 
-- rev.: 1.0 march  7th, 2001. Initial release
-- rev.: 1.1 July  11th, 2001. Changed 'igo' & 'hold_go' signal generation.
--
--
--  CVS Log
--
--  $Id: atahost_pio_tctrl.vhd,v 1.1 2002-02-18 14:29:38 rherveille Exp $
--
--  $Date: 2002-02-18 14:29:38 $
--  $Revision: 1.1 $
--  $Author: rherveille $
--  $Locker:  $
--  $State: Exp $
--
-- Change History:
--               $Log: not supported by cvs2svn $
--
--
 
--
---------------------------
-- PIO Timing controller --
---------------------------
--
 
--
-- Timing       PIO mode transfers
----------------------------------------------
-- T0:  cycle time
-- T1:  address valid to DIOR-/DIOW-
-- T2:  DIOR-/DIOW- pulse width
-- T2i: DIOR-/DIOW- recovery time
-- T3:  DIOW- data setup
-- T4:  DIOW- data hold
-- T5:  DIOR- data setup
-- T6:  DIOR- data hold
-- T9:  address hold from DIOR-/DIOW- negated
-- Trd: Read data valid to IORDY asserted
-- Ta:  IORDY setup time
-- Tb:  IORDY pulse width
--
-- Transfer sequence
----------------------------------
-- 1)   set address (DA, CS0-, CS1-)
-- 2)   wait for T1
-- 3)   assert DIOR-/DIOW-
--         when write action present Data (timing spec. T3 always honored), enable output enable-signal
-- 4)   wait for T2
-- 5)   check IORDY
--         when not IORDY goto 5
--        when IORDY negate DIOW-/DIOR-, latch data (if read action)
--    when write, hold data for T4, disable output-enable signal
-- 6)   wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest
-- 7)   start new cycle
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity atahost_pio_tctrl is
        generic(
                TWIDTH : natural := 8;                   -- counter width
 
                -- PIO mode 0 settings (@100MHz clock)
                PIO_mode0_T1 : natural := 6;             -- 70ns
                PIO_mode0_T2 : natural := 28;            -- 290ns
                PIO_mode0_T4 : natural := 2;             -- 30ns
                PIO_mode0_Teoc : natural := 23           -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
        );
        port(
                clk    : in std_logic;                   -- master clock
                nReset : in std_logic;                   -- asynchronous active low reset
                rst    : in std_logic;                   -- synchronous active high reset
 
                -- timing/control register settings
                IORDY_en : in std_logic;                 -- use IORDY (or not)
                T1   : in unsigned(TWIDTH -1 downto 0);  -- T1 time (in clk-ticks)
                T2   : in unsigned(TWIDTH -1 downto 0);  -- T2 time (in clk-ticks)
                T4   : in unsigned(TWIDTH -1 downto 0);  -- T4 time (in clk-ticks)
                Teoc : in unsigned(TWIDTH -1 downto 0);  -- end of cycle time
 
                -- control signals
                go : in std_logic;                       -- PIO controller selected (strobe signal)
                we : in std_logic;                       -- write enable signal. '0'=read from device, '1'=write to device
 
                -- return signals
                oe    : buffer std_logic;                -- output enable signal
                done  : out std_logic;                   -- finished cycle
                dstrb : out std_logic;                   -- data strobe, latch data (during read)
 
                -- ATA signals
                DIOR,                                    -- IOread signal, active high
                DIOW  : buffer std_logic;                -- IOwrite signal, active high
                IORDY : in std_logic                     -- IORDY signal
        );
end entity atahost_pio_tctrl;
 
architecture structural of atahost_pio_tctrl is
        component ro_cnt is
        generic(
                SIZE : natural := 8;
                UD   : std_logic := '0'; -- default count down
                ID   : natural := 0      -- initial data after reset
        );
        port(
                clk    : in  std_logic;                  -- master clock
                nReset : in  std_logic := '1';           -- asynchronous active low reset
                rst    : in  std_logic := '0';           -- synchronous active high reset
 
                cnt_en : in  std_logic := '1';           -- count enable
                go     : in  std_logic;                  -- load counter and start sequence
                done   : out std_logic;                  -- done counting
                d      : in  unsigned(SIZE -1 downto 0); -- load counter value
                q      : out unsigned(SIZE -1 downto 0)  -- current counter value
        );
        end component ro_cnt;
 
        signal T1done, T2done, T4done, Teoc_done, IORDY_done : std_logic;
        signal busy, hold_go, igo, hT2done : std_logic;
begin
        -- generate internal go strobe
        -- strecht go until ready for new cycle
        process(clk, nReset)
        begin
                if (nReset = '0') then
                        busy <= '0';
                        hold_go <= '0';
                elsif (clk'event and clk = '1') then
                        if (rst = '1') then
                                busy <= '0';
                                hold_go <= '0';
                        else
                                busy <= (igo or busy) and not Teoc_done;
                                hold_go <= (go or (hold_go and busy)) and not igo;
                        end if;
                end if;
        end process;
        igo <= (go or hold_go) and not busy;
 
        -- 1)   hookup T1 counter
        t1_cnt : ro_cnt
                generic map (
                        SIZE => TWIDTH,
                        UD   => '0',
                        ID   => PIO_mode0_T1
                )
                port map (
                        clk => clk,
                        nReset => nReset,
                        rst => rst,
                        go => igo,
                        D => T1,
                        done => T1done
                );
 
        -- 2)   set (and reset) DIOR-/DIOW-, set output-enable when writing to device
        T2proc: process(clk, nReset)
        begin
                if (nReset = '0') then
                        DIOR <= '0';
                        DIOW <= '0';
                        oe   <= '0';
                elsif (clk'event and clk = '1') then
                        if (rst = '1') then
                                DIOR <= '0';
                                DIOW <= '0';
                                oe   <= '0';
                        else
                                DIOR <= (not we and T1done) or (DIOR and not IORDY_done);
                                DIOW <= (    we and T1done) or (DIOW and not IORDY_done);
                                oe   <= ( (we and igo) or oe) and not T4done; -- negate oe when t4-done
                        end if;
                end if;
        end process T2proc;
 
        -- 3)   hookup T2 counter
        t2_cnt : ro_cnt
                generic map (
                        SIZE => TWIDTH,
                        UD   => '0',
                        ID   => PIO_mode0_T2
                )
                port map (
                        clk => clk,
                        nReset => nReset,
                        rst => rst,
                        go => T1done,
                        D => T2,
                        done => T2done
                );
 
        -- 4)   check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-)
        -- hold T2done
        gen_hT2done: process(clk, nReset)
        begin
                if (nReset = '0') then
                        hT2done <= '0';
                elsif (clk'event and clk = '1') then
                        if (rst = '1') then
                                hT2done <= '0';
                        else
                                hT2done <= (T2done or hT2done) and not IORDY_done;
                        end if;
                end if;
        end process gen_hT2done;
        IORDY_done <= (T2done or hT2done) and (IORDY or not IORDY_en);
 
        -- generate datastrobe, capture data at rising DIOR- edge
        gen_dstrb: process(clk)
        begin
                if (clk'event and clk = '1') then
                        dstrb <= IORDY_done;
                end if;
        end process gen_dstrb;
 
        -- hookup data hold counter
        dhold_cnt : ro_cnt
                generic map (
                        SIZE => TWIDTH,
                        UD   => '0',
                        ID   => PIO_mode0_T4
                )
                port map (
                        clk => clk,
                        nReset => nReset,
                        rst => rst,
                        go => IORDY_done,
                        D => T4,
                        done => T4done
                );
        done <= T4done; -- placing done here provides the fastest return possible, 
                      -- while still guaranteeing data and address hold-times
 
        -- 5)   hookup end_of_cycle counter
        eoc_cnt : ro_cnt
                generic map (
                        SIZE => TWIDTH,
                        UD   => '0',
                        ID   => PIO_mode0_Teoc
                )
                port map (
                        clk => clk,
                        nReset => nReset,
                        rst => rst,
                        go => IORDY_done,
                        D => Teoc,
                        done => Teoc_done
                );
 
end architecture structural;

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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec1/] [atahost_pio_tctrl.vhd] - Blame information for rev 35

Line No.	Rev	Author	Line
1	25	rherveille	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- OpenCores ATA/ATAPI-5 Host Controller ----`
4			`---- PIO Timing Controller (common for all OCIDEC cores) ----`
5			`---- ----`
6			`---- Author: Richard Herveille ----`
7			`---- richard@asics.ws ----`
8			`---- www.asics.ws ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2001, 2002 Richard Herveille ----`
13			`---- richard@asics.ws ----`
14			`---- ----`
15			`---- This source file may be used and distributed without ----`
16			`---- restriction provided that this copyright statement is not ----`
17			`---- removed from the file and that any derivative work contains ----`
18			`---- the original copyright notice and the associated disclaimer.----`
19			`---- ----`
20			---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
21			`---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----`
22			`---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
23			`---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----`
24			`---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
25			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----`
26			`---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----`
27			`---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----`
28			`---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----`
29			`---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
30			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----`
31			`---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
32			`---- POSSIBILITY OF SUCH DAMAGE. ----`
33			`---- ----`
34			`---------------------------------------------------------------------`
35
36			`-- rev.: 1.0 march 7th, 2001. Initial release`
37			`-- rev.: 1.1 July 11th, 2001. Changed 'igo' & 'hold_go' signal generation.`
38			`--`
39			`--`
40			`-- CVS Log`
41			`--`
42			`-- $Id: atahost_pio_tctrl.vhd,v 1.1 2002-02-18 14:29:38 rherveille Exp $`
43			`--`
44			`-- $Date: 2002-02-18 14:29:38 $`
45			`-- $Revision: 1.1 $`
46			`-- $Author: rherveille $`
47			`-- $Locker: $`
48			`-- $State: Exp $`
49			`--`
50			`-- Change History:`
51			`-- $Log: not supported by cvs2svn $`
52			`--`
53			`--`
54
55			`--`
56			`---------------------------`
57			`-- PIO Timing controller --`
58			`---------------------------`
59			`--`
60
61			`--`
62			`-- Timing PIO mode transfers`
63			`----------------------------------------------`
64			`-- T0: cycle time`
65			`-- T1: address valid to DIOR-/DIOW-`
66			`-- T2: DIOR-/DIOW- pulse width`
67			`-- T2i: DIOR-/DIOW- recovery time`
68			`-- T3: DIOW- data setup`
69			`-- T4: DIOW- data hold`
70			`-- T5: DIOR- data setup`
71			`-- T6: DIOR- data hold`
72			`-- T9: address hold from DIOR-/DIOW- negated`
73			`-- Trd: Read data valid to IORDY asserted`
74			`-- Ta: IORDY setup time`
75			`-- Tb: IORDY pulse width`
76			`--`
77			`-- Transfer sequence`
78			`----------------------------------`
79			`-- 1) set address (DA, CS0-, CS1-)`
80			`-- 2) wait for T1`
81			`-- 3) assert DIOR-/DIOW-`
82			`-- when write action present Data (timing spec. T3 always honored), enable output enable-signal`
83			`-- 4) wait for T2`
84			`-- 5) check IORDY`
85			`-- when not IORDY goto 5`
86			`-- when IORDY negate DIOW-/DIOR-, latch data (if read action)`
87			`-- when write, hold data for T4, disable output-enable signal`
88			`-- 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest`
89			`-- 7) start new cycle`
90
91			`library ieee;`
92			`use ieee.std_logic_1164.all;`
93			`use ieee.std_logic_arith.all;`
94
95			`entity atahost_pio_tctrl is`
96			`generic(`
97			`TWIDTH : natural := 8; -- counter width`
98
99			`-- PIO mode 0 settings (@100MHz clock)`
100			`PIO_mode0_T1 : natural := 6; -- 70ns`
101			`PIO_mode0_T2 : natural := 28; -- 290ns`
102			`PIO_mode0_T4 : natural := 2; -- 30ns`
103			`PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240`
104			`);`
105			`port(`
106			`clk : in std_logic; -- master clock`
107			`nReset : in std_logic; -- asynchronous active low reset`
108			`rst : in std_logic; -- synchronous active high reset`
109
110			`-- timing/control register settings`
111			`IORDY_en : in std_logic; -- use IORDY (or not)`
112			`T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks)`
113			`T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks)`
114			`T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks)`
115			`Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time`
116
117			`-- control signals`
118			`go : in std_logic; -- PIO controller selected (strobe signal)`
119			`we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device`
120
121			`-- return signals`
122			`oe : buffer std_logic; -- output enable signal`
123			`done : out std_logic; -- finished cycle`
124			`dstrb : out std_logic; -- data strobe, latch data (during read)`
125
126			`-- ATA signals`
127			`DIOR, -- IOread signal, active high`
128			`DIOW : buffer std_logic; -- IOwrite signal, active high`
129			`IORDY : in std_logic -- IORDY signal`
130			`);`
131			`end entity atahost_pio_tctrl;`
132
133			`architecture structural of atahost_pio_tctrl is`
134			`component ro_cnt is`
135			`generic(`
136			`SIZE : natural := 8;`
137			`UD : std_logic := '0'; -- default count down`
138			`ID : natural := 0 -- initial data after reset`
139			`);`
140			`port(`
141			`clk : in std_logic; -- master clock`
142			`nReset : in std_logic := '1'; -- asynchronous active low reset`
143			`rst : in std_logic := '0'; -- synchronous active high reset`
144
145			`cnt_en : in std_logic := '1'; -- count enable`
146			`go : in std_logic; -- load counter and start sequence`
147			`done : out std_logic; -- done counting`
148			`d : in unsigned(SIZE -1 downto 0); -- load counter value`
149			`q : out unsigned(SIZE -1 downto 0) -- current counter value`
150			`);`
151			`end component ro_cnt;`
152
153			`signal T1done, T2done, T4done, Teoc_done, IORDY_done : std_logic;`
154			`signal busy, hold_go, igo, hT2done : std_logic;`
155			`begin`
156			`-- generate internal go strobe`
157			`-- strecht go until ready for new cycle`
158			`process(clk, nReset)`
159			`begin`
160			`if (nReset = '0') then`
161			`busy <= '0';`
162			`hold_go <= '0';`
163			`elsif (clk'event and clk = '1') then`
164			`if (rst = '1') then`
165			`busy <= '0';`
166			`hold_go <= '0';`
167			`else`
168			`busy <= (igo or busy) and not Teoc_done;`
169			`hold_go <= (go or (hold_go and busy)) and not igo;`
170			`end if;`
171			`end if;`
172			`end process;`
173			`igo <= (go or hold_go) and not busy;`
174
175			`-- 1) hookup T1 counter`
176			`t1_cnt : ro_cnt`
177			`generic map (`
178			`SIZE => TWIDTH,`
179			`UD => '0',`
180			`ID => PIO_mode0_T1`
181			`)`
182			`port map (`
183			`clk => clk,`
184			`nReset => nReset,`
185			`rst => rst,`
186			`go => igo,`
187			`D => T1,`
188			`done => T1done`
189			`);`
190
191			`-- 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device`
192			`T2proc: process(clk, nReset)`
193			`begin`
194			`if (nReset = '0') then`
195			`DIOR <= '0';`
196			`DIOW <= '0';`
197			`oe <= '0';`
198			`elsif (clk'event and clk = '1') then`
199			`if (rst = '1') then`
200			`DIOR <= '0';`
201			`DIOW <= '0';`
202			`oe <= '0';`
203			`else`
204			`DIOR <= (not we and T1done) or (DIOR and not IORDY_done);`
205			`DIOW <= ( we and T1done) or (DIOW and not IORDY_done);`
206			`oe <= ( (we and igo) or oe) and not T4done; -- negate oe when t4-done`
207			`end if;`
208			`end if;`
209			`end process T2proc;`
210
211			`-- 3) hookup T2 counter`
212			`t2_cnt : ro_cnt`
213			`generic map (`
214			`SIZE => TWIDTH,`
215			`UD => '0',`
216			`ID => PIO_mode0_T2`
217			`)`
218			`port map (`
219			`clk => clk,`
220			`nReset => nReset,`
221			`rst => rst,`
222			`go => T1done,`
223			`D => T2,`
224			`done => T2done`
225			`);`
226
227			`-- 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-)`
228			`-- hold T2done`
229			`gen_hT2done: process(clk, nReset)`
230			`begin`
231			`if (nReset = '0') then`
232			`hT2done <= '0';`
233			`elsif (clk'event and clk = '1') then`
234			`if (rst = '1') then`
235			`hT2done <= '0';`
236			`else`
237			`hT2done <= (T2done or hT2done) and not IORDY_done;`
238			`end if;`
239			`end if;`
240			`end process gen_hT2done;`
241			`IORDY_done <= (T2done or hT2done) and (IORDY or not IORDY_en);`
242
243			`-- generate datastrobe, capture data at rising DIOR- edge`
244			`gen_dstrb: process(clk)`
245			`begin`
246			`if (clk'event and clk = '1') then`
247			`dstrb <= IORDY_done;`
248			`end if;`
249			`end process gen_dstrb;`
250
251			`-- hookup data hold counter`
252			`dhold_cnt : ro_cnt`
253			`generic map (`
254			`SIZE => TWIDTH,`
255			`UD => '0',`
256			`ID => PIO_mode0_T4`
257			`)`
258			`port map (`
259			`clk => clk,`
260			`nReset => nReset,`
261			`rst => rst,`
262			`go => IORDY_done,`
263			`D => T4,`
264			`done => T4done`
265			`);`
266			`done <= T4done; -- placing done here provides the fastest return possible,`
267			`-- while still guaranteeing data and address hold-times`
268
269			`-- 5) hookup end_of_cycle counter`
270			`eoc_cnt : ro_cnt`
271			`generic map (`
272			`SIZE => TWIDTH,`
273			`UD => '0',`
274			`ID => PIO_mode0_Teoc`
275			`)`
276			`port map (`
277			`clk => clk,`
278			`nReset => nReset,`
279			`rst => rst,`
280			`go => IORDY_done,`
281			`D => Teoc,`
282			`done => Teoc_done`
283			`);`
284
285			`end architecture structural;`