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rherveille |
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Revision: 1.0
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Date: march 22nd, 2001
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Author: Richard Herveille
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- initial release
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Revision: 1.0a
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Date: april 12th, 2001
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Author: Richard Herveille
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- removed records.vhd
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- removed all references to records.vhd, make core compatible with VHDL to Verilog translation tools
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- fixed a minor bug where core didn't respond to IDEen bit.
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Revision: 1.1
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Date: June 18th, 2001
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Author: Richard Herveille
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- Changed PIOack generation. Avoid asserting PIOack continuosly when IDEen = '0'
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- Changed wishbone address-input from ADR_I(4 downto 0) to ADR_I(6 downto 2)
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Revision: 1.1a
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Date: June 19th, 2001
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Author: Richard Herveille
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- Missed a reference to ADR_I(4). Simplified DAT_O output multiplexor.
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Revision: 1.2
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Date: June 26th, 2001
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Author: Richard Herveille
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- Changed dPIOreq generation (controller.vhd). Wishbone burst accesses to ata device were not handled correctly
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- Change PIOack from "out" to "buffer" (controller.vhd + ata.vhd)
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Revision: 1.3
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Date: July 11th, 2001
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Author: Richard Herveille
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- renamed 'ata.vhd' to 'atahost.vhd'
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- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous
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- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).
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25 |
rherveille |
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Revision: 1.4
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Date: Februar 17th, 2002
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Author: Richard Herveille
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- renamed 'atahost.vhd' to 'atahost_top.vhd'
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- renamed 'controller.vhd' to 'atahost_controller.vhd'
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- renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd'
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- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
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- changed resD input to generic RESD in ud_cnt.vhd
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- changed ID input to generic ID in ro_cnt.vhd
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- changed core to reflect changes in ro_cnt.vhd
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- removed references to 'count' library
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- changed IO names
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- added disclaimer
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- added CVS log
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- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
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- core is now equivalent to verilog version
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32 |
rherveille |
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-----------------------------
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Revision: 1.5
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Date: May 19th, 2002.
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Author: Richard Herveille
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- Fixed a potential bug that forced the core into an unknown state
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when an asynchronous reset was given without a running clock
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