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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec2/] [atahost_controller.vhd] - Blame information for rev 33

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---------------------------------------------------------------------
----                                                             ----
----  OpenCores IDE Controller                                   ----
----  ATA/ATAPI-5 Controller (OCIDEC-2)                          ----
----                                                             ----
----  Author: Richard Herveille                                  ----
----          richard@asics.ws                                   ----
----          www.asics.ws                                       ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2001, 2002 Richard Herveille                  ----
----                          richard@asics.ws                   ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
----                                                             ----
---------------------------------------------------------------------
 
-- rev.: 1.0  march 18th, 2001. Initial release
-- rev.: 1.0a april 12th, 2001. Removed references to records.vhd
-- rev.: 1.1  june  18th, 2001. Changed PIOack generation. Avoid asserting PIOack continuously when IDEen = '0'
-- rev.: 1.2  june  26th, 2001. Changed dPIOreq generation. Core did not support wishbone burst accesses to ATA-device.
-- rev.: 1.3  july  11th, 2001. Changed PIOreq & PIOack generation (made them synchronous). 
--
--  CVS Log
--
--  $Id: atahost_controller.vhd,v 1.2 2002-05-19 06:07:09 rherveille Exp $
--
--  $Date: 2002-05-19 06:07:09 $
--  $Revision: 1.2 $
--  $Author: rherveille $
--  $Locker:  $
--  $State: Exp $
--
-- Change History:
--               $Log: not supported by cvs2svn $
--
 
--
-- OCIDEC2 supports:    
-- -Common Compatible timing access to all connected devices
--      -Separate timing accesses to data port
-- -No DMA support
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity atahost_controller is
        generic(
                TWIDTH : natural := 8;                   -- counter width
 
                -- PIO mode 0 settings (@100MHz clock)
                PIO_mode0_T1 : natural := 6;             -- 70ns
                PIO_mode0_T2 : natural := 28;            -- 290ns
                PIO_mode0_T4 : natural := 2;             -- 30ns
                PIO_mode0_Teoc : natural := 23           -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
        );
        port(
                clk    : in std_logic;                                            -- master clock in
                nReset  : in std_logic := '1';                 -- asynchronous active low reset
                rst    : in std_logic := '0';                    -- synchronous active high reset
 
                irq : out std_logic;                          -- interrupt request signal
 
                -- control / registers
                IDEctrl_rst,
                IDEctrl_IDEen,
                IDEctrl_FATR0,
                IDEctrl_FATR1 : in std_logic;
 
                -- PIO registers
                cmdport_T1,
                cmdport_T2,
                cmdport_T4,
                cmdport_Teoc : in unsigned(7 downto 0);
                cmdport_IORDYen : in std_logic;             -- PIO command port / non-fast timing
 
                dport0_T1,
                dport0_T2,
                dport0_T4,
                dport0_Teoc : in unsigned(7 downto 0);
                dport0_IORDYen : in std_logic;              -- PIO mode data-port / fast timing device 0
 
                dport1_T1,
                dport1_T2,
                dport1_T4,
                dport1_Teoc : in unsigned(7 downto 0);
                dport1_IORDYen : in std_logic;              -- PIO mode data-port / fast timing device 1
 
                PIOreq : in std_logic;                      -- PIO transfer request
                PIOack : buffer std_logic;                  -- PIO transfer ended
                PIOa   : in unsigned(3 downto 0);           -- PIO address
                PIOd   : in std_logic_vector(15 downto 0);  -- PIO data in
                PIOq   : out std_logic_vector(15 downto 0); -- PIO data out
                PIOwe  : in std_logic;                      -- PIO direction bit '1'=write, '0'=read
 
                -- ATA signals
                RESETn  : out std_logic;
                DDi      : in std_logic_vector(15 downto 0);
                DDo  : out std_logic_vector(15 downto 0);
                DDoe : out std_logic;
                DA        : out unsigned(2 downto 0);
                CS0n    : out std_logic;
                CS1n    : out std_logic;
 
                DIORn   : out std_logic;
                DIOWn   : out std_logic;
                IORDY   : in std_logic;
                INTRQ   : in std_logic
        );
end entity atahost_controller;
 
architecture structural of atahost_controller is
        --
        -- component declarations
        --
        component atahost_pio_actrl is
        generic(
                TWIDTH : natural := 8;                     -- counter width
 
                -- PIO mode 0 settings (@100MHz clock)
                PIO_mode0_T1 : natural := 6;               -- 70ns
                PIO_mode0_T2 : natural := 28;              -- 290ns
                PIO_mode0_T4 : natural := 2;               -- 30ns
                PIO_mode0_Teoc : natural := 23             -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
        );
        port(
                clk    : in std_logic;                     -- master clock
                nReset : in std_logic;                     -- asynchronous active low reset
                rst    : in std_logic;                     -- synchronous active high reset
 
                IDEctrl_FATR0,
                IDEctrl_FATR1 : in std_logic;
 
                cmdport_T1,
                cmdport_T2,
                cmdport_T4,
                cmdport_Teoc : in unsigned(7 downto 0);
                cmdport_IORDYen : in std_logic;            -- PIO command port / non-fast timing
 
                dport0_T1,
                dport0_T2,
                dport0_T4,
                dport0_Teoc : in unsigned(7 downto 0);
                dport0_IORDYen : in std_logic;             -- PIO mode data-port / fast timing device 0
 
                dport1_T1,
                dport1_T2,
                dport1_T4,
                dport1_Teoc : in unsigned(7 downto 0);
                dport1_IORDYen : in std_logic;             -- PIO mode data-port / fast timing device 1
 
                SelDev : in std_logic;                     -- Selected device   
 
                go   : in  std_logic;                      -- Start transfer sequence
                done : out std_logic;                      -- Transfer sequence done
                dir  : in  std_logic;                      -- Transfer direction '1'=write, '0'=read
                a    : in  unsigned(3 downto 0);           -- PIO transfer address
                q    : out std_logic_vector(15 downto 0);  -- Data read from ATA devices
 
                DDi : in std_logic_vector(15 downto 0);    -- Data from ATA DD bus
                oe  : buffer std_logic;                    -- DDbus output-enable signal
 
                DIOR,
                DIOW  : buffer std_logic;
                IORDY : in std_logic
        );
        end component atahost_pio_actrl;
 
        --
        -- signals
        --
        signal SelDev : std_logic;                      -- selected device
 
        signal dPIOreq, PIOgo : std_logic;              -- start PIO timing controller
        signal PIOdone : std_logic;                     -- PIO timing controller done
 
        -- PIO signals
        signal PIOdior, PIOdiow : std_logic;
        signal PIOoe : std_logic;
 
        -- synchronized ATA inputs
        signal sIORDY : std_logic;
 
begin
 
        --
        -- synchronize incoming signals
        --
        synch_incoming: block
                signal cIORDY : std_logic;                   -- capture IORDY
                signal cINTRQ : std_logic;                   -- capture INTRQ
        begin
                process(clk)
                begin
                        if (clk'event and clk = '1') then
                                cIORDY <= IORDY;
                                cINTRQ <= INTRQ;
 
                                sIORDY <= cIORDY;
                                irq    <= cINTRQ;
                        end if;
                end process;
        end block synch_incoming;
 
        --
        -- generate ATA signals
        --
        gen_ata_sigs: block
        begin
                -- generate registers for ATA signals
                gen_regs: process(clk, nReset)
                begin
                        if (nReset = '0') then
                                RESETn <= '0';
                                DIORn  <= '1';
                                DIOWn  <= '1';
                                DA     <= (others => '0');
                                CS0n      <= '1';
                                CS1n      <= '1';
                                DDo    <= (others => '0');
                                DDoe   <= '0';
                        elsif (clk'event and clk = '1') then
                                if (rst = '1') then
                                        RESETn <= '0';
                                        DIORn  <= '1';
                                        DIOWn  <= '1';
                                        DA     <= (others => '0');
                                        CS0n   <= '1';
                                        CS1n    <= '1';
                                        DDo    <= (others => '0');
                                        DDoe   <= '0';
                                else
                                        RESETn <= not IDEctrl_rst;
                                        DA   <= PIOa(2 downto 0);
                                        CS0n    <= not (not PIOa(3) and PIOreq); -- CS0 asserted when A(3) = '0'
                                        CS1n    <= not (    PIOa(3) and PIOreq); -- CS1 asserted when A(3) = '1'
 
                                        DDo   <= PIOd;
                                        DDoe  <= PIOoe;
                                        DIORn <= not PIOdior;
                                        DIOWn <= not PIOdiow;
                                end if;
                        end if;
                end process gen_regs;
        end block gen_ata_sigs;
 
        --
        -- generate selected device
        --
        gen_seldev: process(clk)
                variable Asel : std_logic; -- address selected
        begin
                Asel := not PIOa(3) and PIOa(2) and PIOa(1) and not PIOa(0); -- header/device register
 
                if (clk'event and clk = '1') then
                        if ( (PIOdone = '1') and (Asel = '1') and (PIOwe = '1') ) then
                                SelDev <= PIOd(4);
                        end if;
                end if;
        end process gen_seldev;
 
        -- generate PIOgo signal
        gen_PIOgo: process(clk, nReset)
        begin
                if (nReset = '0') then
                        dPIOreq <= '0';
                        PIOgo   <= '0';
                elsif (clk'event and clk = '1') then
                        if (rst = '1') then
                                dPIOreq <= '0';
                                PIOgo   <= '0';
                        else
                                dPIOreq <= PIOreq and not PIOack;
                                PIOgo   <= (PIOreq and not dPIOreq) and IDEctrl_IDEen;
                        end if;
        end
        end process gen_PIOgo;
        --
        -- Hookup PIO access controller
        --
        PIO_access_control: atahost_pio_actrl
                generic map(
                        TWIDTH => TWIDTH,
                        PIO_mode0_T1 => PIO_mode0_T1,
                        PIO_mode0_T2 => PIO_mode0_T2,
                        PIO_mode0_T4 => PIO_mode0_T4,
                        PIO_mode0_Teoc => PIO_mode0_Teoc
                )
                port map(
                        clk    => clk,
                        nReset => nReset,
                        rst    => rst,
                        IDEctrl_FATR0 => IDEctrl_FATR0,
                        IDEctrl_FATR1 => IDEctrl_FATR1,
                        cmdport_T1    => cmdport_T1,
                        cmdport_T2    => cmdport_T2,
                        cmdport_T4    => cmdport_T4,
                        cmdport_Teoc  => cmdport_Teoc,
                        cmdport_IORDYen => cmdport_IORDYen,
                        dport0_T1     => dport0_T1,
                        dport0_T2     => dport0_T2,
                        dport0_T4     => dport0_T4,
                        dport0_Teoc   => dport0_Teoc,
                        dport0_IORDYen => dport0_IORDYen,
                        dport1_T1     => dport1_T1,
                        dport1_T2     => dport1_T2,
                        dport1_T4     => dport1_T4,
                        dport1_Teoc   => dport1_Teoc,
                        dport1_IORDYen => dport1_IORDYen,
                        SelDev => SelDev,
                        go     => PIOgo,
                        done   => PIOdone,
                        dir    => PIOwe,
                        a      => PIOa,
                        q      => PIOq,
                        DDi    => DDi,
                        oe     => PIOoe,
                        DIOR   => PIOdior,
                        DIOW   => PIOdiow,
                        IORDY  => sIORDY
                );
 
        -- generate acknowledge
        gen_ack: process(clk)
        begin
                if (clk'event and clk = '1') the
                        PIOack <= PIOdone or (PIOreq and not IDEctrl_IDEen); -- acknowledge when done or when IDE not enabled (discard request)
                end if;
        end process gen_ack;
end architecture structural;
 

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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec2/] [atahost_controller.vhd] - Blame information for rev 33

Line No.	Rev	Author	Line
1	26	rherveille	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- OpenCores IDE Controller ----`
4			`---- ATA/ATAPI-5 Controller (OCIDEC-2) ----`
5			`---- ----`
6			`---- Author: Richard Herveille ----`
7			`---- richard@asics.ws ----`
8			`---- www.asics.ws ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2001, 2002 Richard Herveille ----`
13			`---- richard@asics.ws ----`
14			`---- ----`
15			`---- This source file may be used and distributed without ----`
16			`---- restriction provided that this copyright statement is not ----`
17			`---- removed from the file and that any derivative work contains ----`
18			`---- the original copyright notice and the associated disclaimer.----`
19			`---- ----`
20			---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
21			`---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----`
22			`---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
23			`---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----`
24			`---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
25			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----`
26			`---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----`
27			`---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----`
28			`---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----`
29			`---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
30			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----`
31			`---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
32			`---- POSSIBILITY OF SUCH DAMAGE. ----`
33			`---- ----`
34			`---------------------------------------------------------------------`
35
36			`-- rev.: 1.0 march 18th, 2001. Initial release`
37			`-- rev.: 1.0a april 12th, 2001. Removed references to records.vhd`
38			`-- rev.: 1.1 june 18th, 2001. Changed PIOack generation. Avoid asserting PIOack continuously when IDEen = '0'`
39			`-- rev.: 1.2 june 26th, 2001. Changed dPIOreq generation. Core did not support wishbone burst accesses to ATA-device.`
40			`-- rev.: 1.3 july 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous).`
41			`--`
42			`-- CVS Log`
43			`--`
44	32	rherveille	`-- $Id: atahost_controller.vhd,v 1.2 2002-05-19 06:07:09 rherveille Exp $`
45	26	rherveille	`--`
46	32	rherveille	`-- $Date: 2002-05-19 06:07:09 $`
47			`-- $Revision: 1.2 $`
48	26	rherveille	`-- $Author: rherveille $`
49			`-- $Locker: $`
50			`-- $State: Exp $`
51			`--`
52			`-- Change History:`
53			`-- $Log: not supported by cvs2svn $`
54			`--`
55
56			`--`
57			`-- OCIDEC2 supports:`
58			`-- -Common Compatible timing access to all connected devices`
59			`-- -Separate timing accesses to data port`
60			`-- -No DMA support`
61
62			`library ieee;`
63			`use ieee.std_logic_1164.all;`
64			`use ieee.std_logic_arith.all;`
65
66			`entity atahost_controller is`
67			`generic(`
68			`TWIDTH : natural := 8; -- counter width`
69
70			`-- PIO mode 0 settings (@100MHz clock)`
71			`PIO_mode0_T1 : natural := 6; -- 70ns`
72			`PIO_mode0_T2 : natural := 28; -- 290ns`
73			`PIO_mode0_T4 : natural := 2; -- 30ns`
74			`PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240`
75			`);`
76			`port(`
77			`clk : in std_logic; -- master clock in`
78			`nReset : in std_logic := '1'; -- asynchronous active low reset`
79			`rst : in std_logic := '0'; -- synchronous active high reset`
80
81			`irq : out std_logic; -- interrupt request signal`
82
83			`-- control / registers`
84			`IDEctrl_rst,`
85			`IDEctrl_IDEen,`
86			`IDEctrl_FATR0,`
87			`IDEctrl_FATR1 : in std_logic;`
88
89			`-- PIO registers`
90			`cmdport_T1,`
91			`cmdport_T2,`
92			`cmdport_T4,`
93			`cmdport_Teoc : in unsigned(7 downto 0);`
94			`cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing`
95
96			`dport0_T1,`
97			`dport0_T2,`
98			`dport0_T4,`
99			`dport0_Teoc : in unsigned(7 downto 0);`
100			`dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0`
101
102			`dport1_T1,`
103			`dport1_T2,`
104			`dport1_T4,`
105			`dport1_Teoc : in unsigned(7 downto 0);`
106			`dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1`
107
108			`PIOreq : in std_logic; -- PIO transfer request`
109			`PIOack : buffer std_logic; -- PIO transfer ended`
110			`PIOa : in unsigned(3 downto 0); -- PIO address`
111			`PIOd : in std_logic_vector(15 downto 0); -- PIO data in`
112			`PIOq : out std_logic_vector(15 downto 0); -- PIO data out`
113			`PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read`
114
115			`-- ATA signals`
116			`RESETn : out std_logic;`
117			`DDi : in std_logic_vector(15 downto 0);`
118			`DDo : out std_logic_vector(15 downto 0);`
119			`DDoe : out std_logic;`
120			`DA : out unsigned(2 downto 0);`
121			`CS0n : out std_logic;`
122			`CS1n : out std_logic;`
123
124			`DIORn : out std_logic;`
125			`DIOWn : out std_logic;`
126			`IORDY : in std_logic;`
127			`INTRQ : in std_logic`
128			`);`
129			`end entity atahost_controller;`
130
131			`architecture structural of atahost_controller is`
132			`--`
133			`-- component declarations`
134			`--`
135			`component atahost_pio_actrl is`
136			`generic(`
137			`TWIDTH : natural := 8; -- counter width`
138
139			`-- PIO mode 0 settings (@100MHz clock)`
140			`PIO_mode0_T1 : natural := 6; -- 70ns`
141			`PIO_mode0_T2 : natural := 28; -- 290ns`
142			`PIO_mode0_T4 : natural := 2; -- 30ns`
143			`PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240`
144			`);`
145			`port(`
146			`clk : in std_logic; -- master clock`
147			`nReset : in std_logic; -- asynchronous active low reset`
148			`rst : in std_logic; -- synchronous active high reset`
149
150			`IDEctrl_FATR0,`
151			`IDEctrl_FATR1 : in std_logic;`
152
153			`cmdport_T1,`
154			`cmdport_T2,`
155			`cmdport_T4,`
156			`cmdport_Teoc : in unsigned(7 downto 0);`
157			`cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing`
158
159			`dport0_T1,`
160			`dport0_T2,`
161			`dport0_T4,`
162			`dport0_Teoc : in unsigned(7 downto 0);`
163			`dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0`
164
165			`dport1_T1,`
166			`dport1_T2,`
167			`dport1_T4,`
168			`dport1_Teoc : in unsigned(7 downto 0);`
169			`dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1`
170
171			`SelDev : in std_logic; -- Selected device`
172
173			`go : in std_logic; -- Start transfer sequence`
174			`done : out std_logic; -- Transfer sequence done`
175			`dir : in std_logic; -- Transfer direction '1'=write, '0'=read`
176			`a : in unsigned(3 downto 0); -- PIO transfer address`
177			`q : out std_logic_vector(15 downto 0); -- Data read from ATA devices`
178
179			`DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus`
180			`oe : buffer std_logic; -- DDbus output-enable signal`
181
182			`DIOR,`
183			`DIOW : buffer std_logic;`
184			`IORDY : in std_logic`
185			`);`
186			`end component atahost_pio_actrl;`
187
188			`--`
189			`-- signals`
190			`--`
191			`signal SelDev : std_logic; -- selected device`
192
193			`signal dPIOreq, PIOgo : std_logic; -- start PIO timing controller`
194			`signal PIOdone : std_logic; -- PIO timing controller done`
195
196			`-- PIO signals`
197			`signal PIOdior, PIOdiow : std_logic;`
198			`signal PIOoe : std_logic;`
199
200			`-- synchronized ATA inputs`
201			`signal sIORDY : std_logic;`
202
203			`begin`
204
205			`--`
206			`-- synchronize incoming signals`
207			`--`
208			`synch_incoming: block`
209			`signal cIORDY : std_logic; -- capture IORDY`
210			`signal cINTRQ : std_logic; -- capture INTRQ`
211			`begin`
212			`process(clk)`
213			`begin`
214			`if (clk'event and clk = '1') then`
215			`cIORDY <= IORDY;`
216			`cINTRQ <= INTRQ;`
217
218			`sIORDY <= cIORDY;`
219			`irq <= cINTRQ;`
220			`end if;`
221			`end process;`
222			`end block synch_incoming;`
223
224			`--`
225			`-- generate ATA signals`
226			`--`
227			`gen_ata_sigs: block`
228			`begin`
229			`-- generate registers for ATA signals`
230			`gen_regs: process(clk, nReset)`
231			`begin`
232			`if (nReset = '0') then`
233			`RESETn <= '0';`
234			`DIORn <= '1';`
235			`DIOWn <= '1';`
236			`DA <= (others => '0');`
237			`CS0n <= '1';`
238			`CS1n <= '1';`
239			`DDo <= (others => '0');`
240			`DDoe <= '0';`
241			`elsif (clk'event and clk = '1') then`
242			`if (rst = '1') then`
243			`RESETn <= '0';`
244			`DIORn <= '1';`
245			`DIOWn <= '1';`
246			`DA <= (others => '0');`
247			`CS0n <= '1';`
248			`CS1n <= '1';`
249			`DDo <= (others => '0');`
250			`DDoe <= '0';`
251			`else`
252			`RESETn <= not IDEctrl_rst;`
253			`DA <= PIOa(2 downto 0);`
254			`CS0n <= not (not PIOa(3) and PIOreq); -- CS0 asserted when A(3) = '0'`
255			`CS1n <= not ( PIOa(3) and PIOreq); -- CS1 asserted when A(3) = '1'`
256
257			`DDo <= PIOd;`
258			`DDoe <= PIOoe;`
259			`DIORn <= not PIOdior;`
260			`DIOWn <= not PIOdiow;`
261			`end if;`
262			`end if;`
263			`end process gen_regs;`
264			`end block gen_ata_sigs;`
265
266			`--`
267			`-- generate selected device`
268			`--`
269			`gen_seldev: process(clk)`
270			`variable Asel : std_logic; -- address selected`
271			`begin`
272			`Asel := not PIOa(3) and PIOa(2) and PIOa(1) and not PIOa(0); -- header/device register`
273
274			`if (clk'event and clk = '1') then`
275			`if ( (PIOdone = '1') and (Asel = '1') and (PIOwe = '1') ) then`
276			`SelDev <= PIOd(4);`
277			`end if;`
278			`end if;`
279			`end process gen_seldev;`
280
281			`-- generate PIOgo signal`
282	32	rherveille	`gen_PIOgo: process(clk, nReset)`
283	26	rherveille	`begin`
284	32	rherveille	`if (nReset = '0') then`
285			`dPIOreq <= '0';`
286			`PIOgo <= '0';`
287			`elsif (clk'event and clk = '1') then`
288			`if (rst = '1') then`
289			`dPIOreq <= '0';`
290			`PIOgo <= '0';`
291			`else`
292			`dPIOreq <= PIOreq and not PIOack;`
293			`PIOgo <= (PIOreq and not dPIOreq) and IDEctrl_IDEen;`
294			`end if;`
295			`end`
296	26	rherveille	`end process gen_PIOgo;`
297			`--`
298			`-- Hookup PIO access controller`
299			`--`
300			`PIO_access_control: atahost_pio_actrl`
301			`generic map(`
302			`TWIDTH => TWIDTH,`
303			`PIO_mode0_T1 => PIO_mode0_T1,`
304			`PIO_mode0_T2 => PIO_mode0_T2,`
305			`PIO_mode0_T4 => PIO_mode0_T4,`
306			`PIO_mode0_Teoc => PIO_mode0_Teoc`
307			`)`
308			`port map(`
309			`clk => clk,`
310			`nReset => nReset,`
311			`rst => rst,`
312			`IDEctrl_FATR0 => IDEctrl_FATR0,`
313			`IDEctrl_FATR1 => IDEctrl_FATR1,`
314			`cmdport_T1 => cmdport_T1,`
315			`cmdport_T2 => cmdport_T2,`
316			`cmdport_T4 => cmdport_T4,`
317			`cmdport_Teoc => cmdport_Teoc,`
318			`cmdport_IORDYen => cmdport_IORDYen,`
319			`dport0_T1 => dport0_T1,`
320			`dport0_T2 => dport0_T2,`
321			`dport0_T4 => dport0_T4,`
322			`dport0_Teoc => dport0_Teoc,`
323			`dport0_IORDYen => dport0_IORDYen,`
324			`dport1_T1 => dport1_T1,`
325			`dport1_T2 => dport1_T2,`
326			`dport1_T4 => dport1_T4,`
327			`dport1_Teoc => dport1_Teoc,`
328			`dport1_IORDYen => dport1_IORDYen,`
329			`SelDev => SelDev,`
330			`go => PIOgo,`
331			`done => PIOdone,`
332			`dir => PIOwe,`
333			`a => PIOa,`
334			`q => PIOq,`
335			`DDi => DDi,`
336			`oe => PIOoe,`
337			`DIOR => PIOdior,`
338			`DIOW => PIOdiow,`
339			`IORDY => sIORDY`
340			`);`
341
342			`-- generate acknowledge`
343			`gen_ack: process(clk)`
344			`begin`
345	32	rherveille	`if (clk'event and clk = '1') the`
346	26	rherveille	`PIOack <= PIOdone or (PIOreq and not IDEctrl_IDEen); -- acknowledge when done or when IDE not enabled (discard request)`
347			`end if;`
348			`end process gen_ack;`
349			`end architecture structural;`
350