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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec3/] [atahost_controller.vhd] - Blame information for rev 35

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---------------------------------------------------------------------
----                                                             ----
----  OpenCores IDE Controller                                   ----
----  ATA/ATAPI-5 Host controller (OCIDEC-3)                     ----
----                                                             ----
----  Author: Richard Herveille                                  ----
----          richard@asics.ws                                   ----
----          www.asics.ws                                       ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2001, 2002 Richard Herveille                  ----
----                          richard@asics.ws                   ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
----                                                             ----
---------------------------------------------------------------------
 
-- rev.: 1.0 march 8th, 2001. Initial release
--
--  CVS Log
--
--  $Id: atahost_controller.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $
--
--  $Date: 2002-02-18 14:32:12 $
--  $Revision: 1.1 $
--  $Author: rherveille $
--  $Locker:  $
--  $State: Exp $
--
-- Change History:
--               $Log: not supported by cvs2svn $
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity atahost_controller is
        generic(
                TWIDTH : natural := 8;                   -- counter width
 
                -- PIO mode 0 settings (@100MHz clock)
                PIO_mode0_T1 : natural := 6;             -- 70ns
                PIO_mode0_T2 : natural := 28;            -- 290ns
                PIO_mode0_T4 : natural := 2;             -- 30ns
                PIO_mode0_Teoc : natural := 23;          -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
 
                -- Multiword DMA mode 0 settings (@100MHz clock)
                DMA_mode0_Tm : natural := 4;             -- 50ns
                DMA_mode0_Td : natural := 21;            -- 215ns
                DMA_mode0_Teoc : natural := 21           -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
        );
        port(
                clk : in std_logic;                                       -- master clock in
                nReset  : in std_logic := '1';                 -- asynchronous active low reset
                rst : in std_logic := '0';                    -- synchronous active high reset
 
                irq : out std_logic;                          -- interrupt request signal
 
                -- control / registers
                IDEctrl_IDEen,
                IDEctrl_rst,
                IDEctrl_ppen,
                IDEctrl_FATR0,
                IDEctrl_FATR1 : in std_logic;                 -- control register settings
 
                a : in unsigned(3 downto 0);                  -- address input
                d : in std_logic_vector(31 downto 0);         -- data input
                we : in std_logic;                            -- write enable input '1'=write, '0'=read
 
                -- PIO registers
                PIO_cmdport_T1,
                PIO_cmdport_T2,
                PIO_cmdport_T4,
                PIO_cmdport_Teoc : in unsigned(7 downto 0);
                PIO_cmdport_IORDYen : in std_logic;           -- PIO compatible timing settings
 
                PIO_dport0_T1,
                PIO_dport0_T2,
                PIO_dport0_T4,
                PIO_dport0_Teoc : in unsigned(7 downto 0);
                PIO_dport0_IORDYen : in std_logic;            -- PIO data-port device0 timing settings
 
                PIO_dport1_T1,
                PIO_dport1_T2,
                PIO_dport1_T4,
                PIO_dport1_Teoc : in unsigned(7 downto 0);
                PIO_dport1_IORDYen : in std_logic;            -- PIO data-port device1 timing settings
 
                PIOsel : in std_logic;                        -- PIO controller select
                PIOack : out std_logic;                       -- PIO controller acknowledge
                PIOq : out std_logic_vector(15 downto 0);     -- PIO data out
                PIOtip : buffer std_logic;                    -- PIO transfer in progress
                PIOpp_full : out std_logic;                   -- PIO Write PingPong full
 
                -- DMA registers
                DMA_dev0_Td,
                DMA_dev0_Tm,
                DMA_dev0_Teoc : in unsigned(7 downto 0);      -- DMA timing settings for device0
 
                DMA_dev1_Td,
                DMA_dev1_Tm,
                DMA_dev1_Teoc : in unsigned(7 downto 0);      -- DMA timing settings for device1
 
                DMActrl_DMAen,
                DMActrl_dir,
                DMActrl_BeLeC0,
                DMActrl_BeLeC1 : in std_logic;                -- DMA settings
 
                DMAsel : in std_logic;                        -- DMA controller select
                DMAack : out std_logic;                       -- DMA controller acknowledge
                DMAq : out std_logic_vector(31 downto 0);     -- DMA data out
                DMAtip : buffer std_logic;                    -- DMA transfer in progress
                DMA_dmarq : out std_logic;                    -- Synchronized ATA DMARQ line
 
                DMATxFull : buffer std_logic;                 -- DMA transmit buffer full
                DMARxEmpty : buffer std_logic;                -- DMA receive buffer empty
 
                DMA_req : out std_logic;                      -- DMA request to external DMA engine
                DMA_ack : in std_logic;                       -- DMA acknowledge from external DMA engine
 
                -- ATA signals
                RESETn  : out std_logic;
                DDi     : in std_logic_vector(15 downto 0);
                DDo : out std_logic_vector(15 downto 0);
                DDoe : out std_logic;
                DA      : out unsigned(2 downto 0);
                CS0n    : out std_logic;
                CS1n    : out std_logic;
 
                DMARQ   : in std_logic;
                DMACKn  : out std_logic;
                DIORn   : out std_logic;
                DIOWn   : out std_logic;
                IORDY   : in std_logic;
                INTRQ   : in std_logic
        );
end entity atahost_controller;
 
architecture structural of atahost_controller is
        --
        -- component declarations
        --
        component atahost_pio_controller is
        generic(
                TWIDTH : natural := 8;                   -- counter width
 
                -- PIO mode 0 settings (@100MHz clock)
                PIO_mode0_T1 : natural := 6;             -- 70ns
                PIO_mode0_T2 : natural := 28;            -- 290ns
                PIO_mode0_T4 : natural := 2;             -- 30ns
                PIO_mode0_Teoc : natural := 23           -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
        );
        port(
                clk : in std_logic;                                       -- master clock in
                nReset  : in std_logic := '1';                 -- asynchronous active low reset
                rst : in std_logic := '0';                    -- synchronous active high reset
 
                -- control / registers
                IDEctrl_IDEen,
                IDEctrl_ppen,
                IDEctrl_FATR0,
                IDEctrl_FATR1 : in std_logic;
 
                -- PIO registers
                cmdport_T1,
                cmdport_T2,
                cmdport_T4,
                cmdport_Teoc : in unsigned(7 downto 0);
                cmdport_IORDYen : in std_logic;            -- PIO command port / non-fast timing
 
                dport0_T1,
                dport0_T2,
                dport0_T4,
                dport0_Teoc : in unsigned(7 downto 0);
                dport0_IORDYen : in std_logic;             -- PIO mode data-port / fast timing device 0
 
                dport1_T1,
                dport1_T2,
                dport1_T4,
                dport1_Teoc : in unsigned(7 downto 0);
                dport1_IORDYen : in std_logic;             -- PIO mode data-port / fast timing device 1
 
                sel : in std_logic;                           -- PIO controller selected
                ack : out std_logic;                          -- PIO controller acknowledge
                a : in unsigned(3 downto 0);                  -- lower address bits
                we : in std_logic;                            -- write enable input
                d : in std_logic_vector(15 downto 0);
                q : out std_logic_vector(15 downto 0);
 
                PIOreq : out std_logic;                       -- PIO transfer request
                PPFull : out std_logic;                       -- PIO Write PingPong Full
                go : in std_logic;                            -- start PIO transfer
                done : buffer std_logic;                      -- done with PIO transfer
 
                PIOa : out unsigned(3 downto 0);              -- PIO address, address lines towards ATA devices
                PIOd : out std_logic_vector(15 downto 0);     -- PIO data, data towards ATA devices
 
                SelDev : buffer std_logic;                    -- Selected Device, Dev-bit in ATA Device/Head register
 
                DDi     : in std_logic_vector(15 downto 0);
                DDoe : buffer std_logic;
 
                DIOR    : buffer std_logic;
                DIOW    : buffer std_logic;
                IORDY   : in std_logic
        );
        end component atahost_pio_controller;
 
        component atahost_dma_actrl is
        generic(
                TWIDTH : natural := 8;                     -- counter width
 
                -- DMA mode 0 settings (@100MHz clock)
                DMA_mode0_Tm : natural := 4;               -- 50ns
                DMA_mode0_Td : natural := 21;              -- 215ns
                DMA_mode0_Teoc : natural := 21             -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
        );
        port(
                clk : in std_logic;                           -- master clock
                nReset : in std_logic;                        -- asynchronous active low reset
                rst : in std_logic;                           -- synchronous active high reset
 
                IDEctrl_rst : in std_logic;                   -- IDE control register bit0, 'rst'
 
                sel : in std_logic;                           -- DMA buffers selected
                we : in std_logic;                            -- write enable input
                ack : out std_logic;                                    -- acknowledge output
 
                dev0_Tm,
                dev0_Td,
                dev0_Teoc : in unsigned(7 downto 0);          -- DMA mode timing device 0
                dev1_Tm,
                dev1_Td,
                dev1_Teoc : in unsigned(7 downto 0);          -- DMA mode timing device 1
 
                DMActrl_DMAen,
                DMActrl_dir,
                DMActrl_BeLeC0,
                DMActrl_BeLeC1 : in std_logic;                -- control register settings
 
                TxD : in std_logic_vector(31 downto 0);       -- DMA transmit data
                TxFull : buffer std_logic;                    -- DMA transmit buffer full
                RxQ : out std_logic_vector(31 downto 0);      -- DMA receive data
                RxEmpty : buffer std_logic;                   -- DMA receive buffer empty
                RxFull : out std_logic;                       -- DMA receive buffer full
                DMA_req : out std_logic;                      -- DMA request to external DMA engine
                DMA_ack : in std_logic;                       -- DMA acknowledge from external DMA engine
 
                DMARQ : in std_logic;                         -- ATA devices request DMA transfer
 
                SelDev : in std_logic;                        -- Selected device        
 
                Go : in std_logic;                            -- Start transfer sequence
                Done : out std_logic;                         -- Transfer sequence done
 
                DDi : in std_logic_vector(15 downto 0);       -- Data from ATA DD bus
                DDo : out std_logic_vector(15 downto 0);      -- Data towards ATA DD bus
 
                DIOR,
                DIOW : buffer std_logic
        );
        end component atahost_dma_actrl;
 
        --
        -- signals
        --
        signal SelDev : std_logic;                       -- selected device
        signal DMARxFull : std_logic;                    -- DMA receive buffer full
 
        -- PIO / DMA signals
        signal PIOgo, DMAgo : std_logic;                 -- start PIO / DMA timing controller
        signal PIOdone, DMAdone : std_logic;             -- PIO / DMA timing controller done
 
        -- PIO signals
        signal PIOdior, PIOdiow : std_logic;
        signal PIOoe : std_logic;
 
        -- PIO pingpong signals
        signal PIOd : std_logic_vector(15 downto 0);
        signal PIOa : unsigned(3 downto 0);
        signal PIOreq : std_logic;
 
        -- DMA signals
        signal DMAd : std_logic_vector(15 downto 0);
        signal DMAdior, DMAdiow : std_logic;
 
        -- synchronized ATA inputs
        signal sDMARQ, sIORDY : std_logic;
 
begin
 
        --
        -- synchronize incoming signals
        --
        synch_incoming: block
                signal cDMARQ : std_logic;                   -- capture DMARQ
                signal cIORDY : std_logic;                   -- capture IORDY
                signal cINTRQ : std_logic;                   -- capture INTRQ
        begin
                process(clk)
                begin
                        if (clk'event and clk = '1') then
                                cDMARQ <= DMARQ;
                                cIORDY <= IORDY;
                                cINTRQ <= INTRQ;
 
                                sDMARQ <= cDMARQ;
                                sIORDY <= cIORDY;
                                irq    <= cINTRQ;
                        end if;
                end process;
 
                DMA_dmarq <= sDMARQ;
        end block synch_incoming;
 
        --
        -- generate ATA signals
        --
        gen_ata_sigs: block
                signal iDDo : std_logic_vector(15 downto 0);
        begin
                -- generate registers for ATA signals
                gen_regs: process(clk, nReset)
                begin
                        if (nReset = '0') then
                                RESETn <= '0';
                                DIORn  <= '1';
                                DIOWn  <= '1';
                                DA     <= (others => '0');
                                CS0n      <= '1';
                                CS1n      <= '1';
                                DDo    <= (others => '0');
                                DDoe   <= '0';
                                DMACKn <= '1';
                        elsif (clk'event and clk = '1') then
                                if (rst = '1') then
                                        RESETn <= '0';
                                        DIORn  <= '1';
                                        DIOWn  <= '1';
                                        DA     <= (others => '0');
                                        CS0n   <= '1';
                                        CS1n    <= '1';
                                        DDo    <= (others => '0');
                                        DDoe   <= '0';
                                        DMACKn <= '1';
                                else
                                        RESETn <= not IDEctrl_rst;
                                        DA     <= PIOa(2 downto 0);
                                        CS0n      <= not (not PIOa(3) and PIOtip); -- CS0 asserted when A(3) = '0', negate during DMA transfers
                                        CS1n      <= not (    PIOa(3) and PIOtip); -- CS1 asserted when A(3) = '1', negate during DMA transfers
 
                                        if (PIOtip = '1') then
                                                DDo   <= PIOd;
                                                DDoe  <= PIOoe;
                                                DIORn <= not PIOdior;
                                                DIOWn <= not PIOdiow;
                                        else
                                                DDo   <= DMAd;
                                                DDoe  <= DMActrl_dir and DMAtip;
                                                DIORn <= not DMAdior;
                                                DIOWn <= not DMAdiow;
                                        end if;
 
                                        DMACKn <= not DMAtip;
                                end if;
                        end if;
                end process gen_regs;
        end block gen_ata_sigs;
 
        --
        -- generate bus controller statemachine
        --
        statemachine: block
                type states is (idle, PIO_state, DMA_state);
                signal nxt_state, c_state : states; -- next_state, current_state
 
                signal iPIOgo, iDMAgo : std_logic;
        begin
                -- generate next state decoder + output decoder
                gen_nxt_state: process(c_state, DMActrl_DMAen, DMActrl_dir, PIOreq, sDMARQ, DMATxFull, DMARxFull, PIOdone, DMAdone)
                begin
                        nxt_state <= c_state; -- initialy stay in current state
 
                        iPIOgo <= '0';
                        iDMAgo <= '0';
 
                        case c_state is
                                -- idle
                                when idle =>
                                        -- DMA transfer pending ?
                                        if ( (sDMARQ = '1') and (DMActrl_DMAen = '1') ) then
                                                if (( (DMActrl_dir = '1') and (DMATxFull = '1') ) or ( (DMActrl_dir = '0') and (DMARxFull = '0') )) then
                                                        nxt_state <= DMA_state;                        -- DMA transfer
                                                        iDMAgo    <= '1'; -- start DMA timing controller
                                                end if;
                                        -- PIO transfer pending ?
                                        elsif (PIOreq = '1') then
                                                nxt_state <= PIO_state;                            -- PIO transfer
                                                iPIOgo    <= '1';
                                        end if;
 
                                -- PIO transfer
                                when PIO_state =>
                                        if (PIOdone = '1') then
                                                        nxt_state <= idle;
                                        end if;
 
                                -- DMA transfer
                                when DMA_state =>
                                        if (DMAdone = '1') then
                                                nxt_state <= idle;
                                        end if;
 
                                when others =>
                                        nxt_state <= idle;                                   -- go to idle state
 
                        end case;
                end process gen_nxt_state;
 
                -- generate registers
                gen_regs: process(clk, nReset)
                begin
                        if (nReset = '0') then
                                c_state <= idle;
                                PIOgo <= '0';
                                DMAgo <= '0';
                        elsif (clk'event and clk = '1') then
                                if (rst = '1') then
                                        c_state <= idle;
                                        PIOgo <= '0';
                                        DMAgo <= '0';
                                else
                                        c_state <= nxt_state;
                                        PIOgo <= iPIOgo;
                                        DMAgo <= iDMAgo;
                                end if;
                        end if;
                end process gen_regs;
 
                -- generate PIOtip / DMAtip
                gen_tip: process(clk, nReset)
                begin
                        if (nReset = '0') then
                                PIOtip <= '0';
                                DMAtip <= '0';
                        elsif (clk'event and clk = '1') then
                                if (rst = '1') then
                                        PIOtip <= '0';
                                        DMAtip <= '0';
                                else
                                        PIOtip <= iPIOgo or (PIOtip and not PIOdone);
                                        DMAtip <= iDMAgo or (DMAtip and not ((DMAdone and DMActrl_dir) or (DMAdone and not sDMARQ and not DMActrl_dir)) );
                                end if;
                        end if;
                end process gen_tip;
        end block statemachine;
 
        --
        -- Hookup PIO controller
        --
        PIO_control: atahost_pio_controller
                generic map(
                        TWIDTH => TWIDTH,
                        PIO_mode0_T1 => PIO_mode0_T1,
                        PIO_mode0_T2 => PIO_mode0_T2,
                        PIO_mode0_T4 => PIO_mode0_T4,
                        PIO_mode0_Teoc => PIO_mode0_Teoc
                )
                port map(
                        clk    => clk,
                        nReset => nReset,
                        rst    => rst,
                        IDEctrl_IDEen => IDEctrl_IDEen,
                        IDEctrl_ppen  => IDEctrl_ppen,
                        IDEctrl_FATR0 => IDEctrl_FATR0,
                        IDEctrl_FATR1 => IDEctrl_FATR1,
                        cmdport_T1    => PIO_cmdport_T1,
                        cmdport_T2    => PIO_cmdport_T2,
                        cmdport_T4    => PIO_cmdport_T4,
                        cmdport_Teoc  => PIO_cmdport_Teoc,
                        cmdport_IORDYen => PIO_cmdport_IORDYen,
                        dport0_T1     => PIO_dport0_T1,
                        dport0_T2     => PIO_dport0_T2,
                        dport0_T4     => PIO_dport0_T4,
                        dport0_Teoc   => PIO_dport0_Teoc,
                        dport0_IORDYen => PIO_dport0_IORDYen,
                        dport1_T1     => PIO_dport1_T1,
                        dport1_T2     => PIO_dport1_T2,
                        dport1_T4     => PIO_dport1_T4,
                        dport1_Teoc   => PIO_dport1_Teoc,
                        dport1_IORDYen => PIO_dport1_IORDYen,
                        sel    => PIOsel,
                        ack    => PIOack,
                        a      => a,
                        we     => we,
                        d      => d(15 downto 0),
                        q      => PIOq,
                        PIOreq => PIOreq,
                        PPFull => PIOpp_full,
                        go     => PIOgo,
                        done   => PIOdone,
                        PIOa   => PIOa,
                        PIOd   => PIOd,
                        SelDev => SelDev,
                        DDi    => DDi,
                        DDoe   => PIOoe,
                        DIOR   => PIOdior,
                        DIOW   => PIOdiow,
                        IORDY  => sIORDY
                );
 
        --
        -- Hookup DMA access controller
        --
        DMA_control: atahost_dma_actrl
                generic map(
                        TWIDTH => TWIDTH,
                        DMA_mode0_Tm => DMA_mode0_Tm,
                        DMA_mode0_Td => DMA_mode0_Td,
                        DMA_mode0_Teoc => DMA_mode0_Teoc
                )
                port map(
                        clk    => clk,
                        nReset => nReset,
                        rst    => rst,
                        IDEctrl_rst    => IDEctrl_rst,
                        DMActrl_DMAen  => DMActrl_DMAen,
                        DMActrl_dir    => DMActrl_dir,
                        DMActrl_BeLeC0 => DMActrl_BeLeC0,
                        DMActrl_BeLeC1 => DMActrl_BeLeC1,
                        dev0_Td   => DMA_dev0_Td,
                        dev0_Tm   => DMA_dev0_Tm,
                        dev0_Teoc => DMA_dev0_Teoc,
                        dev1_Td   => DMA_dev1_Td,
                        dev1_Tm   => DMA_dev1_Tm,
                        dev1_Teoc => DMA_dev1_Teoc,
                        sel     => DMAsel,
                        ack     => DMAack,
                        we      => we,
                        TxD     => d,
                        TxFull  => DMATxFull,
                        RxQ     => DMAq,
                        RxFull  => DMARxFull,
                        RxEmpty => DMARxEmpty,
                        DMA_req => DMA_req,
                        DMA_ack => DMA_ack,
                        SelDev  => SelDev,
                        Go      => DMAgo,
                        Done    => DMAdone,
                        DDi     => DDi,
                        DDo     => DMAd,
                        DIOR    => DMAdior,
                        DIOW    => DMAdiow,
                        DMARQ   => sDMARQ
                );
end architecture structural;

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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec3/] [atahost_controller.vhd] - Blame information for rev 35

Line No.	Rev	Author	Line
1	27	rherveille	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- OpenCores IDE Controller ----`
4			`---- ATA/ATAPI-5 Host controller (OCIDEC-3) ----`
5			`---- ----`
6			`---- Author: Richard Herveille ----`
7			`---- richard@asics.ws ----`
8			`---- www.asics.ws ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2001, 2002 Richard Herveille ----`
13			`---- richard@asics.ws ----`
14			`---- ----`
15			`---- This source file may be used and distributed without ----`
16			`---- restriction provided that this copyright statement is not ----`
17			`---- removed from the file and that any derivative work contains ----`
18			`---- the original copyright notice and the associated disclaimer.----`
19			`---- ----`
20			---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
21			`---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----`
22			`---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
23			`---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----`
24			`---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
25			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----`
26			`---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----`
27			`---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----`
28			`---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----`
29			`---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
30			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----`
31			`---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
32			`---- POSSIBILITY OF SUCH DAMAGE. ----`
33			`---- ----`
34			`---------------------------------------------------------------------`
35
36			`-- rev.: 1.0 march 8th, 2001. Initial release`
37			`--`
38			`-- CVS Log`
39			`--`
40			`-- $Id: atahost_controller.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $`
41			`--`
42			`-- $Date: 2002-02-18 14:32:12 $`
43			`-- $Revision: 1.1 $`
44			`-- $Author: rherveille $`
45			`-- $Locker: $`
46			`-- $State: Exp $`
47			`--`
48			`-- Change History:`
49			`-- $Log: not supported by cvs2svn $`
50			`--`
51
52			`library ieee;`
53			`use ieee.std_logic_1164.all;`
54			`use ieee.std_logic_arith.all;`
55
56			`entity atahost_controller is`
57			`generic(`
58			`TWIDTH : natural := 8; -- counter width`
59
60			`-- PIO mode 0 settings (@100MHz clock)`
61			`PIO_mode0_T1 : natural := 6; -- 70ns`
62			`PIO_mode0_T2 : natural := 28; -- 290ns`
63			`PIO_mode0_T4 : natural := 2; -- 30ns`
64			`PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240`
65
66			`-- Multiword DMA mode 0 settings (@100MHz clock)`
67			`DMA_mode0_Tm : natural := 4; -- 50ns`
68			`DMA_mode0_Td : natural := 21; -- 215ns`
69			`DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215`
70			`);`
71			`port(`
72			`clk : in std_logic; -- master clock in`
73			`nReset : in std_logic := '1'; -- asynchronous active low reset`
74			`rst : in std_logic := '0'; -- synchronous active high reset`
75
76			`irq : out std_logic; -- interrupt request signal`
77
78			`-- control / registers`
79			`IDEctrl_IDEen,`
80			`IDEctrl_rst,`
81			`IDEctrl_ppen,`
82			`IDEctrl_FATR0,`
83			`IDEctrl_FATR1 : in std_logic; -- control register settings`
84
85			`a : in unsigned(3 downto 0); -- address input`
86			`d : in std_logic_vector(31 downto 0); -- data input`
87			`we : in std_logic; -- write enable input '1'=write, '0'=read`
88
89			`-- PIO registers`
90			`PIO_cmdport_T1,`
91			`PIO_cmdport_T2,`
92			`PIO_cmdport_T4,`
93			`PIO_cmdport_Teoc : in unsigned(7 downto 0);`
94			`PIO_cmdport_IORDYen : in std_logic; -- PIO compatible timing settings`
95
96			`PIO_dport0_T1,`
97			`PIO_dport0_T2,`
98			`PIO_dport0_T4,`
99			`PIO_dport0_Teoc : in unsigned(7 downto 0);`
100			`PIO_dport0_IORDYen : in std_logic; -- PIO data-port device0 timing settings`
101
102			`PIO_dport1_T1,`
103			`PIO_dport1_T2,`
104			`PIO_dport1_T4,`
105			`PIO_dport1_Teoc : in unsigned(7 downto 0);`
106			`PIO_dport1_IORDYen : in std_logic; -- PIO data-port device1 timing settings`
107
108			`PIOsel : in std_logic; -- PIO controller select`
109			`PIOack : out std_logic; -- PIO controller acknowledge`
110			`PIOq : out std_logic_vector(15 downto 0); -- PIO data out`
111			`PIOtip : buffer std_logic; -- PIO transfer in progress`
112			`PIOpp_full : out std_logic; -- PIO Write PingPong full`
113
114			`-- DMA registers`
115			`DMA_dev0_Td,`
116			`DMA_dev0_Tm,`
117			`DMA_dev0_Teoc : in unsigned(7 downto 0); -- DMA timing settings for device0`
118
119			`DMA_dev1_Td,`
120			`DMA_dev1_Tm,`
121			`DMA_dev1_Teoc : in unsigned(7 downto 0); -- DMA timing settings for device1`
122
123			`DMActrl_DMAen,`
124			`DMActrl_dir,`
125			`DMActrl_BeLeC0,`
126			`DMActrl_BeLeC1 : in std_logic; -- DMA settings`
127
128			`DMAsel : in std_logic; -- DMA controller select`
129			`DMAack : out std_logic; -- DMA controller acknowledge`
130			`DMAq : out std_logic_vector(31 downto 0); -- DMA data out`
131			`DMAtip : buffer std_logic; -- DMA transfer in progress`
132			`DMA_dmarq : out std_logic; -- Synchronized ATA DMARQ line`
133
134			`DMATxFull : buffer std_logic; -- DMA transmit buffer full`
135			`DMARxEmpty : buffer std_logic; -- DMA receive buffer empty`
136
137			`DMA_req : out std_logic; -- DMA request to external DMA engine`
138			`DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine`
139
140			`-- ATA signals`
141			`RESETn : out std_logic;`
142			`DDi : in std_logic_vector(15 downto 0);`
143			`DDo : out std_logic_vector(15 downto 0);`
144			`DDoe : out std_logic;`
145			`DA : out unsigned(2 downto 0);`
146			`CS0n : out std_logic;`
147			`CS1n : out std_logic;`
148
149			`DMARQ : in std_logic;`
150			`DMACKn : out std_logic;`
151			`DIORn : out std_logic;`
152			`DIOWn : out std_logic;`
153			`IORDY : in std_logic;`
154			`INTRQ : in std_logic`
155			`);`
156			`end entity atahost_controller;`
157
158			`architecture structural of atahost_controller is`
159			`--`
160			`-- component declarations`
161			`--`
162			`component atahost_pio_controller is`
163			`generic(`
164			`TWIDTH : natural := 8; -- counter width`
165
166			`-- PIO mode 0 settings (@100MHz clock)`
167			`PIO_mode0_T1 : natural := 6; -- 70ns`
168			`PIO_mode0_T2 : natural := 28; -- 290ns`
169			`PIO_mode0_T4 : natural := 2; -- 30ns`
170			`PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240`
171			`);`
172			`port(`
173			`clk : in std_logic; -- master clock in`
174			`nReset : in std_logic := '1'; -- asynchronous active low reset`
175			`rst : in std_logic := '0'; -- synchronous active high reset`
176
177			`-- control / registers`
178			`IDEctrl_IDEen,`
179			`IDEctrl_ppen,`
180			`IDEctrl_FATR0,`
181			`IDEctrl_FATR1 : in std_logic;`
182
183			`-- PIO registers`
184			`cmdport_T1,`
185			`cmdport_T2,`
186			`cmdport_T4,`
187			`cmdport_Teoc : in unsigned(7 downto 0);`
188			`cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing`
189
190			`dport0_T1,`
191			`dport0_T2,`
192			`dport0_T4,`
193			`dport0_Teoc : in unsigned(7 downto 0);`
194			`dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0`
195
196			`dport1_T1,`
197			`dport1_T2,`
198			`dport1_T4,`
199			`dport1_Teoc : in unsigned(7 downto 0);`
200			`dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1`
201
202			`sel : in std_logic; -- PIO controller selected`
203			`ack : out std_logic; -- PIO controller acknowledge`
204			`a : in unsigned(3 downto 0); -- lower address bits`
205			`we : in std_logic; -- write enable input`
206			`d : in std_logic_vector(15 downto 0);`
207			`q : out std_logic_vector(15 downto 0);`
208
209			`PIOreq : out std_logic; -- PIO transfer request`
210			`PPFull : out std_logic; -- PIO Write PingPong Full`
211			`go : in std_logic; -- start PIO transfer`
212			`done : buffer std_logic; -- done with PIO transfer`
213
214			`PIOa : out unsigned(3 downto 0); -- PIO address, address lines towards ATA devices`
215			`PIOd : out std_logic_vector(15 downto 0); -- PIO data, data towards ATA devices`
216
217			`SelDev : buffer std_logic; -- Selected Device, Dev-bit in ATA Device/Head register`
218
219			`DDi : in std_logic_vector(15 downto 0);`
220			`DDoe : buffer std_logic;`
221
222			`DIOR : buffer std_logic;`
223			`DIOW : buffer std_logic;`
224			`IORDY : in std_logic`
225			`);`
226			`end component atahost_pio_controller;`
227
228			`component atahost_dma_actrl is`
229			`generic(`
230			`TWIDTH : natural := 8; -- counter width`
231
232			`-- DMA mode 0 settings (@100MHz clock)`
233			`DMA_mode0_Tm : natural := 4; -- 50ns`
234			`DMA_mode0_Td : natural := 21; -- 215ns`
235			`DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215`
236			`);`
237			`port(`
238			`clk : in std_logic; -- master clock`
239			`nReset : in std_logic; -- asynchronous active low reset`
240			`rst : in std_logic; -- synchronous active high reset`
241
242			`IDEctrl_rst : in std_logic; -- IDE control register bit0, 'rst'`
243
244			`sel : in std_logic; -- DMA buffers selected`
245			`we : in std_logic; -- write enable input`
246			`ack : out std_logic; -- acknowledge output`
247
248			`dev0_Tm,`
249			`dev0_Td,`
250			`dev0_Teoc : in unsigned(7 downto 0); -- DMA mode timing device 0`
251			`dev1_Tm,`
252			`dev1_Td,`
253			`dev1_Teoc : in unsigned(7 downto 0); -- DMA mode timing device 1`
254
255			`DMActrl_DMAen,`
256			`DMActrl_dir,`
257			`DMActrl_BeLeC0,`
258			`DMActrl_BeLeC1 : in std_logic; -- control register settings`
259
260			`TxD : in std_logic_vector(31 downto 0); -- DMA transmit data`
261			`TxFull : buffer std_logic; -- DMA transmit buffer full`
262			`RxQ : out std_logic_vector(31 downto 0); -- DMA receive data`
263			`RxEmpty : buffer std_logic; -- DMA receive buffer empty`
264			`RxFull : out std_logic; -- DMA receive buffer full`
265			`DMA_req : out std_logic; -- DMA request to external DMA engine`
266			`DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine`
267
268			`DMARQ : in std_logic; -- ATA devices request DMA transfer`
269
270			`SelDev : in std_logic; -- Selected device`
271
272			`Go : in std_logic; -- Start transfer sequence`
273			`Done : out std_logic; -- Transfer sequence done`
274
275			`DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus`
276			`DDo : out std_logic_vector(15 downto 0); -- Data towards ATA DD bus`
277
278			`DIOR,`
279			`DIOW : buffer std_logic`
280			`);`
281			`end component atahost_dma_actrl;`
282
283			`--`
284			`-- signals`
285			`--`
286			`signal SelDev : std_logic; -- selected device`
287			`signal DMARxFull : std_logic; -- DMA receive buffer full`
288
289			`-- PIO / DMA signals`
290			`signal PIOgo, DMAgo : std_logic; -- start PIO / DMA timing controller`
291			`signal PIOdone, DMAdone : std_logic; -- PIO / DMA timing controller done`
292
293			`-- PIO signals`
294			`signal PIOdior, PIOdiow : std_logic;`
295			`signal PIOoe : std_logic;`
296
297			`-- PIO pingpong signals`
298			`signal PIOd : std_logic_vector(15 downto 0);`
299			`signal PIOa : unsigned(3 downto 0);`
300			`signal PIOreq : std_logic;`
301
302			`-- DMA signals`
303			`signal DMAd : std_logic_vector(15 downto 0);`
304			`signal DMAdior, DMAdiow : std_logic;`
305
306			`-- synchronized ATA inputs`
307			`signal sDMARQ, sIORDY : std_logic;`
308
309			`begin`
310
311			`--`
312			`-- synchronize incoming signals`
313			`--`
314			`synch_incoming: block`
315			`signal cDMARQ : std_logic; -- capture DMARQ`
316			`signal cIORDY : std_logic; -- capture IORDY`
317			`signal cINTRQ : std_logic; -- capture INTRQ`
318			`begin`
319			`process(clk)`
320			`begin`
321			`if (clk'event and clk = '1') then`
322			`cDMARQ <= DMARQ;`
323			`cIORDY <= IORDY;`
324			`cINTRQ <= INTRQ;`
325
326			`sDMARQ <= cDMARQ;`
327			`sIORDY <= cIORDY;`
328			`irq <= cINTRQ;`
329			`end if;`
330			`end process;`
331
332			`DMA_dmarq <= sDMARQ;`
333			`end block synch_incoming;`
334
335			`--`
336			`-- generate ATA signals`
337			`--`
338			`gen_ata_sigs: block`
339			`signal iDDo : std_logic_vector(15 downto 0);`
340			`begin`
341			`-- generate registers for ATA signals`
342			`gen_regs: process(clk, nReset)`
343			`begin`
344			`if (nReset = '0') then`
345			`RESETn <= '0';`
346			`DIORn <= '1';`
347			`DIOWn <= '1';`
348			`DA <= (others => '0');`
349			`CS0n <= '1';`
350			`CS1n <= '1';`
351			`DDo <= (others => '0');`
352			`DDoe <= '0';`
353			`DMACKn <= '1';`
354			`elsif (clk'event and clk = '1') then`
355			`if (rst = '1') then`
356			`RESETn <= '0';`
357			`DIORn <= '1';`
358			`DIOWn <= '1';`
359			`DA <= (others => '0');`
360			`CS0n <= '1';`
361			`CS1n <= '1';`
362			`DDo <= (others => '0');`
363			`DDoe <= '0';`
364			`DMACKn <= '1';`
365			`else`
366			`RESETn <= not IDEctrl_rst;`
367			`DA <= PIOa(2 downto 0);`
368			`CS0n <= not (not PIOa(3) and PIOtip); -- CS0 asserted when A(3) = '0', negate during DMA transfers`
369			`CS1n <= not ( PIOa(3) and PIOtip); -- CS1 asserted when A(3) = '1', negate during DMA transfers`
370
371			`if (PIOtip = '1') then`
372			`DDo <= PIOd;`
373			`DDoe <= PIOoe;`
374			`DIORn <= not PIOdior;`
375			`DIOWn <= not PIOdiow;`
376			`else`
377			`DDo <= DMAd;`
378			`DDoe <= DMActrl_dir and DMAtip;`
379			`DIORn <= not DMAdior;`
380			`DIOWn <= not DMAdiow;`
381			`end if;`
382
383			`DMACKn <= not DMAtip;`
384			`end if;`
385			`end if;`
386			`end process gen_regs;`
387			`end block gen_ata_sigs;`
388
389			`--`
390			`-- generate bus controller statemachine`
391			`--`
392			`statemachine: block`
393			`type states is (idle, PIO_state, DMA_state);`
394			`signal nxt_state, c_state : states; -- next_state, current_state`
395
396			`signal iPIOgo, iDMAgo : std_logic;`
397			`begin`
398			`-- generate next state decoder + output decoder`
399			`gen_nxt_state: process(c_state, DMActrl_DMAen, DMActrl_dir, PIOreq, sDMARQ, DMATxFull, DMARxFull, PIOdone, DMAdone)`
400			`begin`
401			`nxt_state <= c_state; -- initialy stay in current state`
402
403			`iPIOgo <= '0';`
404			`iDMAgo <= '0';`
405
406			`case c_state is`
407			`-- idle`
408			`when idle =>`
409			`-- DMA transfer pending ?`
410			`if ( (sDMARQ = '1') and (DMActrl_DMAen = '1') ) then`
411			`if (( (DMActrl_dir = '1') and (DMATxFull = '1') ) or ( (DMActrl_dir = '0') and (DMARxFull = '0') )) then`
412			`nxt_state <= DMA_state; -- DMA transfer`
413			`iDMAgo <= '1'; -- start DMA timing controller`
414			`end if;`
415			`-- PIO transfer pending ?`
416			`elsif (PIOreq = '1') then`
417			`nxt_state <= PIO_state; -- PIO transfer`
418			`iPIOgo <= '1';`
419			`end if;`
420
421			`-- PIO transfer`
422			`when PIO_state =>`
423			`if (PIOdone = '1') then`
424			`nxt_state <= idle;`
425			`end if;`
426
427			`-- DMA transfer`
428			`when DMA_state =>`
429			`if (DMAdone = '1') then`
430			`nxt_state <= idle;`
431			`end if;`
432
433			`when others =>`
434			`nxt_state <= idle; -- go to idle state`
435
436			`end case;`
437			`end process gen_nxt_state;`
438
439			`-- generate registers`
440			`gen_regs: process(clk, nReset)`
441			`begin`
442			`if (nReset = '0') then`
443			`c_state <= idle;`
444			`PIOgo <= '0';`
445			`DMAgo <= '0';`
446			`elsif (clk'event and clk = '1') then`
447			`if (rst = '1') then`
448			`c_state <= idle;`
449			`PIOgo <= '0';`
450			`DMAgo <= '0';`
451			`else`
452			`c_state <= nxt_state;`
453			`PIOgo <= iPIOgo;`
454			`DMAgo <= iDMAgo;`
455			`end if;`
456			`end if;`
457			`end process gen_regs;`
458
459			`-- generate PIOtip / DMAtip`
460			`gen_tip: process(clk, nReset)`
461			`begin`
462			`if (nReset = '0') then`
463			`PIOtip <= '0';`
464			`DMAtip <= '0';`
465			`elsif (clk'event and clk = '1') then`
466			`if (rst = '1') then`
467			`PIOtip <= '0';`
468			`DMAtip <= '0';`
469			`else`
470			`PIOtip <= iPIOgo or (PIOtip and not PIOdone);`
471			`DMAtip <= iDMAgo or (DMAtip and not ((DMAdone and DMActrl_dir) or (DMAdone and not sDMARQ and not DMActrl_dir)) );`
472			`end if;`
473			`end if;`
474			`end process gen_tip;`
475			`end block statemachine;`
476
477			`--`
478			`-- Hookup PIO controller`
479			`--`
480			`PIO_control: atahost_pio_controller`
481			`generic map(`
482			`TWIDTH => TWIDTH,`
483			`PIO_mode0_T1 => PIO_mode0_T1,`
484			`PIO_mode0_T2 => PIO_mode0_T2,`
485			`PIO_mode0_T4 => PIO_mode0_T4,`
486			`PIO_mode0_Teoc => PIO_mode0_Teoc`
487			`)`
488			`port map(`
489			`clk => clk,`
490			`nReset => nReset,`
491			`rst => rst,`
492			`IDEctrl_IDEen => IDEctrl_IDEen,`
493			`IDEctrl_ppen => IDEctrl_ppen,`
494			`IDEctrl_FATR0 => IDEctrl_FATR0,`
495			`IDEctrl_FATR1 => IDEctrl_FATR1,`
496			`cmdport_T1 => PIO_cmdport_T1,`
497			`cmdport_T2 => PIO_cmdport_T2,`
498			`cmdport_T4 => PIO_cmdport_T4,`
499			`cmdport_Teoc => PIO_cmdport_Teoc,`
500			`cmdport_IORDYen => PIO_cmdport_IORDYen,`
501			`dport0_T1 => PIO_dport0_T1,`
502			`dport0_T2 => PIO_dport0_T2,`
503			`dport0_T4 => PIO_dport0_T4,`
504			`dport0_Teoc => PIO_dport0_Teoc,`
505			`dport0_IORDYen => PIO_dport0_IORDYen,`
506			`dport1_T1 => PIO_dport1_T1,`
507			`dport1_T2 => PIO_dport1_T2,`
508			`dport1_T4 => PIO_dport1_T4,`
509			`dport1_Teoc => PIO_dport1_Teoc,`
510			`dport1_IORDYen => PIO_dport1_IORDYen,`
511			`sel => PIOsel,`
512			`ack => PIOack,`
513			`a => a,`
514			`we => we,`
515			`d => d(15 downto 0),`
516			`q => PIOq,`
517			`PIOreq => PIOreq,`
518			`PPFull => PIOpp_full,`
519			`go => PIOgo,`
520			`done => PIOdone,`
521			`PIOa => PIOa,`
522			`PIOd => PIOd,`
523			`SelDev => SelDev,`
524			`DDi => DDi,`
525			`DDoe => PIOoe,`
526			`DIOR => PIOdior,`
527			`DIOW => PIOdiow,`
528			`IORDY => sIORDY`
529			`);`
530
531			`--`
532			`-- Hookup DMA access controller`
533			`--`
534			`DMA_control: atahost_dma_actrl`
535			`generic map(`
536			`TWIDTH => TWIDTH,`
537			`DMA_mode0_Tm => DMA_mode0_Tm,`
538			`DMA_mode0_Td => DMA_mode0_Td,`
539			`DMA_mode0_Teoc => DMA_mode0_Teoc`
540			`)`
541			`port map(`
542			`clk => clk,`
543			`nReset => nReset,`
544			`rst => rst,`
545			`IDEctrl_rst => IDEctrl_rst,`
546			`DMActrl_DMAen => DMActrl_DMAen,`
547			`DMActrl_dir => DMActrl_dir,`
548			`DMActrl_BeLeC0 => DMActrl_BeLeC0,`
549			`DMActrl_BeLeC1 => DMActrl_BeLeC1,`
550			`dev0_Td => DMA_dev0_Td,`
551			`dev0_Tm => DMA_dev0_Tm,`
552			`dev0_Teoc => DMA_dev0_Teoc,`
553			`dev1_Td => DMA_dev1_Td,`
554			`dev1_Tm => DMA_dev1_Tm,`
555			`dev1_Teoc => DMA_dev1_Teoc,`
556			`sel => DMAsel,`
557			`ack => DMAack,`
558			`we => we,`
559			`TxD => d,`
560			`TxFull => DMATxFull,`
561			`RxQ => DMAq,`
562			`RxFull => DMARxFull,`
563			`RxEmpty => DMARxEmpty,`
564			`DMA_req => DMA_req,`
565			`DMA_ack => DMA_ack,`
566			`SelDev => SelDev,`
567			`Go => DMAgo,`
568			`Done => DMAdone,`
569			`DDi => DDi,`
570			`DDo => DMAd,`
571			`DIOR => DMAdior,`
572			`DIOW => DMAdiow,`
573			`DMARQ => sDMARQ`
574			`);`
575			`end architecture structural;`