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rherveille |
---------------------------------------------------------------------
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---- ----
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---- OpenCores IDE Controller ----
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---- DMA (single- and multiword) mode access controller ----
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---- ----
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---- Author: Richard Herveille ----
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---- richard@asics.ws ----
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---- www.asics.ws ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2001, 2002 Richard Herveille ----
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---- richard@asics.ws ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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-- rev.: 1.0 march 9th, 2001. Initial release
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--
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-- CVS Log
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--
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-- $Id: atahost_dma_actrl.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $
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--
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-- $Date: 2002-02-18 14:32:12 $
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-- $Revision: 1.1 $
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-- $Author: rherveille $
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-- $Locker: $
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-- $State: Exp $
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--
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-- Change History:
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-- $Log: not supported by cvs2svn $
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--
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--
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-- Host accesses to DMA ports are 32bit wide. Accesses are made by 2 consecutive 16bit accesses to the ATA
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-- device's DataPort. The MSB HostData(31:16) is transfered first, then the LSB HostData(15:0) is transfered.
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--
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---------------------------
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-- DMA Access Controller --
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---------------------------
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity atahost_dma_actrl is
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generic(
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TWIDTH : natural := 8; -- counter width
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-- DMA mode 0 settings (@100MHz clock)
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DMA_mode0_Tm : natural := 4; -- 50ns
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DMA_mode0_Td : natural := 21; -- 215ns
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DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
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);
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port(
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clk : in std_logic; -- master clock
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nReset : in std_logic; -- asynchronous active low reset
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rst : in std_logic; -- synchronous active high reset
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IDEctrl_rst : in std_logic; -- IDE control register bit0, 'rst'
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sel : in std_logic; -- DMA buffers selected
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we : in std_logic; -- write enable input
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ack : out std_logic; -- acknowledge output
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dev0_Tm,
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dev0_Td,
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dev0_Teoc : in unsigned(7 downto 0); -- DMA mode timing device 0
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dev1_Tm,
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dev1_Td,
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dev1_Teoc : in unsigned(7 downto 0); -- DMA mode timing device 1
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DMActrl_DMAen,
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DMActrl_dir,
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DMActrl_BeLeC0,
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DMActrl_BeLeC1 : in std_logic; -- control register settings
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TxD : in std_logic_vector(31 downto 0); -- DMA transmit data
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TxFull : buffer std_logic; -- DMA transmit buffer full
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RxQ : out std_logic_vector(31 downto 0); -- DMA receive data
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RxEmpty : buffer std_logic; -- DMA receive buffer empty
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RxFull : out std_logic; -- DMA receive buffer full
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DMA_req : out std_logic; -- DMA request to external DMA engine
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DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine
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DMARQ : in std_logic; -- ATA devices request DMA transfer
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SelDev : in std_logic; -- Selected device
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Go : in std_logic; -- Start transfer sequence
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Done : out std_logic; -- Transfer sequence done
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DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus
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DDo : out std_logic_vector(15 downto 0); -- Data towards ATA DD bus
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DIOR,
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DIOW : buffer std_logic
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);
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end entity atahost_dma_actrl;
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architecture structural of atahost_dma_actrl is
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--
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-- component declarations
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--
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component atahost_dma_tctrl is
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generic(
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TWIDTH : natural := 8; -- counter width
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-- DMA mode 0 settings (@100MHz clock)
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DMA_mode0_Tm : natural := 6; -- 70ns
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DMA_mode0_Td : natural := 28; -- 290ns
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DMA_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
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);
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port(
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clk : in std_logic; -- master clock
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nReset : in std_logic; -- asynchronous active low reset
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rst : in std_logic; -- synchronous active high reset
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-- timing register settings
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Tm : in unsigned(TWIDTH -1 downto 0); -- Tm time (in clk-ticks)
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Td : in unsigned(TWIDTH -1 downto 0); -- Td time (in clk-ticks)
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Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time
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-- control signals
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go : in std_logic; -- DMA controller selected (strobe signal)
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we : in std_logic; -- DMA direction '1' = write, '0' = read
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-- return signals
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done : out std_logic; -- finished cycle
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dstrb : out std_logic; -- data strobe
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-- ATA signals
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DIOR, -- IOread signal, active high
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DIOW : buffer std_logic -- IOwrite signal, active high
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);
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end component atahost_dma_tctrl;
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component atahost_reg_buf is
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generic (
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WIDTH : natural := 8
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);
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port(
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clk : in std_logic;
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nReset : in std_logic;
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rst : in std_logic;
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D : in std_logic_vector(WIDTH -1 downto 0);
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Q : out std_logic_vector(WIDTH -1 downto 0);
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rd : in std_logic;
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wr : in std_logic;
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valid : buffer std_logic
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);
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end component atahost_reg_buf;
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component atahost_fifo is
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generic(
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DEPTH : natural := 32; -- fifo depth
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SIZE : natural := 32 -- data width
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);
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port(
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clk : in std_logic; -- master clock in
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nReset : in std_logic := '1'; -- asynchronous active low reset
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rst : in std_logic := '0'; -- synchronous active high reset
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rreq : in std_logic; -- read request
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wreq : in std_logic; -- write request
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empty : out std_logic; -- fifo empty
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full : out std_logic; -- fifo full
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D : in std_logic_vector(SIZE -1 downto 0); -- data input
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Q : out std_logic_vector(SIZE -1 downto 0) -- data output
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);
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end component atahost_fifo;
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signal Tdone, Tfw : std_logic;
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signal RxWr, TxRd : std_logic;
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signal dstrb, rd_dstrb, wr_dstrb : std_logic;
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signal TxbufQ, RxbufD : std_logic_vector(31 downto 0);
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begin
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-- note: *fw = *first_word, *lw = *last_word
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--
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-- generate DDi/DDo controls
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--
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gen_DMA_sigs: block
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signal writeDfw, writeDlw : std_logic_vector(15 downto 0);
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signal readDfw, readDlw : std_logic_vector(15 downto 0);
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signal BeLeC : std_logic; -- BigEndian <-> LittleEndian conversion
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begin
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-- generate byte_swap signal
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BeLeC <= (not SelDev and DMActrl_BeLeC0) or (SelDev and DMActrl_BeLeC1);
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-- generate Tfw (Transfering first word)
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gen_Tfw: process(clk, nReset)
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begin
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if (nReset = '0') then
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Tfw <= '0';
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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Tfw <= '0';
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else
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Tfw <= go or (Tfw and not Tdone);
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end if;
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end if;
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end process gen_Tfw;
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-- transmit data part
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gen_writed_pipe:process(clk)
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begin
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if (clk'event and clk = '1') then
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if (TxRd = '1') then -- reload registers
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if (BeLeC = '1') then -- Do big<->little endian conversion
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writeDfw(15 downto 8) <= TxbufQ( 7 downto 0); -- TxbufQ = data from transmit buffer
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writeDfw( 7 downto 0) <= TxbufQ(15 downto 8);
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writeDlw(15 downto 8) <= TxbufQ(23 downto 16);
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writeDlw( 7 downto 0) <= TxbufQ(31 downto 24);
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else -- don't do big<->little endian conversion
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writeDfw <= TxbufQ(31 downto 16);
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writeDlw <= TxbufQ(15 downto 0);
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end if;
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elsif (wr_dstrb = '1') then -- next word to transfer
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writeDfw <= writeDlw;
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end if;
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end if;
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end process gen_writed_pipe;
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DDo <= writeDfw; -- assign DMA data out
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-- generate transmit register read request
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gen_Tx_rreq: process(clk, nReset)
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begin
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if (nReset = '0') then
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TxRd <= '0';
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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TxRd <= '0';
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else
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TxRd <= go and DMActrl_dir;
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end if;
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end if;
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end process gen_Tx_rreq;
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-- receive
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gen_readd_pipe:process(clk)
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begin
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if (clk'event and clk = '1') then
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if (rd_dstrb = '1') then
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readDfw <= readDlw; -- shift previous read word to msb
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if (BeLeC = '1') then -- swap bytes
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readDlw(15 downto 8) <= DDi( 7 downto 0);
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readDlw( 7 downto 0) <= DDi(15 downto 8);
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else -- don't swap bytes
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readDlw <= DDi;
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end if;
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end if;
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end if;
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end process gen_readd_pipe;
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-- RxD = data to receive buffer
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RxbufD <= (readDfw & readDlw) when (BeLeC = '0') else (readDlw & readDfw);
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-- generate receive register write request
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gen_Rx_wreq: process(clk, nReset)
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begin
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if (nReset = '0') then
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RxWr <= '0';
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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RxWr <= '0';
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else
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RxWr <= not Tfw and rd_dstrb;
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end if;
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end if;
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end process gen_Rx_wreq;
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end block gen_DMA_sigs;
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--
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-- Hookup DMA read / write buffers
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--
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gen_DMAbuf: block
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signal DMArst : std_logic;
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signal RxRd, TxWr : std_logic;
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signal iRxEmpty : std_logic;
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begin
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-- generate DMA reset signal
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DMArst <= rst or IDEctrl_rst;
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Txbuf: atahost_reg_buf
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generic map (WIDTH => 32)
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port map (
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clk => clk,
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nReset => nReset,
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rst => DMArst,
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D => TxD,
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Q => TxbufQ,
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rd => TxRd,
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wr => TxWr,
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valid => TxFull
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);
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Rxbuf: atahost_fifo
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generic map (DEPTH => 7, SIZE => 32)
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port map (
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clk => clk,
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nReset => nReset,
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rst => DMArst,
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D => RxbufD,
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Q => RxQ,
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rreq => RxRd,
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wreq => RxWr,
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empty => iRxEmpty,
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full => RxFull
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);
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RxEmpty <= iRxEmpty; -- avoid 'cannot associate OUT port with BUFFER port' error
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--
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-- generate DMA buffer access signals
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--
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RxRd <= sel and not we and not RxEmpty;
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TxWr <= sel and we and not TxFull;
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ack <= RxRd or TxWr; -- DMA buffer access acknowledge
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end block gen_DMAbuf;
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--
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-- generate request signal for external DMA engine
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--
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gen_DMA_req: block
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signal hgo : std_logic;
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signal iDMA_req : std_logic;
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signal request : std_logic;
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begin
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-- generate hold-go
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|
|
gen_hgo : process(clk, nReset)
|
360 |
|
|
begin
|
361 |
|
|
if (nReset = '0') then
|
362 |
|
|
hgo <= '0';
|
363 |
|
|
elsif (clk'event and clk = '1') then
|
364 |
|
|
if (rst = '1') then
|
365 |
|
|
hgo <= '0';
|
366 |
|
|
else
|
367 |
|
|
hgo <= go or (hgo and not (wr_dstrb and not Tfw) and DMActrl_dir);
|
368 |
|
|
end if;
|
369 |
|
|
end if;
|
370 |
|
|
end process gen_hgo;
|
371 |
|
|
|
372 |
|
|
request <= (DMActrl_dir and DMARQ and not TxFull and not hgo) or not RxEmpty;
|
373 |
|
|
process(clk, nReset)
|
374 |
|
|
begin
|
375 |
|
|
if (nReset = '0') then
|
376 |
|
|
iDMA_req <= '0';
|
377 |
|
|
elsif (clk'event and clk = '1') then
|
378 |
|
|
if (rst = '1') then
|
379 |
|
|
iDMA_req <= '0';
|
380 |
|
|
else
|
381 |
|
|
iDMA_req <= DMActrl_DMAen and not DMA_ack and (request or iDMA_req);
|
382 |
|
|
-- DMA_req <= (DMActrl_DMAen and DMActrl_dir and DMARQ and not TxFull and not hgo) or not RxEmpty;
|
383 |
|
|
end if;
|
384 |
|
|
end if;
|
385 |
|
|
end process;
|
386 |
|
|
DMA_req <= iDMA_req;
|
387 |
|
|
end block gen_DMA_req;
|
388 |
|
|
|
389 |
|
|
|
390 |
|
|
--
|
391 |
|
|
-- DMA timing controller
|
392 |
|
|
--
|
393 |
|
|
DMA_timing_ctrl: block
|
394 |
|
|
signal Tm, Td, Teoc, Tdmack_ext : unsigned(TWIDTH -1 downto 0);
|
395 |
|
|
signal dTfw, igo : std_logic;
|
396 |
|
|
begin
|
397 |
|
|
--
|
398 |
|
|
-- generate internal GO signal
|
399 |
|
|
--
|
400 |
|
|
gen_igo : process(clk, nReset)
|
401 |
|
|
begin
|
402 |
|
|
if (nReset = '0') then
|
403 |
|
|
igo <= '0';
|
404 |
|
|
dTfw <= '0';
|
405 |
|
|
elsif (clk'event and clk = '1') then
|
406 |
|
|
if (rst = '1') then
|
407 |
|
|
igo <= '0';
|
408 |
|
|
dTfw <= '0';
|
409 |
|
|
else
|
410 |
|
|
igo <= go or (not Tfw and dTfw);
|
411 |
|
|
dTfw <= Tfw;
|
412 |
|
|
end if;
|
413 |
|
|
end if;
|
414 |
|
|
end process gen_igo;
|
415 |
|
|
|
416 |
|
|
--
|
417 |
|
|
-- select timing settings for the addressed device
|
418 |
|
|
--
|
419 |
|
|
sel_dev_t: process(clk)
|
420 |
|
|
begin
|
421 |
|
|
if (clk'event and clk = '1') then
|
422 |
|
|
if (SelDev = '1') then -- device1 selected
|
423 |
|
|
Tm <= dev1_Tm;
|
424 |
|
|
Td <= dev1_Td;
|
425 |
|
|
Teoc <= dev1_Teoc;
|
426 |
|
|
else -- device0 selected
|
427 |
|
|
Tm <= dev0_Tm;
|
428 |
|
|
Td <= dev0_Td;
|
429 |
|
|
Teoc <= dev0_Teoc;
|
430 |
|
|
end if;
|
431 |
|
|
end if;
|
432 |
|
|
end process sel_dev_t;
|
433 |
|
|
|
434 |
|
|
--
|
435 |
|
|
-- hookup timing controller
|
436 |
|
|
--
|
437 |
|
|
DMA_timing_ctrl: atahost_dma_tctrl
|
438 |
|
|
generic map (
|
439 |
|
|
TWIDTH => TWIDTH,
|
440 |
|
|
DMA_mode0_Tm => DMA_mode0_Tm,
|
441 |
|
|
DMA_mode0_Td => DMA_mode0_Td,
|
442 |
|
|
DMA_mode0_Teoc => DMA_mode0_Teoc
|
443 |
|
|
)
|
444 |
|
|
port map (
|
445 |
|
|
clk => clk,
|
446 |
|
|
nReset => nReset,
|
447 |
|
|
rst => rst,
|
448 |
|
|
Tm => Tm,
|
449 |
|
|
Td => Td,
|
450 |
|
|
Teoc => Teoc,
|
451 |
|
|
go => igo,
|
452 |
|
|
we => DMActrl_dir,
|
453 |
|
|
done => Tdone,
|
454 |
|
|
dstrb => dstrb,
|
455 |
|
|
DIOR => dior,
|
456 |
|
|
DIOW => diow
|
457 |
|
|
);
|
458 |
|
|
|
459 |
|
|
done <= Tdone and not Tfw; -- done transfering last word
|
460 |
|
|
rd_dstrb <= dstrb and not DMActrl_dir; -- read data strobe
|
461 |
|
|
wr_dstrb <= dstrb and DMActrl_dir; -- write data strobe
|
462 |
|
|
end block DMA_timing_ctrl;
|
463 |
|
|
|
464 |
|
|
end architecture structural;
|
465 |
|
|
|