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rherveille |
---------------------------------------------------------------------
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---- ----
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---- OpenCores IDE Controller ----
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---- synchronous single clock fifo, uses LFSR pointers ----
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---- ----
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---- Author: Richard Herveille ----
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---- richard@asics.ws ----
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---- www.asics.ws ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2001, 2002 Richard Herveille ----
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---- richard@asics.ws ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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-- rev.: 1.0 march 12th, 2001. Initial release
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--
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-- CVS Log
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--
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-- $Id: atahost_fifo.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $
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--
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-- $Date: 2002-02-18 14:32:12 $
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-- $Revision: 1.1 $
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-- $Author: rherveille $
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-- $Locker: $
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-- $State: Exp $
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--
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-- Change History:
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-- $Log: not supported by cvs2svn $
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity atahost_fifo is
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generic(
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DEPTH : natural := 31; -- fifo depth, this must be a number according to the following range
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-- 3, 7, 15, 31, 63 ... 65535
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SIZE : natural := 32 -- data width
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);
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port(
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clk : in std_logic; -- master clock in
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nReset : in std_logic := '1'; -- asynchronous active low reset
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rst : in std_logic := '0'; -- synchronous active high reset
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rreq : in std_logic; -- read request
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wreq : in std_logic; -- write request
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empty : out std_logic; -- fifo empty
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full : out std_logic; -- fifo full
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D : in std_logic_vector(SIZE -1 downto 0); -- data input
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Q : out std_logic_vector(SIZE -1 downto 0) -- data output
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);
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end entity atahost_fifo;
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architecture structural of atahost_fifo is
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--
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-- function declarations
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--
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function bitsize(n : in natural) return natural is
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variable tmp : unsigned(32 downto 1);
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variable cnt : integer;
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begin
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tmp := conv_unsigned(n, 32);
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cnt := 32;
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while ( (tmp(cnt) = '0') and (cnt > 0) ) loop
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cnt := cnt -1;
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end loop;
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return natural(cnt);
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end function bitsize;
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--
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-- component declarations
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--
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component atahost_lfsr is
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generic(
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TAPS : positive range 16 downto 3 :=8;
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OFFSET : natural := 0
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);
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port(
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clk : in std_logic; -- clock input
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ena : in std_logic; -- count enable
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nReset : in std_logic; -- asynchronous active low reset
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rst : in std_logic; -- synchronous active high reset
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Q : out unsigned(TAPS downto 1); -- count value
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Qprev : out unsigned(TAPS downto 1) -- previous count value
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);
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end component atahost_lfsr;
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constant ADEPTH : natural := bitsize(DEPTH);
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-- memory block
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type memory is array (DEPTH -1 downto 0) of std_logic_vector(SIZE -1 downto 0);
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-- shared variable mem : memory; -- VHDL'93 PREFERED
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signal mem : memory; -- VHDL'87
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-- address pointers
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signal wr_ptr, rd_ptr, dwr_ptr, drd_ptr : unsigned(ADEPTH -1 downto 0);
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begin
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-- generate write address; hookup write_pointer counter
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wr_ptr_lfsr: atahost_lfsr
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generic map(
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TAPS => ADEPTH,
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OFFSET => 0
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)
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port map(
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clk => clk,
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ena => wreq,
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nReset => nReset,
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rst => rst,
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Q => wr_ptr,
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Qprev => dwr_ptr
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);
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-- generate read address; hookup read_pointer counter
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rd_ptr_lfsr: atahost_lfsr
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generic map(
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TAPS => ADEPTH,
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OFFSET => 0
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)
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port map(
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clk => clk,
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ena => rreq,
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nReset => nReset,
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rst => rst,
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Q => rd_ptr,
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Qprev => drd_ptr
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);
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-- generate full/empty signal
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full <= '1' when (wr_ptr = drd_ptr) else '0';
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empty <= '1' when (rd_ptr = wr_ptr) else '0';
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-- generate memory structure
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gen_mem: process(clk)
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begin
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if (clk'event and clk = '1') then
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if (wreq = '1') then
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mem(conv_integer(wr_ptr)) <= D;
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end if;
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end if;
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end process gen_mem;
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Q <= mem(conv_integer(rd_ptr));
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end architecture structural;
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