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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec3/] [atahost_fifo.vhd] - Blame information for rev 35

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---------------------------------------------------------------------
----                                                             ----
----  OpenCores IDE Controller                                   ----
----  synchronous single clock fifo, uses LFSR pointers          ----
----                                                             ----
----  Author: Richard Herveille                                  ----
----          richard@asics.ws                                   ----
----          www.asics.ws                                       ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2001, 2002 Richard Herveille                  ----
----                          richard@asics.ws                   ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
----                                                             ----
---------------------------------------------------------------------
 
-- rev.: 1.0 march 12th, 2001. Initial release
--
--  CVS Log
--
--  $Id: atahost_fifo.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $
--
--  $Date: 2002-02-18 14:32:12 $
--  $Revision: 1.1 $
--  $Author: rherveille $
--  $Locker:  $
--  $State: Exp $
--
-- Change History:
--               $Log: not supported by cvs2svn $
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity atahost_fifo is
        generic(
                DEPTH : natural := 31;                      -- fifo depth, this must be a number according to the following range
                                                 -- 3, 7, 15, 31, 63 ... 65535
                SIZE : natural := 32                        -- data width
        );
        port(
                clk : in std_logic;                         -- master clock in
                nReset : in std_logic := '1';               -- asynchronous active low reset
                rst : in std_logic := '0';                  -- synchronous active high reset
 
                rreq : in std_logic;                        -- read request
                wreq : in std_logic;                        -- write request
 
                empty : out std_logic;                      -- fifo empty
                full : out std_logic;                       -- fifo full
 
                D : in std_logic_vector(SIZE -1 downto 0);  -- data input
                Q : out std_logic_vector(SIZE -1 downto 0)  -- data output
        );
end entity atahost_fifo;
 
architecture structural of atahost_fifo is
        --
        -- function declarations
        --
        function bitsize(n : in natural) return natural is
                variable tmp : unsigned(32 downto 1);
                variable cnt : integer;
        begin
                tmp := conv_unsigned(n, 32);
                cnt := 32;
 
                while ( (tmp(cnt) = '0') and (cnt > 0) ) loop
                        cnt := cnt -1;
                end loop;
 
                return natural(cnt);
        end function bitsize;
 
        --
        -- component declarations
        --
        component atahost_lfsr is
        generic(
                TAPS : positive range 16 downto 3 :=8;
                OFFSET : natural := 0
        );
        port(
                clk : in std_logic;                 -- clock input
                ena : in std_logic;                 -- count enable
                nReset : in std_logic;              -- asynchronous active low reset
                rst : in std_logic;                 -- synchronous active high reset
 
                Q : out unsigned(TAPS downto 1);    -- count value
                Qprev : out unsigned(TAPS downto 1) -- previous count value
        );
        end component atahost_lfsr;
 
        constant ADEPTH : natural := bitsize(DEPTH);
 
        -- memory block
        type memory is array (DEPTH -1 downto 0) of std_logic_vector(SIZE -1 downto 0);
--      shared variable mem : memory; -- VHDL'93 PREFERED
        signal mem : memory; -- VHDL'87
 
        -- address pointers
        signal wr_ptr, rd_ptr, dwr_ptr, drd_ptr : unsigned(ADEPTH -1 downto 0);
 
begin
        -- generate write address; hookup write_pointer counter
        wr_ptr_lfsr: atahost_lfsr
                generic map(
                        TAPS => ADEPTH,
                        OFFSET => 0
                )
                port map(
                        clk => clk,
                        ena => wreq,
                        nReset => nReset,
                        rst => rst,
                        Q => wr_ptr,
                        Qprev => dwr_ptr
                );
 
        -- generate read address; hookup read_pointer counter
        rd_ptr_lfsr: atahost_lfsr
                generic map(
                        TAPS => ADEPTH,
                        OFFSET => 0
                )
                port map(
                        clk => clk,
                        ena => rreq,
                        nReset => nReset,
                        rst => rst,
                        Q => rd_ptr,
                        Qprev => drd_ptr
                );
 
        -- generate full/empty signal
        full  <= '1' when (wr_ptr = drd_ptr) else '0';
        empty <= '1' when (rd_ptr = wr_ptr) else '0';
 
        -- generate memory structure
        gen_mem: process(clk)
        begin
                if (clk'event and clk = '1') then
                        if (wreq = '1') then
                                mem(conv_integer(wr_ptr)) <= D;
                        end if;
                end if;
        end process gen_mem;
        Q <= mem(conv_integer(rd_ptr));
end architecture structural;

Line No.	Rev	Author	Line
1	27	rherveille	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- OpenCores IDE Controller ----`
4			`---- synchronous single clock fifo, uses LFSR pointers ----`
5			`---- ----`
6			`---- Author: Richard Herveille ----`
7			`---- richard@asics.ws ----`
8			`---- www.asics.ws ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2001, 2002 Richard Herveille ----`
13			`---- richard@asics.ws ----`
14			`---- ----`
15			`---- This source file may be used and distributed without ----`
16			`---- restriction provided that this copyright statement is not ----`
17			`---- removed from the file and that any derivative work contains ----`
18			`---- the original copyright notice and the associated disclaimer.----`
19			`---- ----`
20			---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
21			`---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----`
22			`---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
23			`---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----`
24			`---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
25			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----`
26			`---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----`
27			`---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----`
28			`---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----`
29			`---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
30			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----`
31			`---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
32			`---- POSSIBILITY OF SUCH DAMAGE. ----`
33			`---- ----`
34			`---------------------------------------------------------------------`
35
36			`-- rev.: 1.0 march 12th, 2001. Initial release`
37			`--`
38			`-- CVS Log`
39			`--`
40			`-- $Id: atahost_fifo.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $`
41			`--`
42			`-- $Date: 2002-02-18 14:32:12 $`
43			`-- $Revision: 1.1 $`
44			`-- $Author: rherveille $`
45			`-- $Locker: $`
46			`-- $State: Exp $`
47			`--`
48			`-- Change History:`
49			`-- $Log: not supported by cvs2svn $`
50			`--`
51
52			`library ieee;`
53			`use ieee.std_logic_1164.all;`
54			`use ieee.std_logic_arith.all;`
55
56			`entity atahost_fifo is`
57			`generic(`
58			`DEPTH : natural := 31; -- fifo depth, this must be a number according to the following range`
59			`-- 3, 7, 15, 31, 63 ... 65535`
60			`SIZE : natural := 32 -- data width`
61			`);`
62			`port(`
63			`clk : in std_logic; -- master clock in`
64			`nReset : in std_logic := '1'; -- asynchronous active low reset`
65			`rst : in std_logic := '0'; -- synchronous active high reset`
66
67			`rreq : in std_logic; -- read request`
68			`wreq : in std_logic; -- write request`
69
70			`empty : out std_logic; -- fifo empty`
71			`full : out std_logic; -- fifo full`
72
73			`D : in std_logic_vector(SIZE -1 downto 0); -- data input`
74			`Q : out std_logic_vector(SIZE -1 downto 0) -- data output`
75			`);`
76			`end entity atahost_fifo;`
77
78			`architecture structural of atahost_fifo is`
79			`--`
80			`-- function declarations`
81			`--`
82			`function bitsize(n : in natural) return natural is`
83			`variable tmp : unsigned(32 downto 1);`
84			`variable cnt : integer;`
85			`begin`
86			`tmp := conv_unsigned(n, 32);`
87			`cnt := 32;`
88
89			`while ( (tmp(cnt) = '0') and (cnt > 0) ) loop`
90			`cnt := cnt -1;`
91			`end loop;`
92
93			`return natural(cnt);`
94			`end function bitsize;`
95
96			`--`
97			`-- component declarations`
98			`--`
99			`component atahost_lfsr is`
100			`generic(`
101			`TAPS : positive range 16 downto 3 :=8;`
102			`OFFSET : natural := 0`
103			`);`
104			`port(`
105			`clk : in std_logic; -- clock input`
106			`ena : in std_logic; -- count enable`
107			`nReset : in std_logic; -- asynchronous active low reset`
108			`rst : in std_logic; -- synchronous active high reset`
109
110			`Q : out unsigned(TAPS downto 1); -- count value`
111			`Qprev : out unsigned(TAPS downto 1) -- previous count value`
112			`);`
113			`end component atahost_lfsr;`
114
115			`constant ADEPTH : natural := bitsize(DEPTH);`
116
117			`-- memory block`
118			`type memory is array (DEPTH -1 downto 0) of std_logic_vector(SIZE -1 downto 0);`
119			`-- shared variable mem : memory; -- VHDL'93 PREFERED`
120			`signal mem : memory; -- VHDL'87`
121
122			`-- address pointers`
123			`signal wr_ptr, rd_ptr, dwr_ptr, drd_ptr : unsigned(ADEPTH -1 downto 0);`
124
125			`begin`
126			`-- generate write address; hookup write_pointer counter`
127			`wr_ptr_lfsr: atahost_lfsr`
128			`generic map(`
129			`TAPS => ADEPTH,`
130			`OFFSET => 0`
131			`)`
132			`port map(`
133			`clk => clk,`
134			`ena => wreq,`
135			`nReset => nReset,`
136			`rst => rst,`
137			`Q => wr_ptr,`
138			`Qprev => dwr_ptr`
139			`);`
140
141			`-- generate read address; hookup read_pointer counter`
142			`rd_ptr_lfsr: atahost_lfsr`
143			`generic map(`
144			`TAPS => ADEPTH,`
145			`OFFSET => 0`
146			`)`
147			`port map(`
148			`clk => clk,`
149			`ena => rreq,`
150			`nReset => nReset,`
151			`rst => rst,`
152			`Q => rd_ptr,`
153			`Qprev => drd_ptr`
154			`);`
155
156			`-- generate full/empty signal`
157			`full <= '1' when (wr_ptr = drd_ptr) else '0';`
158			`empty <= '1' when (rd_ptr = wr_ptr) else '0';`
159
160			`-- generate memory structure`
161			`gen_mem: process(clk)`
162			`begin`
163			`if (clk'event and clk = '1') then`
164			`if (wreq = '1') then`
165			`mem(conv_integer(wr_ptr)) <= D;`
166			`end if;`
167			`end if;`
168			`end process gen_mem;`
169			`Q <= mem(conv_integer(rd_ptr));`
170			`end architecture structural;`

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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec3/] [atahost_fifo.vhd] - Blame information for rev 35