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rherveille |
---------------------------------------------------------------------
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---- ----
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---- OpenCores IDE Controller ----
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---- Linear Feedback Shift Register ----
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---- ----
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---- Author: Richard Herveille ----
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---- richard@asics.ws ----
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---- www.asics.ws ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2001, 2002 Richard Herveille ----
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---- richard@asics.ws ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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-- rev.: 1.0 march 12th, 2001. Initial release
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--
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-- CVS Log
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--
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-- $Id: atahost_lfsr.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $
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--
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-- $Date: 2002-02-18 14:32:12 $
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-- $Revision: 1.1 $
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-- $Author: rherveille $
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-- $Locker: $
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-- $State: Exp $
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--
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-- Change History:
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-- $Log: not supported by cvs2svn $
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity atahost_lfsr is
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generic(
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TAPS : positive range 16 downto 3 :=8;
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OFFSET : natural := 0
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);
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port(
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clk : in std_logic; -- clock input
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ena : in std_logic; -- count enable
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nReset : in std_logic; -- asynchronous active low reset
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rst : in std_logic; -- synchronous active high reset
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Q : out unsigned(TAPS downto 1); -- count value
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Qprev : out unsigned(TAPS downto 1) -- previous count value
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);
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end entity atahost_lfsr;
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architecture dataflow of atahost_lfsr is
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function lsb(tap : positive range 16 downto 3; Q : unsigned(TAPS downto 1) ) return std_logic is
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begin
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case tap is
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when 3 =>
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return Q(3) xnor Q(2);
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when 4 =>
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return Q(4) xnor Q(3);
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when 5 =>
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return Q(5) xnor Q(3);
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when 6 =>
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return Q(6) xnor Q(5);
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when 7 =>
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return Q(7) xnor Q(6);
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when 8 =>
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return (Q(8) xnor Q(6)) xnor (Q(5) xnor Q(4));
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when 9 =>
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return Q(9) xnor Q(5);
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when 10 =>
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return Q(10) xnor Q(7);
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when 11 =>
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return Q(11) xnor Q(9);
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when 12 =>
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return (Q(12) xnor Q(6)) xnor (Q(4) xnor Q(1));
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when 13 =>
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return (Q(13) xnor Q(4)) xnor (Q(3) xnor Q(1));
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when 14 =>
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return (Q(14) xnor Q(5)) xnor (Q(3) xnor Q(1));
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when 15 =>
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return Q(15) xnor Q(14);
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when 16 =>
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return (Q(16) xnor Q(15)) xnor (Q(13) xnor Q(4));
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end case;
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end function lsb;
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signal msb : std_logic;
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signal iQ : unsigned(TAPS downto 1);
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begin
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--
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-- generate register
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--
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gen_regs: process(clk, nReset)
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variable tmpQ : unsigned(TAPS downto 1);
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variable tmpmsb : std_logic;
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begin
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tmpQ := (others => '0');
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tmpmsb := '1';
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for n in 1 to offset loop
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tmpQ := (tmpQ(TAPS -1 downto 1) & lsb(TAPS, tmpQ) );
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tmpmsb := tmpQ(TAPS);
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end loop;
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if (nReset = '0') then
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iQ <= tmpQ;
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msb <= tmpmsb;
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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iQ <= tmpQ;
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msb <= tmpmsb;
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elsif (ena = '1') then
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iQ <= (iQ(TAPS -1 downto 1) & lsb(TAPS, iq) );
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msb <= iQ(TAPS);
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end if;
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end if;
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end process gen_regs;
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-- assign outputs
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Q <= iQ;
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Qprev <= (msb & iQ(TAPS downto 2));
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end architecture dataflow;
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