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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec3/] [atahost_pio_actrl.vhd] - Blame information for rev 33

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1 27 rherveille
---------------------------------------------------------------------
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----                                                             ----
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----  OpenCores IDE Controller                                   ----
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----  PIO Access Controller (common for OCIDEC 2 and above)      ----
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----                                                             ----
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----  Author: Richard Herveille                                  ----
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----          richard@asics.ws                                   ----
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----          www.asics.ws                                       ----
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----                                                             ----
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---------------------------------------------------------------------
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----                                                             ----
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---- Copyright (C) 2001, 2002 Richard Herveille                  ----
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----                          richard@asics.ws                   ---
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----                                                             ----
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---- This source file may be used and distributed without        ----
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---- restriction provided that this copyright statement is not   ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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----                                                             ----
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----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
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---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
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---- POSSIBILITY OF SUCH DAMAGE.                                 ----
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----                                                             ----
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---------------------------------------------------------------------
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-- rev.: 1.0 march 9th, 2001
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-- rev.: 1.0a april 12th, 2001 Removed references to records.vhd
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--
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--
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--  CVS Log
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--
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--  $Id: atahost_pio_actrl.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $
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--
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--  $Date: 2002-02-18 14:32:12 $
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--  $Revision: 1.1 $
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--  $Author: rherveille $
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--  $Locker:  $
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--  $State: Exp $
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--
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-- Change History:
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--               $Log: not supported by cvs2svn $
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--
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---------------------------
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-- PIO Access controller --
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---------------------------
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity atahost_pio_actrl is
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        generic(
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                TWIDTH : natural := 8;                     -- counter width
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                -- PIO mode 0 settings (@100MHz clock)
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                PIO_mode0_T1 : natural := 6;               -- 70ns
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                PIO_mode0_T2 : natural := 28;              -- 290ns
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                PIO_mode0_T4 : natural := 2;               -- 30ns
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                PIO_mode0_Teoc : natural := 23             -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
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        );
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        port(
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                clk    : in std_logic;                     -- master clock
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                nReset : in std_logic;                     -- asynchronous active low reset
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                rst    : in std_logic;                     -- synchronous active high reset
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                IDEctrl_FATR0,
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                IDEctrl_FATR1 : in std_logic;
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                cmdport_T1,
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                cmdport_T2,
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                cmdport_T4,
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                cmdport_Teoc : in unsigned(7 downto 0);
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                cmdport_IORDYen : in std_logic;            -- PIO command port / non-fast timing
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                dport0_T1,
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                dport0_T2,
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                dport0_T4,
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                dport0_Teoc : in unsigned(7 downto 0);
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                dport0_IORDYen : in std_logic;             -- PIO mode data-port / fast timing device 0
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                dport1_T1,
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                dport1_T2,
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                dport1_T4,
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                dport1_Teoc : in unsigned(7 downto 0);
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                dport1_IORDYen : in std_logic;             -- PIO mode data-port / fast timing device 1
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                SelDev : in std_logic;                     -- Selected device   
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                go   : in  std_logic;                      -- Start transfer sequence
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                done : out std_logic;                      -- Transfer sequence done
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                dir  : in  std_logic;                      -- Transfer direction '1'=write, '0'=read
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                a    : in  unsigned(3 downto 0);           -- PIO transfer address
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                q    : out std_logic_vector(15 downto 0);  -- Data read from ATA devices
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                DDi : in std_logic_vector(15 downto 0);    -- Data from ATA DD bus
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                oe  : buffer std_logic;                    -- DDbus output-enable signal
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                DIOR,
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                DIOW  : buffer std_logic;
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                IORDY : in std_logic
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        );
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end entity atahost_pio_actrl;
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architecture structural of atahost_pio_actrl is
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        --
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        -- Component declarations
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        --
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        component atahost_pio_tctrl is
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        generic(
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                TWIDTH : natural := 8;                   -- counter width
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                -- PIO mode 0 settings (@100MHz clock)
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                PIO_mode0_T1 : natural := 6;             -- 70ns
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                PIO_mode0_T2 : natural := 28;            -- 290ns
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                PIO_mode0_T4 : natural := 2;             -- 30ns
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                PIO_mode0_Teoc : natural := 23           -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
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        );
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        port(
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                clk    : in std_logic;                   -- master clock
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                nReset : in std_logic;                   -- asynchronous active low reset
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                rst    : in std_logic;                   -- synchronous active high reset
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                -- timing/control register settings
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                IORDY_en : in std_logic;                 -- use IORDY (or not)
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                T1   : in unsigned(TWIDTH -1 downto 0);  -- T1 time (in clk-ticks)
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                T2   : in unsigned(TWIDTH -1 downto 0);  -- T2 time (in clk-ticks)
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                T4   : in unsigned(TWIDTH -1 downto 0);  -- T4 time (in clk-ticks)
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                Teoc : in unsigned(TWIDTH -1 downto 0);  -- end of cycle time
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                -- control signals
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                go : in std_logic;                       -- PIO controller selected (strobe signal)
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                we : in std_logic;                       -- write enable signal. '0'=read from device, '1'=write to device
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                -- return signals
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                oe    : buffer std_logic;                -- output enable signal
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                done  : out std_logic;                   -- finished cycle
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                dstrb : out std_logic;                   -- data strobe, latch data (during read)
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                -- ATA signals
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                DIOR,                                    -- IOread signal, active high
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                DIOW  : buffer std_logic;                -- IOwrite signal, active high
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                IORDY : in std_logic                     -- IORDY signal
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        );
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        end component atahost_pio_tctrl;
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        signal dstrb : std_logic;
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        signal T1, T2, T4, Teoc : unsigned(TWIDTH -1 downto 0);
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        signal IORDYen : std_logic;
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begin
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        --
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        --------------------------
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        -- PIO transfer control --
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        --------------------------
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        --
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        -- capture ATA data for PIO access
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        gen_PIOq: process(clk)
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        begin
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                if (clk'event and clk = '1') then
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                        if (dstrb = '1') then
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                                q <= DDi;
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                        end if;
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                end if;
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        end process gen_PIOq;
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        --
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        -- PIO timing controllers
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        --
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        -- select timing settings for the addressed port
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        sel_port_t: process(clk, a, SelDev, IDEctrl_FATR1, IDEctrl_FATR0,
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                        cmdport_T1, cmdport_T2, cmdport_T4, cmdport_Teoc, cmdport_IORDYen,
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                        dport0_T1, dport0_T2, dport0_T4, dport0_Teoc, dport0_IORDYen,
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                        dport1_T1, dport1_T2, dport1_T4, dport1_Teoc, dport1_IORDYen)
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                variable Asel : std_logic; -- address selected
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                variable iT1, iT2, iT4, iTeoc : unsigned(TWIDTH -1 downto 0);
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                variable iIORDYen : std_logic;
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        begin
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                -- initially set timing registers to compatible timing
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                iT1      := cmdport_T1;
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                iT2      := cmdport_T2;
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                iT4      := cmdport_T4;
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                iTeoc    := cmdport_Teoc;
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                iIORDYen := cmdport_IORDYen;
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                -- detect data-port access
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                Asel := not a(3) and not a(2) and not a(1) and not a(0); -- data port
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                if (Asel = '1') then                                     -- data port selected, 16bit transfers
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                        if ((SelDev = '1') and (IDEctrl_FATR1 = '1')) then    -- data port1 selected and enabled ?
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                                iT1      := dport1_T1;
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                                iT2      := dport1_T2;
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                                iT4      := dport1_T4;
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                                iTeoc    := dport1_Teoc;
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                                iIORDYen := dport1_IORDYen;
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                        elsif((SelDev = '0') and (IDEctrl_FATR0 = '1')) then       -- data port0 selected and enabled ?
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                                iT1      := dport0_T1;
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                                iT2      := dport0_T2;
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                                iT4      := dport0_T4;
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                                iTeoc    := dport0_Teoc;
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                                iIORDYen := dport0_IORDYen;
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                        end if;
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                end if;
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                if (clk'event and clk = '1') then
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                        T1      <= iT1;
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                        T2      <= iT2;
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                        T4      <= iT4;
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                        Teoc    <= iTeoc;
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                        IORDYen <= iIORDYen;
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                end if;
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        end process sel_port_t;
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        --
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        -- hookup timing controller
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        --
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        PIO_timing_controller: atahost_pio_tctrl
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                generic map (
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                        TWIDTH => TWIDTH,
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                        PIO_mode0_T1 => PIO_mode0_T1,
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                        PIO_mode0_T2 => PIO_mode0_T2,
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                        PIO_mode0_T4 => PIO_mode0_T4,
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                        PIO_mode0_Teoc => PIO_mode0_Teoc
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                )
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                port map (
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                        clk => clk,
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                        nReset => nReset,
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                        rst => rst,
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                        IORDY_en => IORDYen,
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                        T1 => T1,
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                        T2 => T2,
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                        T4 => T4,
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                        Teoc => Teoc,
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                        go => go,
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                        we => dir,
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                        oe => oe,
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                        done => done,
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                        dstrb => dstrb,
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                        DIOR => dior,
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                        DIOW => diow,
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                        IORDY => IORDY
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                );
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end architecture structural;
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