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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec3/] [atahost_pio_tctrl.vhd] - Blame information for rev 33

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1 27 rherveille
---------------------------------------------------------------------
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----                                                             ----
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----  OpenCores ATA/ATAPI-5 Host Controller                      ----
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----  PIO Timing Controller (common for all OCIDEC cores)        ----
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----                                                             ----
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----  Author: Richard Herveille                                  ----
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----          richard@asics.ws                                   ----
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----          www.asics.ws                                       ----
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----                                                             ----
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---------------------------------------------------------------------
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----                                                             ----
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---- Copyright (C) 2001, 2002 Richard Herveille                  ----
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----                          richard@asics.ws                   ----
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----                                                             ----
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---- This source file may be used and distributed without        ----
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---- restriction provided that this copyright statement is not   ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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----                                                             ----
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----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
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---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
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---- POSSIBILITY OF SUCH DAMAGE.                                 ----
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----                                                             ----
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---------------------------------------------------------------------
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-- rev.: 1.0 march  7th, 2001. Initial release
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-- rev.: 1.1 July  11th, 2001. Changed 'igo' & 'hold_go' signal generation.
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--
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--
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--  CVS Log
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--
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--  $Id: atahost_pio_tctrl.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $
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--
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--  $Date: 2002-02-18 14:32:12 $
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--  $Revision: 1.1 $
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--  $Author: rherveille $
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--  $Locker:  $
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--  $State: Exp $
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--
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-- Change History:
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--               $Log: not supported by cvs2svn $
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--
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--
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--
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---------------------------
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-- PIO Timing controller --
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---------------------------
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--
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--
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-- Timing       PIO mode transfers
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----------------------------------------------
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-- T0:  cycle time
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-- T1:  address valid to DIOR-/DIOW-
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-- T2:  DIOR-/DIOW- pulse width
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-- T2i: DIOR-/DIOW- recovery time
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-- T3:  DIOW- data setup
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-- T4:  DIOW- data hold
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-- T5:  DIOR- data setup
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-- T6:  DIOR- data hold
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-- T9:  address hold from DIOR-/DIOW- negated
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-- Trd: Read data valid to IORDY asserted
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-- Ta:  IORDY setup time
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-- Tb:  IORDY pulse width
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--
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-- Transfer sequence
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----------------------------------
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-- 1)   set address (DA, CS0-, CS1-)
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-- 2)   wait for T1
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-- 3)   assert DIOR-/DIOW-
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--         when write action present Data (timing spec. T3 always honored), enable output enable-signal
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-- 4)   wait for T2
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-- 5)   check IORDY
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--         when not IORDY goto 5
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--        when IORDY negate DIOW-/DIOR-, latch data (if read action)
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--    when write, hold data for T4, disable output-enable signal
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-- 6)   wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest
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-- 7)   start new cycle
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity atahost_pio_tctrl is
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        generic(
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                TWIDTH : natural := 8;                   -- counter width
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                -- PIO mode 0 settings (@100MHz clock)
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                PIO_mode0_T1 : natural := 6;             -- 70ns
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                PIO_mode0_T2 : natural := 28;            -- 290ns
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                PIO_mode0_T4 : natural := 2;             -- 30ns
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                PIO_mode0_Teoc : natural := 23           -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
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        );
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        port(
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                clk    : in std_logic;                   -- master clock
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                nReset : in std_logic;                   -- asynchronous active low reset
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                rst    : in std_logic;                   -- synchronous active high reset
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                -- timing/control register settings
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                IORDY_en : in std_logic;                 -- use IORDY (or not)
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                T1   : in unsigned(TWIDTH -1 downto 0);  -- T1 time (in clk-ticks)
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                T2   : in unsigned(TWIDTH -1 downto 0);  -- T2 time (in clk-ticks)
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                T4   : in unsigned(TWIDTH -1 downto 0);  -- T4 time (in clk-ticks)
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                Teoc : in unsigned(TWIDTH -1 downto 0);  -- end of cycle time
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                -- control signals
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                go : in std_logic;                       -- PIO controller selected (strobe signal)
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                we : in std_logic;                       -- write enable signal. '0'=read from device, '1'=write to device
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                -- return signals
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                oe    : buffer std_logic;                -- output enable signal
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                done  : out std_logic;                   -- finished cycle
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                dstrb : out std_logic;                   -- data strobe, latch data (during read)
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                -- ATA signals
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                DIOR,                                    -- IOread signal, active high
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                DIOW  : buffer std_logic;                -- IOwrite signal, active high
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                IORDY : in std_logic                     -- IORDY signal
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        );
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end entity atahost_pio_tctrl;
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architecture structural of atahost_pio_tctrl is
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        component ro_cnt is
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        generic(
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                SIZE : natural := 8;
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                UD   : std_logic := '0'; -- default count down
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                ID   : natural := 0      -- initial data after reset
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        );
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        port(
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                clk    : in  std_logic;                  -- master clock
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                nReset : in  std_logic := '1';           -- asynchronous active low reset
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                rst    : in  std_logic := '0';           -- synchronous active high reset
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                cnt_en : in  std_logic := '1';           -- count enable
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                go     : in  std_logic;                  -- load counter and start sequence
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                done   : out std_logic;                  -- done counting
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                d      : in  unsigned(SIZE -1 downto 0); -- load counter value
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                q      : out unsigned(SIZE -1 downto 0)  -- current counter value
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        );
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        end component ro_cnt;
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        signal T1done, T2done, T4done, Teoc_done, IORDY_done : std_logic;
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        signal busy, hold_go, igo, hT2done : std_logic;
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begin
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        -- generate internal go strobe
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        -- strecht go until ready for new cycle
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        process(clk, nReset)
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        begin
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                if (nReset = '0') then
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                        busy <= '0';
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                        hold_go <= '0';
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                elsif (clk'event and clk = '1') then
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                        if (rst = '1') then
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                                busy <= '0';
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                                hold_go <= '0';
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                        else
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                                busy <= (igo or busy) and not Teoc_done;
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                                hold_go <= (go or (hold_go and busy)) and not igo;
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                        end if;
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                end if;
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        end process;
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        igo <= (go or hold_go) and not busy;
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        -- 1)   hookup T1 counter
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        t1_cnt : ro_cnt
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                generic map (
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                        SIZE => TWIDTH,
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                        UD   => '0',
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                        ID   => PIO_mode0_T1
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                )
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                port map (
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                        clk => clk,
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                        nReset => nReset,
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                        rst => rst,
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                        go => igo,
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                        D => T1,
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                        done => T1done
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                );
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        -- 2)   set (and reset) DIOR-/DIOW-, set output-enable when writing to device
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        T2proc: process(clk, nReset)
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        begin
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                if (nReset = '0') then
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                        DIOR <= '0';
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                        DIOW <= '0';
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                        oe   <= '0';
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                elsif (clk'event and clk = '1') then
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                        if (rst = '1') then
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                                DIOR <= '0';
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                                DIOW <= '0';
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                                oe   <= '0';
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                        else
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                                DIOR <= (not we and T1done) or (DIOR and not IORDY_done);
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                                DIOW <= (    we and T1done) or (DIOW and not IORDY_done);
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                                oe   <= ( (we and igo) or oe) and not T4done; -- negate oe when t4-done
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                        end if;
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                end if;
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        end process T2proc;
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        -- 3)   hookup T2 counter
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        t2_cnt : ro_cnt
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                generic map (
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                        SIZE => TWIDTH,
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                        UD   => '0',
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                        ID   => PIO_mode0_T2
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                )
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                port map (
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                        clk => clk,
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                        nReset => nReset,
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                        rst => rst,
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                        go => T1done,
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                        D => T2,
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                        done => T2done
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                );
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        -- 4)   check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-)
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        -- hold T2done
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        gen_hT2done: process(clk, nReset)
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        begin
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                if (nReset = '0') then
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                        hT2done <= '0';
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                elsif (clk'event and clk = '1') then
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                        if (rst = '1') then
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                                hT2done <= '0';
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                        else
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                                hT2done <= (T2done or hT2done) and not IORDY_done;
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                        end if;
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                end if;
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        end process gen_hT2done;
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        IORDY_done <= (T2done or hT2done) and (IORDY or not IORDY_en);
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        -- generate datastrobe, capture data at rising DIOR- edge
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        gen_dstrb: process(clk)
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        begin
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                if (clk'event and clk = '1') then
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                        dstrb <= IORDY_done;
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                end if;
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        end process gen_dstrb;
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        -- hookup data hold counter
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        dhold_cnt : ro_cnt
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                generic map (
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                        SIZE => TWIDTH,
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                        UD   => '0',
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                        ID   => PIO_mode0_T4
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                )
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                port map (
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                        clk => clk,
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                        nReset => nReset,
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                        rst => rst,
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                        go => IORDY_done,
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                        D => T4,
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                        done => T4done
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                );
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        done <= T4done; -- placing done here provides the fastest return possible, 
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                      -- while still guaranteeing data and address hold-times
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        -- 5)   hookup end_of_cycle counter
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        eoc_cnt : ro_cnt
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                generic map (
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                        SIZE => TWIDTH,
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                        UD   => '0',
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                        ID   => PIO_mode0_Teoc
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                )
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                port map (
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                        clk => clk,
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                        nReset => nReset,
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                        rst => rst,
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                        go => IORDY_done,
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                        D => Teoc,
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                        done => Teoc_done
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                );
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end architecture structural;

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