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rherveille |
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---- ----
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---- OpenCores IDE Controller ----
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---- ----
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---- Author: Richard Herveille ----
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---- richard@asics.ws ----
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---- www.asics.ws ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2001, 2002 Richard Herveille ----
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---- richard@asics.ws ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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-- CVS Log
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--
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-- $Id: atahost_reg_buf.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $
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--
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-- $Date: 2002-02-18 14:32:12 $
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-- $Revision: 1.1 $
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-- $Author: rherveille $
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-- $Locker: $
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-- $State: Exp $
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--
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-- Change History:
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-- $Log: not supported by cvs2svn $
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity atahost_reg_buf is
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generic (
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WIDTH : natural := 8
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);
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port(
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clk : in std_logic;
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nReset : in std_logic;
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rst : in std_logic;
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D : in std_logic_vector(WIDTH -1 downto 0);
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Q : out std_logic_vector(WIDTH -1 downto 0);
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rd : in std_logic;
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wr : in std_logic;
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valid : buffer std_logic
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);
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end entity atahost_reg_buf;
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architecture structural of atahost_reg_buf is
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begin
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process(clk, nReset)
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begin
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if (nReset = '0') then
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Q <= (others => '0');
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valid <= '0';
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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Q <= (others => '0');
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valid <= '0';
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else
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if (wr = '1') then
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Q <= D;
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end if;
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valid <= wr or (valid and not rd);
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end if;
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end if;
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end process;
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end architecture structural;
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