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rherveille |
---------------------------------------------------------------------
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---- ----
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---- OpenCores IDE Controller ----
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---- Wishbone Slave (common for all OCIDEC cores) ----
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---- ----
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---- Author: Richard Herveille ----
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---- richard@asics.ws ----
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---- www.asics.ws ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2002 Richard Herveille ----
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---- richard@asics.ws ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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--
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-- CVS Log
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--
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-- $Id: atahost_wb_slave.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $
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--
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-- $Date: 2002-02-18 14:32:12 $
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-- $Revision: 1.1 $
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-- $Author: rherveille $
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-- $Locker: $
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-- $State: Exp $
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--
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-- Change History:
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-- $Log: not supported by cvs2svn $
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity atahost_wb_slave is
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generic(
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DeviceID : unsigned(3 downto 0) := x"0";
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RevisionNo : unsigned(3 downto 0) := x"0";
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-- PIO mode 0 settings (@100MHz clock)
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PIO_mode0_T1 : natural := 6; -- 70ns
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PIO_mode0_T2 : natural := 28; -- 290ns
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PIO_mode0_T4 : natural := 2; -- 30ns
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PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
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-- Multiword DMA mode 0 settings (@100MHz clock)
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DMA_mode0_Tm : natural := 4; -- 50ns
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DMA_mode0_Td : natural := 21; -- 215ns
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DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
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);
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port(
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-- WISHBONE SYSCON signals
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clk_i : in std_logic; -- master clock in
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arst_i : in std_logic := '1'; -- asynchronous active low reset
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rst_i : in std_logic := '0'; -- synchronous active high reset
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-- WISHBONE SLAVE signals
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cyc_i : in std_logic; -- valid bus cycle input
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stb_i : in std_logic; -- strobe/core select input
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ack_o : out std_logic; -- strobe acknowledge output
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rty_o : out std_logic; -- retry output
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err_o : out std_logic; -- error output
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adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected
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-- A5 = '1' CS1- asserted, '0' CS0- asserted
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-- A4..A2 ATA address lines
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-- A6 = '0' ATA controller selected
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dat_i : in std_logic_vector(31 downto 0); -- Databus in
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dat_o : out std_logic_vector(31 downto 0); -- Databus out
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sel_i : in std_logic_vector(3 downto 0); -- Byte select signals
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we_i : in std_logic; -- Write enable input
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inta_o : out std_logic; -- interrupt request signal IDE0
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-- PIO control input
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PIOsel : buffer std_logic;
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PIOtip, -- PIO transfer in progress
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PIOack : in std_logic; -- PIO acknowledge signal
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PIOq : in std_logic_vector(15 downto 0); -- PIO data input
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PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full
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irq : in std_logic; -- interrupt signal input
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-- DMA control inputs
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DMAsel : out std_logic;
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DMAtip, -- DMA transfer in progress
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DMAack, -- DMA transfer acknowledge
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DMARxEmpty, -- DMA receive buffer empty
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DMATxFull, -- DMA transmit buffer full
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DMA_dmarq : in std_logic; -- wishbone DMA request
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DMAq : in std_logic_vector(31 downto 0);
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-- outputs
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-- control register outputs
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IDEctrl_rst,
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IDEctrl_IDEen,
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IDEctrl_FATR1,
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IDEctrl_FATR0,
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IDEctrl_ppen,
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DMActrl_DMAen,
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DMActrl_dir,
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DMActrl_BeLeC0,
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DMActrl_BeLeC1 : out std_logic;
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-- CMD port timing registers
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PIO_cmdport_T1,
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PIO_cmdport_T2,
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PIO_cmdport_T4,
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PIO_cmdport_Teoc : buffer unsigned(7 downto 0);
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PIO_cmdport_IORDYen : out std_logic;
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-- data-port0 timing registers
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PIO_dport0_T1,
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PIO_dport0_T2,
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PIO_dport0_T4,
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PIO_dport0_Teoc : buffer unsigned(7 downto 0);
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PIO_dport0_IORDYen : out std_logic;
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-- data-port1 timing registers
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PIO_dport1_T1,
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PIO_dport1_T2,
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PIO_dport1_T4,
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PIO_dport1_Teoc : buffer unsigned(7 downto 0);
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PIO_dport1_IORDYen : out std_logic;
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-- DMA device0 timing registers
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DMA_dev0_Tm,
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DMA_dev0_Td,
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DMA_dev0_Teoc : buffer unsigned(7 downto 0);
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-- DMA device1 timing registers
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DMA_dev1_Tm,
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DMA_dev1_Td,
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DMA_dev1_Teoc : buffer unsigned(7 downto 0)
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);
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end entity atahost_wb_slave;
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architecture structural of atahost_wb_slave is
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--
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-- constants
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--
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-- addresses
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alias ATA_DEV_ADR : std_logic is adr_i(6);
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alias ATA_ADR : unsigned(3 downto 0) is adr_i(5 downto 2);
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constant ATA_CTRL_REG : unsigned(3 downto 0) := "0000";
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constant ATA_STAT_REG : unsigned(3 downto 0) := "0001";
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constant ATA_PIO_CMD : unsigned(3 downto 0) := "0010";
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constant ATA_PIO_DP0 : unsigned(3 downto 0) := "0011";
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constant ATA_PIO_DP1 : unsigned(3 downto 0) := "0100";
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constant ATA_DMA_DEV0 : unsigned(3 downto 0) := "0101";
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constant ATA_DMA_DEV1 : unsigned(3 downto 0) := "0110";
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-- reserved --
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constant ATA_DMA_PORT : unsigned(3 downto 0) := "1111";
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--
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-- function declarations
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--
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-- overload '=' to compare two unsigned numbers
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function "=" (a, b : unsigned) return std_logic is
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alias la: unsigned(1 to a'length) is a;
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alias lb: unsigned(1 to b'length) is b;
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variable result : std_logic;
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begin
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-- check vector length
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assert a'length = b'length
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report "std_logic_vector comparison: operands of unequal lengths"
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severity FAILURE;
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result := '1';
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for n in 1 to a'length loop
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result := result and not (la(n) xor lb(n));
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end loop;
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return result;
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end;
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-- primary address decoder
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signal CONsel : std_logic; -- controller select, IDE devices select
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signal berr, brty : std_logic; -- bus error, bus retry
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-- registers
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signal CtrlReg, StatReg : std_logic_vector(31 downto 0); -- control and status registers
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begin
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--
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-- generate bus cycle / address decoder
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--
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gen_bc_dec: block
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signal w_acc, dw_acc : std_logic; -- word access, double word access
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signal store_pp_full : std_logic;
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begin
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-- word / double word
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w_acc <= sel_i(1) and sel_i(0);
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dw_acc <= sel_i(3) and sel_i(2) and sel_i(1) and sel_i(0);
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-- bus error
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berr <= not w_acc when (ATA_DEV_ADR = '1') else not dw_acc;
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-- PIO accesses at least 16bit wide, no PIO access during DMAtip or pingpong full
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PIOsel <= cyc_i and stb_i and ATA_DEV_ADR and w_acc and not (DMAtip or store_pp_full);
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-- CON accesses only 32bit wide
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CONsel <= cyc_i and stb_i and not ATA_DEV_ADR and dw_acc;
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DMAsel <= CONsel and (ATA_ADR = ATA_DMA_PORT);
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-- bus retry (OCIDEC-3 and above)
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-- store PIOpp_full, we don't want a PPfull based retry initiated by the current bus-cycle
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process(clk_i)
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begin
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if (clk_i'event and clk_i = '1') then
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if (PIOsel = '0') then
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store_pp_full <= PIOpp_full;
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end if;
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end if;
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end process;
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brty <= (ATA_DEV_ADR and w_acc) and (DMAtip or store_pp_full);
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end block gen_bc_dec;
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--
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-- generate registers
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--
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register_block : block
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signal sel_PIO_cmdport, sel_PIO_dport0, sel_PIO_dport1 : std_logic; -- PIO timing registers
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signal sel_DMA_dev0, sel_DMA_dev1 : std_logic; -- DMA timing registers
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signal sel_ctrl, sel_stat : std_logic; -- control / status register
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begin
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-- generate register select signals
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sel_ctrl <= CONsel and we_i and (ATA_ADR = ATA_CTRL_REG);
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sel_stat <= CONsel and we_i and (ATA_ADR = ATA_STAT_REG);
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sel_PIO_cmdport <= CONsel and we_i and (ATA_ADR = ATA_PIO_CMD);
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sel_PIO_dport0 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP0);
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sel_PIO_dport1 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP1);
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sel_DMA_dev0 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV0);
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sel_DMA_dev1 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV1);
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-- reserved 0x1C-0x38 --
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-- reserved 0x3C : DMA port --
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-- generate control register
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gen_ctrl_reg: process(clk_i, arst_i)
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begin
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if (arst_i = '0') then
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CtrlReg(31 downto 1) <= (others => '0');
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CtrlReg(0) <= '1'; -- set reset bit
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elsif (clk_i'event and clk_i = '1') then
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if (rst_i = '1') then
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CtrlReg(31 downto 1) <= (others => '0');
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CtrlReg(0) <= '1'; -- set reset bit
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elsif (sel_ctrl = '1') then
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CtrlReg <= dat_i;
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end if;
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end if;
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end process gen_ctrl_reg;
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-- assign bits
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DMActrl_DMAen <= CtrlReg(15);
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DMActrl_dir <= CtrlReg(13);
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DMActrl_BeLeC1 <= CtrlReg(9);
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DMActrl_BeLeC0 <= CtrlReg(8);
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IDEctrl_IDEen <= CtrlReg(7);
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IDEctrl_FATR1 <= CtrlReg(6);
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IDEctrl_FATR0 <= CtrlReg(5);
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IDEctrl_ppen <= CtrlReg(4);
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PIO_dport1_IORDYen <= CtrlReg(3);
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PIO_dport0_IORDYen <= CtrlReg(2);
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PIO_cmdport_IORDYen <= CtrlReg(1);
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IDEctrl_rst <= CtrlReg(0);
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-- generate status register clearable bits
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gen_stat_reg: block
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signal dirq, int : std_logic;
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begin
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gen_irq: process(clk_i, arst_i)
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| 292 |
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begin
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| 293 |
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if (arst_i = '0') then
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int <= '0';
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dirq <= '0';
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elsif (clk_i'event and clk_i = '1') then
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| 297 |
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if (rst_i = '1') then
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int <= '0';
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dirq <= '0';
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else
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int <= (int or (irq and not dirq)) and not (sel_stat and not dat_i(0));
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dirq <= irq;
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end if;
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end if;
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end process gen_irq;
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| 307 |
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gen_stat: process(DMAtip, DMARxEmpty, DMATxFull, DMA_dmarq, PIOtip, int, PIOpp_full)
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| 308 |
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begin
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| 309 |
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StatReg(31 downto 0) <= (others => '0'); -- clear all bits (read unused bits as '0')
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| 310 |
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| 311 |
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StatReg(31 downto 28) <= std_logic_vector(DeviceId); -- set Device ID
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| 312 |
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StatReg(27 downto 24) <= std_logic_vector(RevisionNo); -- set revision number
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| 313 |
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StatReg(15) <= DMAtip;
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| 314 |
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StatReg(10) <= DMARxEmpty;
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| 315 |
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StatReg(9) <= DMATxFull;
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| 316 |
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StatReg(8) <= DMA_dmarq;
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| 317 |
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StatReg(7) <= PIOtip;
|
| 318 |
|
|
StatReg(6) <= PIOpp_full;
|
| 319 |
|
|
StatReg(0) <= int;
|
| 320 |
|
|
end process;
|
| 321 |
|
|
end block gen_stat_reg;
|
| 322 |
|
|
|
| 323 |
|
|
-- generate PIO compatible / command-port timing register
|
| 324 |
|
|
gen_PIO_cmdport_reg: process(clk_i, arst_i)
|
| 325 |
|
|
begin
|
| 326 |
|
|
if (arst_i = '0') then
|
| 327 |
|
|
PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8);
|
| 328 |
|
|
PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8);
|
| 329 |
|
|
PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8);
|
| 330 |
|
|
PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);
|
| 331 |
|
|
elsif (clk_i'event and clk_i = '1') then
|
| 332 |
|
|
if (rst_i = '1') then
|
| 333 |
|
|
PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8);
|
| 334 |
|
|
PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8);
|
| 335 |
|
|
PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8);
|
| 336 |
|
|
PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);
|
| 337 |
|
|
elsif (sel_PIO_cmdport = '1') then
|
| 338 |
|
|
PIO_cmdport_T1 <= unsigned(dat_i( 7 downto 0));
|
| 339 |
|
|
PIO_cmdport_T2 <= unsigned(dat_i(15 downto 8));
|
| 340 |
|
|
PIO_cmdport_T4 <= unsigned(dat_i(23 downto 16));
|
| 341 |
|
|
PIO_cmdport_Teoc <= unsigned(dat_i(31 downto 24));
|
| 342 |
|
|
end if;
|
| 343 |
|
|
end if;
|
| 344 |
|
|
end process gen_PIO_cmdport_reg;
|
| 345 |
|
|
|
| 346 |
|
|
-- generate PIO device0 timing register
|
| 347 |
|
|
gen_PIO_dport0_reg: process(clk_i, arst_i)
|
| 348 |
|
|
begin
|
| 349 |
|
|
if (arst_i = '0') then
|
| 350 |
|
|
PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8);
|
| 351 |
|
|
PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8);
|
| 352 |
|
|
PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8);
|
| 353 |
|
|
PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);
|
| 354 |
|
|
elsif (clk_i'event and clk_i = '1') then
|
| 355 |
|
|
if (rst_i = '1') then
|
| 356 |
|
|
PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8);
|
| 357 |
|
|
PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8);
|
| 358 |
|
|
PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8);
|
| 359 |
|
|
PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);
|
| 360 |
|
|
elsif (sel_PIO_dport0 = '1') then
|
| 361 |
|
|
PIO_dport0_T1 <= unsigned(dat_i( 7 downto 0));
|
| 362 |
|
|
PIO_dport0_T2 <= unsigned(dat_i(15 downto 8));
|
| 363 |
|
|
PIO_dport0_T4 <= unsigned(dat_i(23 downto 16));
|
| 364 |
|
|
PIO_dport0_Teoc <= unsigned(dat_i(31 downto 24));
|
| 365 |
|
|
end if;
|
| 366 |
|
|
end if;
|
| 367 |
|
|
end process gen_PIO_dport0_reg;
|
| 368 |
|
|
|
| 369 |
|
|
-- generate PIO device1 timing register
|
| 370 |
|
|
gen_PIO_dport1_reg: process(clk_i, arst_i)
|
| 371 |
|
|
begin
|
| 372 |
|
|
if (arst_i = '0') then
|
| 373 |
|
|
PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8);
|
| 374 |
|
|
PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8);
|
| 375 |
|
|
PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8);
|
| 376 |
|
|
PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);
|
| 377 |
|
|
elsif (clk_i'event and clk_i = '1') then
|
| 378 |
|
|
if (rst_i = '1') then
|
| 379 |
|
|
PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8);
|
| 380 |
|
|
PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8);
|
| 381 |
|
|
PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8);
|
| 382 |
|
|
PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);
|
| 383 |
|
|
elsif (sel_PIO_dport1 = '1') then
|
| 384 |
|
|
PIO_dport1_T1 <= unsigned(dat_i( 7 downto 0));
|
| 385 |
|
|
PIO_dport1_T2 <= unsigned(dat_i(15 downto 8));
|
| 386 |
|
|
PIO_dport1_T4 <= unsigned(dat_i(23 downto 16));
|
| 387 |
|
|
PIO_dport1_Teoc <= unsigned(dat_i(31 downto 24));
|
| 388 |
|
|
end if;
|
| 389 |
|
|
end if;
|
| 390 |
|
|
end process gen_PIO_dport1_reg;
|
| 391 |
|
|
|
| 392 |
|
|
-- generate DMA device0 timing register
|
| 393 |
|
|
gen_DMA_dev0_reg: process(clk_i, arst_i)
|
| 394 |
|
|
begin
|
| 395 |
|
|
if (arst_i = '0') then
|
| 396 |
|
|
DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8);
|
| 397 |
|
|
DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8);
|
| 398 |
|
|
DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8);
|
| 399 |
|
|
elsif (clk_i'event and clk_i = '1') then
|
| 400 |
|
|
if (rst_i = '1') then
|
| 401 |
|
|
DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8);
|
| 402 |
|
|
DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8);
|
| 403 |
|
|
DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8);
|
| 404 |
|
|
elsif (sel_DMA_dev0 = '1') then
|
| 405 |
|
|
DMA_dev0_Tm <= unsigned(dat_i( 7 downto 0));
|
| 406 |
|
|
DMA_dev0_Td <= unsigned(dat_i(15 downto 8));
|
| 407 |
|
|
DMA_dev0_Teoc <= unsigned(dat_i(31 downto 24));
|
| 408 |
|
|
end if;
|
| 409 |
|
|
end if;
|
| 410 |
|
|
end process gen_DMA_dev0_reg;
|
| 411 |
|
|
|
| 412 |
|
|
-- generate DMA device1 timing register
|
| 413 |
|
|
gen_DMA_dev1_reg: process(clk_i, arst_i)
|
| 414 |
|
|
begin
|
| 415 |
|
|
if (arst_i = '0') then
|
| 416 |
|
|
DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8);
|
| 417 |
|
|
DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8);
|
| 418 |
|
|
DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8);
|
| 419 |
|
|
elsif (clk_i'event and clk_i = '1') then
|
| 420 |
|
|
if (rst_i = '1') then
|
| 421 |
|
|
DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8);
|
| 422 |
|
|
DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8);
|
| 423 |
|
|
DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8);
|
| 424 |
|
|
elsif (sel_DMA_dev1 = '1') then
|
| 425 |
|
|
DMA_dev1_Tm <= unsigned(dat_i( 7 downto 0));
|
| 426 |
|
|
DMA_dev1_Td <= unsigned(dat_i(15 downto 8));
|
| 427 |
|
|
DMA_dev1_Teoc <= unsigned(dat_i(31 downto 24));
|
| 428 |
|
|
end if;
|
| 429 |
|
|
end if;
|
| 430 |
|
|
end process gen_DMA_dev1_reg;
|
| 431 |
|
|
|
| 432 |
|
|
end block register_block;
|
| 433 |
|
|
|
| 434 |
|
|
--
|
| 435 |
|
|
-- generate WISHBONE interconnect signals
|
| 436 |
|
|
--
|
| 437 |
|
|
gen_WB_sigs: block
|
| 438 |
|
|
signal Q : std_logic_vector(31 downto 0);
|
| 439 |
|
|
begin
|
| 440 |
|
|
-- generate acknowledge signal
|
| 441 |
|
|
ack_o <= PIOack or CONsel; -- or DMAack; -- since DMAack is derived from CONsel this is OK
|
| 442 |
|
|
|
| 443 |
|
|
-- generate error signal
|
| 444 |
|
|
err_o <= cyc_i and stb_i and berr;
|
| 445 |
|
|
|
| 446 |
|
|
-- generate retry signal
|
| 447 |
|
|
rty_o <= cyc_i and stb_i and brty;
|
| 448 |
|
|
|
| 449 |
|
|
-- assign interrupt signal
|
| 450 |
|
|
inta_o <= StatReg(0);
|
| 451 |
|
|
|
| 452 |
|
|
-- generate output multiplexor
|
| 453 |
|
|
with ATA_ADR select
|
| 454 |
|
|
Q <= CtrlReg when ATA_CTRL_REG, -- control register
|
| 455 |
|
|
StatReg when ATA_STAT_REG, -- status register
|
| 456 |
|
|
std_logic_vector(PIO_cmdport_Teoc & PIO_cmdport_T4 & PIO_cmdport_T2 & PIO_cmdport_T1) when ATA_PIO_CMD, -- PIO compatible / cmd-port timing register
|
| 457 |
|
|
std_logic_vector(PIO_dport0_Teoc & PIO_dport0_T4 & PIO_dport0_T2 & PIO_dport0_T1) when ATA_PIO_DP0, -- PIO fast timing register device0
|
| 458 |
|
|
std_logic_vector(PIO_dport1_Teoc & PIO_dport1_T4 & PIO_dport1_T2 & PIO_dport1_T1) when ATA_PIO_DP1, -- PIO fast timing register device1
|
| 459 |
|
|
std_logic_vector(DMA_dev0_Teoc & x"00" & DMA_dev0_Td & DMA_dev0_Tm) when ATA_DMA_DEV0, -- DMA timing register device0
|
| 460 |
|
|
std_logic_vector(DMA_dev1_Teoc & x"00" & DMA_dev1_Td & DMA_dev1_Tm) when ATA_DMA_DEV1, -- DMA timing register device1
|
| 461 |
|
|
DMAq when ATA_DMA_PORT, -- DMA port, DMA receive register
|
| 462 |
|
|
(others => '0') when others;
|
| 463 |
|
|
|
| 464 |
|
|
dat_o <= (x"0000" & PIOq) when (ATA_DEV_ADR = '1') else Q;
|
| 465 |
|
|
end block gen_WB_sigs;
|
| 466 |
|
|
|
| 467 |
|
|
end architecture structural;
|
