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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec3/] [revision_history.txt] - Blame information for rev 33

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-----------------------------
Revision: 1.0
Date: march 22nd, 2001
Author: Richard Herveille
- initial release
-----------------------------
 
-----------------------------
Revision: 1.0a
Date: april 12th, 2001
Author: Richard Herveille
- removed records.vhd
- removed all references to records.vhd, make core compatible with VHDL to Verilog translation tools
- fixed a minor bug where core didn't respond to IDEen bit.
-----------------------------
 
-----------------------------
Revision: 1.1
Date: june 18th, 2001
Author: Richard Herveille
- Changed wishbone address-input from ADR_I(4 downto 0) to ADR_I(6 downto 2)
-----------------------------
 
-----------------------------
Revision: 1.1a
Date: june 19th, 2001
Author: Richard Herveille
- Simplified DAT_O output multiplexor
-----------------------------
 
-----------------------------
Revision: 1.3
Date: July 11th, 2001
Author: Richard Herveille
- renamed 'ata.vhd' to 'atahost.vhd'
- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).
-----------------------------
 
-----------------------------
Revision: 1.4
Date: Februar 17th, 2002
Author: Richard Herveille
- renamed all files to 'atahost_***.vhd'
- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
- changed resD input to generic RESD in ud_cnt.vhd
- changed ID input to generic ID in ro_cnt.vhd
- changed core to reflect changes in ro_cnt.vhd
- removed references to 'count' library
- changed IO names
- added disclaimer
- added CVS log
- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
-----------------------------

Line No.	Rev	Author	Line
1	14	rherveille	`-----------------------------`
2			`Revision: 1.0`
3			`Date: march 22nd, 2001`
4			`Author: Richard Herveille`
5			`- initial release`
6			`-----------------------------`
7
8			`-----------------------------`
9			`Revision: 1.0a`
10			`Date: april 12th, 2001`
11			`Author: Richard Herveille`
12			`- removed records.vhd`
13			`- removed all references to records.vhd, make core compatible with VHDL to Verilog translation tools`
14			`- fixed a minor bug where core didn't respond to IDEen bit.`
15			`-----------------------------`
16
17			`-----------------------------`
18			`Revision: 1.1`
19			`Date: june 18th, 2001`
20			`Author: Richard Herveille`
21			`- Changed wishbone address-input from ADR_I(4 downto 0) to ADR_I(6 downto 2)`
22			`-----------------------------`
23
24			`-----------------------------`
25			`Revision: 1.1a`
26			`Date: june 19th, 2001`
27			`Author: Richard Herveille`
28			`- Simplified DAT_O output multiplexor`
29			`-----------------------------`
30
31			`-----------------------------`
32			`Revision: 1.3`
33			`Date: July 11th, 2001`
34			`Author: Richard Herveille`
35			`- renamed 'ata.vhd' to 'atahost.vhd'`
36			`- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).`
37			`-----------------------------`
38	27	rherveille
39			`-----------------------------`
40			`Revision: 1.4`
41			`Date: Februar 17th, 2002`
42			`Author: Richard Herveille`
43			`- renamed all files to 'atahost_***.vhd'`
44			`- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'`
45			`- changed resD input to generic RESD in ud_cnt.vhd`
46			`- changed ID input to generic ID in ro_cnt.vhd`
47			`- changed core to reflect changes in ro_cnt.vhd`
48			`- removed references to 'count' library`
49			`- changed IO names`
50			`- added disclaimer`
51			`- added CVS log`
52			`- moved registers and wishbone signals into 'atahost_wb_slave.vhd'`
53			`-----------------------------`

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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec3/] [revision_history.txt] - Blame information for rev 33