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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec3/] [revision_history.txt] - Blame information for rev 14
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Author |
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14 |
rherveille |
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Revision: 1.0
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Date: march 22nd, 2001
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Author: Richard Herveille
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- initial release
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| 8 |
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| 9 |
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Revision: 1.0a
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| 10 |
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Date: april 12th, 2001
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| 11 |
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Author: Richard Herveille
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| 12 |
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- removed records.vhd
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| 13 |
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- removed all references to records.vhd, make core compatible with VHDL to Verilog translation tools
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| 14 |
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- fixed a minor bug where core didn't respond to IDEen bit.
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| 15 |
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Revision: 1.1
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| 19 |
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Date: june 18th, 2001
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| 20 |
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Author: Richard Herveille
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| 21 |
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- Changed wishbone address-input from ADR_I(4 downto 0) to ADR_I(6 downto 2)
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Revision: 1.1a
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| 26 |
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Date: june 19th, 2001
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| 27 |
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Author: Richard Herveille
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| 28 |
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- Simplified DAT_O output multiplexor
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| 29 |
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| 32 |
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Revision: 1.3
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| 33 |
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Date: July 11th, 2001
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| 34 |
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Author: Richard Herveille
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| 35 |
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- renamed 'ata.vhd' to 'atahost.vhd'
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| 36 |
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- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).
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| 37 |
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