OpenCores
URL https://opencores.org/ocsvn/ata/ata/trunk

Subversion Repositories ata

[/] [ata/] [trunk/] [syn/] [bin/] [comp.dc] - Blame information for rev 16

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 16 rudi
###############################################################################
2
#
3
# Actual Synthesis Script
4
#
5
# This script does the actual synthesis
6
#
7
# Author: Rudolf Usselmann
8
#         rudi@asics.ws
9
#
10
# Revision:
11
# 3/7/01 RU Initial Sript
12
#
13
#
14
###############################################################################
15
 
16
# ==============================================
17
# Setup Design Parameters
18
source ../bin/design_spec.dc
19
 
20
# ==============================================
21
# Setup Libraries
22
source ../bin/lib_spec.dc
23
 
24
# ==============================================
25
# Setup IO Files
26
 
27
append log_file                 ../log/$active_design "_cmp.log"
28
append pre_comp_db_file         ../out/$design_name "_pre.db"
29
append post_comp_db_file        ../out/$design_name ".db"
30
append post_syn_verilog_file    ../out/$design_name "_ps.v"
31
set junk_file /dev/null
32
 
33
sh rm -f $log_file
34
 
35
# ==============================================
36
# Setup Misc Variables
37
 
38
set hdlin_enable_vpp true       ;# Important - this enables 'ifdefs
39
 
40
# ==============================================
41
# Read Design
42
 
43
echo "+++++++++ Reading Design ..."                             >> $log_file
44
read_file $pre_comp_db_file                                     >> $log_file
45
 
46
# ==============================================
47
# Operating conditions
48
 
49
echo "+++++++++ Setting up Operation Conditions ..."            >> $log_file
50
current_design $design_name
51
set_operating_conditions WORST                                  >> $log_file
52
 
53
# Turn off automatic wire load selection, as this
54
# always (WHY ???) defaults to "zero_load"
55
#set auto_wire_load_selection false
56
#set_wire_load_mode enclosed                                     >> $log_file
57
#set_wire_load_mode top                                          >> $log_file
58
#set_wire_load_model -name suggested_40K                         >> $log_file
59
 
60
# ==============================================
61
# Setup Clocks and Resets
62
 
63
echo "+++++++++ Setting up Clocks ..."                           >> $log_file
64
 
65
set_drive 0 [find port {*clk*}]
66
 
67
# !!! WISHBONE Clock !!!
68
set clock_period 5
69
create_clock -period $clock_period wb_clk_i
70
set_clock_skew -uncertainty 0.1 wb_clk_i
71
set_clock_transition 0.5 wb_clk_i
72
set_dont_touch_network wb_clk_i
73
 
74
# !!! Reset !!!
75
set_drive 0 [find port {*rst*}]
76
set_dont_touch_network [find port {*rst*}]
77
 
78
# ==============================================
79
# Setup IOs
80
 
81
echo "+++++++++ Setting up IOs ..."                             >> $log_file
82
 
83
set_driving_cell -cell NAND2D2 -pin Z [all_inputs]              >> $junk_file
84
set_load 0.2 [all_outputs]
85
 
86
set_input_delay -max 1 -clock wb_clk_i [all_inputs]
87
set_output_delay -max 1 -clock wb_clk_i [all_outputs]
88
 
89
# ==============================================
90
# Setup Area Constrains
91
set_max_area 0.0
92
 
93
# ==============================================
94
# Force Ultra
95
set_ultra_optimization -f
96
 
97
# ==============================================
98
# Compile Design
99
 
100
echo "+++++++++ Starting Compile ..."                           >> $log_file
101
compile -map_effort medium -area_effort medium -ungroup_all    >> $log_file
102
#compile -map_effort low -area_effort low                       >> $log_file
103
#compile -map_effort high -area_effort high -ungroup_all        >> $log_file
104
#compile -map_effort high -area_effort high -auto_ungroup       >> $log_file
105
 
106
# ==============================================
107
# Write Out the optimized design
108
 
109
echo "+++++++++ Saving Optimized Design ..."                    >> $log_file
110
write_file -format verilog -output $post_syn_verilog_file
111
write_file -hierarchy -format db -output $post_comp_db_file
112
 
113
# ==============================================
114
# Create Some Basic Reports
115
 
116
echo "+++++++++ Reporting Final Results ..."                    >> $log_file
117
report_timing -nworst 10                                        >> $log_file
118
report_area                                                     >> $log_file
119
 
120
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.