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# Design Specification

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# Author: Rudolf Usselmann

#         rudi@asics.ws

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# Revision:

# 3/7/01 RU Initial Sript

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# Setup Design Parameters

set design_files {ud_cnt ro_cnt atahost_pio_tctrl atahost_controller atahost_top}

set design_name atahost_top

set active_design atahost_top

# Next Statement defines all clocks and resets in the design

set special_net {wb_rst_i rst_nreset_i wb_clk_i}

set hdl_src_dir ../../rtl/verilog/ocidec-1/