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jclaytons |
--------------------------------------------------------------------------
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-- Package of auto_baud components
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--
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-- Contains the following components:
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--
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-- auto_baud_with_tracking
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-- auto_baud_with_tracking_slv
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--
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-- the version with the suffix _slv attached to the name provides
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-- IO busses of the "std_logic_vector" type instead of "unsigned."
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-- In all other ways, these components are identical.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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package auto_baud_pack is
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component auto_baud_with_tracking
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generic (
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CLOCK_FACTOR : natural; -- Output is this factor times the baud rate
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FPGA_CLKRATE : integer; -- FPGA system clock rate
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MIN_BAUDRATE : integer; -- Minimum expected incoming Baud rate
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DELTA_THRESHOLD : integer -- Max. number of sys_clks difference allowed between
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-- "half_measurement" and "measurement"
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);
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port (
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sys_rst_n : in std_logic;
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sys_clk : in std_logic;
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-- rate and parity
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rx_parity_i : in unsigned(1 downto 0); -- 0=none, 1=even, 2=odd
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-- serial input
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rx_stream_i : in std_logic;
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-- Output
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baud_lock_o : out std_logic;
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baud_clk_o : out std_logic
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);
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end component;
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component auto_baud_with_tracking_slv
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generic (
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CLOCK_FACTOR : natural; -- Output is this factor times the baud rate
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FPGA_CLKRATE : integer; -- FPGA system clock rate
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MIN_BAUDRATE : integer; -- Minimum expected incoming Baud rate
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DELTA_THRESHOLD : integer -- Max. number of sys_clks difference allowed between
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-- "half_measurement" and "measurement"
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);
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port (
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sys_rst_n : in std_logic;
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sys_clk : in std_logic;
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-- rate and parity
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rx_parity_i : in std_logic_vector(1 downto 0); -- 0=none, 1=even, 2=odd
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-- serial input
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rx_stream_i : in std_logic;
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-- Output
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baud_lock_o : out std_logic;
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baud_clk_o : out std_logic
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);
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end component;
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end auto_baud_pack;
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package body auto_baud_pack is
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end auto_baud_pack;
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-------------------------------------------------------------------------------
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-- Auto Baud with tracking core
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-------------------------------------------------------------------------------
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--
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-- Author: John Clayton
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-- Date : Aug. 20, 2002 Began project
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-- Update: Sep. 5, 2002 copied this file from "autobaud.v"
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-- Added tracking functions, and debugged them.
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-- Update: Sep. 13, 2002 Added test data. Module complete, it works well.
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-- Update: Nov. 20, 2009 Began translation into VHDL
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--
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-- Description
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-------------------------------------------------------------------------------
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-- This is a state-machine driven core that measures transition intervals
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-- in a particular character arriving via rs232 transmission (i.e. PC serial
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-- port.) Measurements of time intervals between transitions in the received
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-- character are then used to generate a baud rate clock for use in serial
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-- communications back and forth with the device that originally transmitted
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-- the measured character. The clock which is generated is in reality a
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-- clock enable pulse, one single clock wide, occurring at a rate suitable
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-- for use in serial communications. (This means that it will be generated
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-- at 4x or 8x or 16x the actual measured baud rate of the received character.
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-- The multiplication factor is called "CLOCK_FACTOR" and is a settable
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-- parameter within this module. The parameter "CLOCK_FACTOR" need not
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-- be a power of two, but it should be a number between 2 and 16 inclusive.)
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--
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-- The particular character which is targeted for measurement and verification
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-- in this module is: carriage return (CR) = 0x0d = 13.
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-- This particular character was chosen because it is frequently used at the
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-- end of a command line, as entered at a keyboard by a human user interacting
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-- with a command interpreter. It is anticipated that the user would press
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-- the "enter" key once upon initializing communications with the electronic
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-- device, and the resulting carriage return character would be used for
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-- determining BAUD rate, thus allowing the device to respond at the correct
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-- rate, and to carry on further communications. The electronic device using
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-- this "auto_baud" module adjusts its baud rate to match the baud rate of
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-- the received data. This works for all baud rates, within certain limits,
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-- and for all system clock rates, within certain limits.
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--
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-- Received serially, and with no parity bit, the carriage return appears as
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-- the following waveform:
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-- ________ __ ____ _______________
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-- |__|d0|__|d2d3|________|stop
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-- start d1 d4d5d6d7
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--
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-- The waveform is shown with an identical "high" time and "low" time for
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-- each bit. However, actual measurements taken using a logic analyzer
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-- on characters received from a PC show that the times are not equal.
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-- The "high" times turned out shorter, and the "low" times longer...
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-- Therefore, this module attempts to average out this discrepancy by
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-- measuring one low time and one high time.
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--
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-- Since the transition measurements must unavoidably contain small amounts
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-- of error, the measurements are made during the beginning 2 bits of
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-- the received character, (that is, start bit and data bit zero).
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-- Then the measurement is immediately transformed into a baud rate clock,
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-- used to verify correct reception of the remaining 8 bits of the character.
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-- If the entire character is not received correctly using the generated
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-- baud rate, then the measurement is scrapped, and the unit goes into an
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-- idle scanning mode waiting for another character to test.
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--
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-- This effectively filters out characters that the unit is not interested in
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-- receiving (anything that is not a carriage return.) There is a slight
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-- possibility that a group of other characters could appear by random
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-- chance in a configuration that resembles a carriage return closely enough
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-- that the unit might accept the measurement and produce a baud clock too
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-- low. But the probability of this happening is remote enough that the
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-- unit is considered highly "robust" in normal use, especially when used
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-- for command entry by humans. It would take a very clever user indeed, to
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-- enter the correct series of characters with the correct intercharacter
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-- timing needed to possibly "fool" the unit!
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--
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-- (Also, the baud rate produced falls within certain limits imposed by
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-- the hardware of the unit, which prevents the auto_baud unit from mistaking
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-- a series of short glitches on the serial data line for a really
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-- fast CR character.)
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--
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-- This method of operation implies that each carriage return character
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-- received will produce a correctly generated baud rate clock. Therefore,
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-- each and every carriage return actually causes a new baud rate clock to
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-- be produced. However, updates occur smoothly, and there should be no
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-- apparent effect as an old BAUD clock is stopped and a new one started.
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-- The transition is done smoothly.
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--
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-- For users who desire a single measurement at the beginning of a session
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-- to produce a steady baud clock during the entire session, there is a
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-- slightly smaller module called "auto_baud.v" which performs a single
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-- measurement, but which requires a reset pulse in order to begin measuring
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-- for a new BAUD rate.
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--
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-- NOTES:
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-- - This module uses a counter to divide down the sys_clk signal to produce the
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-- baud_clk_o signal. Since the frequency of baud_clk_o is nominally
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-- CLOCK_FACTOR * rx_baud_rate, where "rx_baud_rate" is the baud rate
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-- of the received character, then the higher you make CLOCK_FACTOR, the
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-- higher the generated baud_clk_o signal frequency, and hence the lower the
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-- resolution of the divider. Therefore, using a lower value for the
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-- CLOCK_FACTOR will allow you to use a lower sys_clk with this module.
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-- - The lower the minimum baud rate setting, the larger the counters will be.
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-- This is so that the counters can accomodate the large count values needed
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-- to divide the system clock into the low Baud rate output.
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--
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-- - If the percentage error for your highest desired baud rate is greater
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-- than a few percent, you might want to use a higher Fsys_clk or else a
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-- lower CLOCK_FACTOR.
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--
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-- Note: Simply changing the template bits does not reconfigure the
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-- module to look for a different character (because a new measurement
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-- window might have to be defined for a different character...)
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-- The template bits are the exact bits used during verify, against
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-- which the incoming character is checked.
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-- The LSB of the character is not used for verification, since it is
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-- actually used in the measurement.
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.MATH_REAL.ALL;
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entity auto_baud_with_tracking is
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generic (
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CLOCK_FACTOR : natural := 16; -- Output is this factor times the baud rate
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FPGA_CLKRATE : integer := 25000000; -- FPGA system clock rate
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MIN_BAUDRATE : integer := 57600; -- Minimum expected incoming Baud rate
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DELTA_THRESHOLD : integer := 6 -- Max. number of sys_clks difference allowed between
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-- "half_measurement" and "measurement"
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);
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port (
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sys_rst_n : in std_logic;
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sys_clk : in std_logic;
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-- rate and parity
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rx_parity_i : in unsigned(1 downto 0); -- 0=none, 1=even, 2=odd
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-- serial input
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rx_stream_i : in std_logic;
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-- Output
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baud_lock_o : out std_logic;
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baud_clk_o : out std_logic
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);
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end auto_baud_with_tracking;
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architecture beh of auto_baud_with_tracking is
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-- Constants
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constant TEMPLATE_BITS : unsigned(7 downto 0) := "00001101"; -- Carriage return
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constant MAIN_COUNT_WIDTH : integer := integer(ceil(log2(real(FPGA_CLKRATE)/real(MIN_BAUDRATE)))); -- Bit Width of timer.
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-- Internal signal declarations
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-- State Machine
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type FSM_STATE_TYPE is (IDLE, MEASURE_START_BIT, MEASURE_DATA_BIT, VERIFY);
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signal fsm_state : FSM_STATE_TYPE;
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signal baud_lock : std_logic; -- When high, indicates output can operate.
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signal char_mismatch : std_logic; -- Indicates character did not verify
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signal baud_count : unsigned(MAIN_COUNT_WIDTH-1 downto 0); -- BAUD counter register
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signal baud_div : unsigned(MAIN_COUNT_WIDTH-1 downto 0); -- measurement for running
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signal measurement : unsigned(MAIN_COUNT_WIDTH-1 downto 0); -- measurement for verify
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signal half_check : unsigned(MAIN_COUNT_WIDTH-1 downto 0); -- Half of measurement
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signal half_measurement : unsigned(MAIN_COUNT_WIDTH-1 downto 0); -- measurement at end of start bit
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signal delta : unsigned(MAIN_COUNT_WIDTH-1 downto 0); -- Difference value
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signal target_bits : unsigned(8 downto 0); -- Character bits to compare
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signal target_bit_count : unsigned(3 downto 0); -- Contains count of bits remaining to check
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signal parity : std_logic; -- The "template bit" for checking the received parity bit.
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----------------------------------------------------------------------------
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-- Functions
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----------------------------------------------------------------------------
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function gen_even_parity(in_a : unsigned) return std_logic is
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variable i : natural;
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variable o : std_logic;
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begin
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o := '0'; -- Default value
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for i in 0 to in_a'length-1 loop
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o := o xor in_a(i);
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end loop;
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return(o);
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end;
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-----------------------------------------------------------------------------
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begin
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parity <= '1' when (rx_parity_i="00") else
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gen_even_parity(TEMPLATE_BITS) when (rx_parity_i="01") else
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not gen_even_parity(TEMPLATE_BITS) when (rx_parity_i="10") else
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'1';
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-- Form a difference between the measurement and twice the "half-measurement"
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-- Take the absolute value.
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half_check <= '0' & measurement(MAIN_COUNT_WIDTH-1 downto 1);
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delta <= (half_check-half_measurement) when (half_check>half_measurement) else
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(half_measurement-half_check);
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-- This is state machine. It checks the status of the rx_stream_i line
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-- and coordinates the measurement of the time interval of the first two
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-- bits of the received character, which is the "measurement interval."
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-- Following the measurement interval, the state machine enters a new
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-- phase of bit verification. If the measured time interval is accurate
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-- enough to measure the remaining 8 or 9 bits of the character correctly, then
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-- the measurement is accepted, and the baud rate clock is driven onto
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-- the baud_clk_o output pin. Incidentally, the process of verification
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-- effectively filters out characters which are not the desired target
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-- character for measurement. In this case, the target character is the
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-- carriage return.
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fsm_proc: process(sys_clk, sys_rst_n, parity)
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begin
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if (sys_rst_n='0') then
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fsm_state <= IDLE; -- asynchronous reset
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baud_clk_o <= '0';
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baud_lock <= '0';
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char_mismatch <= '0';
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baud_count <= (others=>'0');
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half_measurement <= (others=>'0'); -- The measurement at the end of the start bit
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measurement <= (others=>'0'); -- The candidate divider value.
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baud_div <= (others=>'0'); -- The "running" copy of measurement
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target_bits <= '1' & parity & TEMPLATE_BITS(7 downto 1);
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target_bit_count <= (others=>'0');
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elsif (sys_clk'event and sys_clk='1') then
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-- Handle the baud clock output generation, if we have achieved "baud_lock"
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if (baud_lock='1') then
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if (baud_count + 2*CLOCK_FACTOR > baud_div) then
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baud_count <= to_unsigned(CLOCK_FACTOR,baud_count'length);
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-- baud_count <= baud_count + to_unsigned(CLOCK_FACTOR,baud_count'length) - baud_div;
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-- (Compromised above for simplicity)
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-- (It could have been baud_count+CLOCK_FACTOR-baud_div)
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baud_clk_o <= '1';
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else
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baud_count <= baud_count + 2*CLOCK_FACTOR;
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baud_clk_o <= '0';
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end if;
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end if;
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case (fsm_state) is
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when IDLE =>
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char_mismatch <= '0';
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measurement <= (others=>'0');
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half_measurement <= (others=>'0');
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target_bits <= '1' & parity & TEMPLATE_BITS(7 downto 1);
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if (rx_parity_i=0) then
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target_bit_count <= to_unsigned(8,target_bit_count'length);
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else
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target_bit_count <= to_unsigned(9,target_bit_count'length); -- ODD/EVEN parity means extra bit.
|
326 |
|
|
end if;
|
327 |
|
|
if (rx_stream_i = '0') then
|
328 |
|
|
fsm_state <= MEASURE_START_BIT;
|
329 |
|
|
end if;
|
330 |
|
|
|
331 |
|
|
when MEASURE_START_BIT =>
|
332 |
|
|
if (rx_stream_i = '1') then
|
333 |
|
|
half_measurement <= measurement;
|
334 |
|
|
fsm_state <= MEASURE_DATA_BIT;
|
335 |
|
|
else
|
336 |
|
|
measurement <= measurement+1;
|
337 |
|
|
end if;
|
338 |
|
|
|
339 |
|
|
when MEASURE_DATA_BIT =>
|
340 |
|
|
-- The duration of the data bit must not be significantly different
|
341 |
|
|
-- than the duration of the start bit...
|
342 |
|
|
measurement <= measurement+1;
|
343 |
|
|
if (rx_stream_i='0') then -- Look for the end of the least significant data bit.
|
344 |
|
|
if (delta>DELTA_THRESHOLD) then
|
345 |
|
|
fsm_state <= IDLE;
|
346 |
|
|
else
|
347 |
|
|
fsm_state <= VERIFY;
|
348 |
|
|
end if;
|
349 |
|
|
end if;
|
350 |
|
|
|
351 |
|
|
when VERIFY => -- Wait for verify operations to finish
|
352 |
|
|
if (target_bit_count=0) then -- At the stop bit, check the status
|
353 |
|
|
if (char_mismatch='0') then
|
354 |
|
|
baud_div <= measurement; -- Store final verified measurement for running
|
355 |
|
|
baud_lock <= '1';
|
356 |
|
|
end if;
|
357 |
|
|
if (rx_stream_i='1') then -- Only return when there is a chance of making a valid new measurement...
|
358 |
|
|
fsm_state <= IDLE; -- Whether successful, or not, return to IDLE ("autotracking" feature.)
|
359 |
|
|
end if;
|
360 |
|
|
else
|
361 |
|
|
if (half_measurement>=measurement) then -- Initial setting leads to near mid-bit sampling.
|
362 |
|
|
half_measurement <= (others=>'0');
|
363 |
|
|
target_bits <= '0' & target_bits(target_bits'length-1 downto 1);
|
364 |
|
|
target_bit_count <= target_bit_count-1;
|
365 |
|
|
if (target_bits(0)/=rx_stream_i) then
|
366 |
|
|
char_mismatch <= '1';
|
367 |
|
|
end if;
|
368 |
|
|
else
|
369 |
|
|
half_measurement <= half_measurement+2;
|
370 |
|
|
end if;
|
371 |
|
|
end if;
|
372 |
|
|
|
373 |
|
|
--when others =>
|
374 |
|
|
-- fsm_state <= IDLE;
|
375 |
|
|
end case;
|
376 |
|
|
|
377 |
|
|
end if;
|
378 |
|
|
end process;
|
379 |
|
|
|
380 |
|
|
baud_lock_o <= baud_lock;
|
381 |
|
|
|
382 |
|
|
|
383 |
|
|
|
384 |
|
|
end beh;
|
385 |
|
|
|
386 |
|
|
|
387 |
|
|
--------------------------------------------------------------------
|
388 |
|
|
-- ...A wrapper to allow instantiating this module with
|
389 |
|
|
-- busses of type "std_logic_vector" for those who need that.
|
390 |
|
|
--
|
391 |
|
|
--------------------------------------------------------------------
|
392 |
|
|
library IEEE;
|
393 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
394 |
|
|
use IEEE.NUMERIC_STD.ALL;
|
395 |
|
|
|
396 |
|
|
library work;
|
397 |
|
|
use work.auto_baud_pack.all;
|
398 |
|
|
|
399 |
|
|
entity auto_baud_with_tracking_slv is
|
400 |
|
|
generic (
|
401 |
|
|
CLOCK_FACTOR : natural := 16; -- Output is this factor times the baud rate
|
402 |
|
|
FPGA_CLKRATE : integer := 25000000; -- FPGA system clock rate
|
403 |
|
|
MIN_BAUDRATE : integer := 57600; -- Minimum expected incoming Baud rate
|
404 |
|
|
DELTA_THRESHOLD : integer := 6 -- Max. number of sys_clks difference allowed between
|
405 |
|
|
-- "half_measurement" and "measurement"
|
406 |
|
|
);
|
407 |
|
|
port (
|
408 |
|
|
|
409 |
|
|
sys_rst_n : in std_logic;
|
410 |
|
|
sys_clk : in std_logic;
|
411 |
|
|
|
412 |
|
|
-- rate and parity
|
413 |
|
|
rx_parity_i : in std_logic_vector(1 downto 0); -- 0=none, 1=even, 2=odd
|
414 |
|
|
|
415 |
|
|
-- serial input
|
416 |
|
|
rx_stream_i : in std_logic;
|
417 |
|
|
|
418 |
|
|
-- Output
|
419 |
|
|
baud_lock_o : out std_logic;
|
420 |
|
|
baud_clk_o : out std_logic
|
421 |
|
|
);
|
422 |
|
|
end auto_baud_with_tracking_slv;
|
423 |
|
|
|
424 |
|
|
architecture beh of auto_baud_with_tracking_slv is
|
425 |
|
|
|
426 |
|
|
-- Internal signal declarations
|
427 |
|
|
signal rx_parity_u : unsigned(1 downto 0); -- The "template bit" for checking the received parity bit.
|
428 |
|
|
|
429 |
|
|
-----------------------------------------------------------------------------
|
430 |
|
|
begin
|
431 |
|
|
|
432 |
|
|
-- This module generates a serial BAUD clock automatically.
|
433 |
|
|
-- The unit synchronizes on the carriage return character, so the user
|
434 |
|
|
-- only needs to press the "enter" key for serial communications to start
|
435 |
|
|
-- working, no matter what BAUD rate and clk_i frequency are used!
|
436 |
|
|
auto_baud1 : auto_baud_with_tracking
|
437 |
|
|
generic map(
|
438 |
|
|
CLOCK_FACTOR => CLOCK_FACTOR, -- Output is this factor times the baud rate
|
439 |
|
|
FPGA_CLKRATE => FPGA_CLKRATE, -- FPGA system clock rate
|
440 |
|
|
MIN_BAUDRATE => MIN_BAUDRATE, -- Minimum expected incoming Baud rate
|
441 |
|
|
DELTA_THRESHOLD => DELTA_THRESHOLD -- Max. number of sys_clks difference allowed between
|
442 |
|
|
-- "half_measurement" and "measurement"
|
443 |
|
|
)
|
444 |
|
|
port map(
|
445 |
|
|
|
446 |
|
|
sys_rst_n => sys_rst_n,
|
447 |
|
|
sys_clk => sys_clk,
|
448 |
|
|
|
449 |
|
|
-- rate and parity
|
450 |
|
|
rx_parity_i => rx_parity_u, -- 0=none, 1=even, 2=odd
|
451 |
|
|
|
452 |
|
|
-- serial input
|
453 |
|
|
rx_stream_i => rx_stream_i,
|
454 |
|
|
|
455 |
|
|
-- Output
|
456 |
|
|
baud_lock_o => baud_lock_o,
|
457 |
|
|
baud_clk_o => baud_clk_o
|
458 |
|
|
);
|
459 |
|
|
|
460 |
|
|
rx_parity_u <= unsigned(rx_parity_i);
|
461 |
|
|
|
462 |
|
|
end beh;
|
463 |
|
|
|