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1 2 jclaytons
//-----------------------------------------------------------------------------
2
// Auto Baud with tracking core
3
//
4
// This file is part of the "auto_baud" project.
5
// http://www.opencores.org/
6
// 
7
//
8
// Description: See description below (which suffices for IP core
9
//                                     specification document.)
10
//
11
// Copyright (C) 2002 John Clayton and OPENCORES.ORG
12
//
13
// This source file may be used and distributed without restriction provided
14
// that this copyright statement is not removed from the file and that any
15
// derivative work contains the original copyright notice and the associated
16
// disclaimer.
17
//
18
// This source file is free software; you can redistribute it and/or modify
19
// it under the terms of the GNU Lesser General Public License as published
20
// by the Free Software Foundation;  either version 2.1 of the License, or
21
// (at your option) any later version.
22
//
23
// This source is distributed in the hope that it will be useful, but WITHOUT
24
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
25
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
26
// License for more details.
27
//
28
// You should have received a copy of the GNU Lesser General Public License
29
// along with this source.
30
// If not, download it from http://www.opencores.org/lgpl.shtml
31
//
32
//-----------------------------------------------------------------------------
33
//
34
// Author: John Clayton
35
// Date  : Aug. 20, 2002 Began project
36
// Update: Sep.  5, 2002 copied this file from "autobaud.v"
37
//                       Added tracking functions, and debugged them.
38
// Update: Sep. 13, 2002 Added test data.  Module complete, it works well.
39
//
40
// Description
41
//-----------------------------------------------------------------------------
42
// This is a state-machine driven core that measures transition intervals
43
// in a particular character arriving via rs232 transmission (i.e. PC serial 
44
// port.)  Measurements of time intervals between transitions in the received
45
// character are then used to generate a baud rate clock for use in serial
46
// communications back and forth with the device that originally transmitted
47
// the measured character.  The clock which is generated is in reality a
48
// clock enable pulse, one single clock wide, occurring at a rate suitable
49
// for use in serial communications.  (This means that it will be generated
50
// at 4x or 8x or 16x the actual measured baud rate of the received character.
51
// The multiplication factor is called "CLOCK_FACTOR_PP" and is a settable
52
// parameter within this module.  The parameter "CLOCK_FACTOR_PP" need not
53
// be a power of two, but it should be a number between 2 and 16 inclusive.)
54
//
55
// The particular character which is targeted for measurement and verification
56
// in this module is: carriage return (CR) = 0x0d = 13.
57
// This particular character was chosen because it is frequently used at the
58
// end of a command line, as entered at a keyboard by a human user interacting
59
// with a command interpreter.  It is anticipated that the user would press
60
// the "enter" key once upon initializing communications with the electronic
61
// device, and the resulting carriage return character would be used for 
62
// determining BAUD rate, thus allowing the device to respond at the correct
63
// rate, and to carry on further communications.  The electronic device using
64
// this "auto_baud" module adjusts its baud rate to match the baud rate of
65
// the received data.  This works for all baud rates, within certain limits,
66
// and for all system clock rates, within certain limits.
67
//
68
// Received serially, the carriage return appears as the following waveform:
69
// ________    __    ____          _______________
70
//         |__|d0|__|d2d3|________|stop
71
//        start   d1      d4d5d6d7
72
//
73
// The waveform is shown with an identical "high" time and "low" time for
74
// each bit.  However, actual measurements taken using a logic analyzer
75
// on characters received from a PC show that the times are not equal.
76
// The "high" times turned out shorter, and the "low" times longer...
77
// Therefore, this module attempts to average out this discrepancy by
78
// measuring one low time and one high time.
79
//
80
// Since the transition measurements must unavoidably contain small amounts
81
// of error, the measurements are made during the beginning 2 bits of
82
// the received character, (that is, start bit and data bit zero).
83
// Then the measurement is immediately transformed into a baud rate clock,
84
// used to verify correct reception of the remaining 8 bits of the character.
85
// If the entire character is not received correctly using the generated
86
// baud rate, then the measurement is scrapped, and the unit goes into an
87
// idle scanning mode waiting for another character to test.
88
//
89
// This effectively filters out characters that the unit is not interested in
90
// receiving (anything that is not a carriage return.)  There is a slight
91
// possibility that a group of other characters could appear by random
92
// chance in a configuration that resembles a carriage return closely enough
93
// that the unit might accept the measurement and produce a baud clock too
94
// low.  But the probability of this happening is remote enough that the
95
// unit is considered highly "robust" in normal use, especially when used
96
// for command entry by humans.  It would take a very clever user indeed, to
97
// enter the correct series of characters with the correct intercharacter
98
// timing needed to possibly "fool" the unit!
99
//
100
// (Also, the baud rate produced falls within certain limits imposed by
101
//  the hardware of the unit, which prevents the auto_baud unit from mistaking
102
//  a series of short glitches on the serial data line for a really
103
//  fast CR character.)
104
//
105
// This method of operation implies that each carriage return character
106
// received will produce a correctly generated baud rate clock.  Therefore,
107
// each and every carriage return actually causes a new baud rate clock to
108
// be produced.  However, updates occur smoothly, and there should be no
109
// apparent effect as an old BAUD clock is stopped and a new one started.
110
// The transition is done smoothly.
111
//
112
// For users who desire a single measurement at the beginning of a session
113
// to produce a steady baud clock during the entire session, there is a
114
// slightly smaller module called "auto_baud.v" which performs a single
115
// measurement, but which requires a reset pulse in order to begin measuring
116
// for a new BAUD rate.
117
//
118
// NOTES:
119
// - This module uses a counter to divide down the clk_i signal to produce the
120
//   baud_clk_o signal.  Since the frequency of baud_clk_o is nominally
121
//   CLOCK_FACTOR_PP * rx_baud_rate, where "rx_baud_rate" is the baud rate
122
//   of the received character, then the higher you make CLOCK_FACTOR_PP, the
123
//   higher the generated baud_clk_o signal frequency, and hence the lower the
124
//   resolution of the divider.  Therefore, using a lower value for the
125
//   CLOCK_FACTOR_PP will allow you to use a lower clk_i with this module.
126
// - To set LOG2_MAX_COUNT_PP, remember (max_count*CLOCK_FACTOR_PP)/Fclk_i
127
//   is the maximum measurement time that can be accomodated by the circuit.
128
//   (where Fclk_i is the frequency of clk_i, and 1/Fclk_i is the period.)
129
//   Therefore, set LOG2_MAX_COUNT_PP so that the maximum measurement time
130
//   is at least as long as 2x the baud interval of the slowest received
131
//   serial data (2x because there are two bits involved in the measurement!)
132
//   For example, for Fclk_i = 20MHz, CLOCK_FACTOR_PP = 4 and a minimum
133
//   baud rate of 115,200, you would calculate:
134
//
135
//   (max_count * CLOCK_FACTOR_PP)*1/Fclk_i >= 2/Fbaud_max
136
//
137
//   Solving for the bit width of the max_count counter...
138
//
139
//   LOG2_MAX_COUNT_PP >= ceil(log_base_2(max_count))
140
//
141
//                 >= ceil(log_base_2(2*Fclk_i/(Fbaud_max*CLOCK_FACTOR_PP)))
142
//
143
//                 >= ceil(log_base_2(2*20E6/(115200*4)))
144
//
145
//                 >= ceil(log_base_2(86.8))
146
//
147
//                 >= 7 bits.
148
//
149
// - In the above example, the maximum count would approach 87, which means
150
//   that a measurement error of 1 count is about (1/87)=approx. 1.15%.  This
151
//   is an acceptable level of error for a baud rate clock.  Notice that the
152
//   lower baud rates have an even smaller error percentage (Yes!) but that
153
//   they require a much larger measurement counter...  For instance,
154
//   to lock onto 300 baud using the same example above, would require:
155
//
156
//   LOG2_MAX_COUNT_PP >= ceil(log_base_2(40000000/1200))
157
//
158
//                     >= ceil(log_base_2(33333.3))
159
//
160
//                     >= ceil(15.024678)
161
//
162
//                     >= 16 bits.
163
//
164
// - If the percentage error for your highest desired baud rate is greater
165
//   than a few percent, you might want to use a higher Fclk_i or else a 
166
//   lower CLOCK_FACTOR_PP.
167
//
168
// - Using the default settings:  CLK_FACTOR_PP = 8, LOG2_MAX_COUNT_PP = 16
169
//   The following test results were obtained, using an actual session in
170
//   hyperterm, looking for correct readable character transmission both
171
//   directions.  (Note: These tests were performed at "human interface"
172
//   speeds.  High speed or "back-to-back" character transmission might
173
//   exhibit worse performance than these results.)
174
//
175
//   Clk_i
176
//   Freq.
177
//   (MHz)    110    300    1200   2400   4800   9600   19200  57600  115200
178
//   ------  ---------------------------------------------------------------
179
//   98       FAIL   pass   pass   pass   pass   pass   pass   pass   pass
180
//   55       FAIL   pass   pass   pass   pass   pass   pass   pass   pass
181
//   49       pass   pass   pass   pass   pass   pass   pass   pass   pass
182
//   24.5     pass   pass   pass   pass   pass   pass   pass   pass   FAIL
183
//   12       pass   pass   pass   pass   pass   pass   pass   pass   FAIL
184
//    6       pass   pass   pass   pass   pass   pass   pass   FAIL   FAIL
185
//    3       pass   pass   pass   pass   pass   FAIL   FAIL   FAIL   FAIL
186
//    1.5     pass   pass   pass   pass   FAIL   FAIL   FAIL   FAIL   FAIL
187
//
188
//
189
//-------------------------------------------------------------------------------------
190
 
191
`define LOG2_MAX_CLOCK_FACTOR 4  // Sets the size of the CLOCK_FACTOR
192
                                 // prescaler.
193
`define BITS_PER_CHAR         8  // Include parity, if used, but not
194
                                 // start and stop bits...
195
 
196
// Note: Simply changing the template bits does not reconfigure the
197
//       module to look for a different character (because a new measurement
198
//       window would have to be defined for a different character...)
199
//       The template bits are the exact bits used during verify, against
200
//       which the incoming character is checked.
201
//       The LSB of the character is discarded, and the stop bit is appended
202
//       since it is the last bit used during verify.
203
//
204
// so, for N:8:1 (no parity, 8 data bits, 1 stop bit) it is:
205
//                         = {1,(character>>1)} = 9'h086
206
// or, with parity included it is:
207
//                         = {1,parity_bit,(character>>1)} = 9'h106
208
//
209
`define TEMPLATE_BITS     9'h086  // Carriage return && termination flag
210
 
211
 
212
module auto_baud_with_tracking
213
  (
214
  clk_i,
215
  reset_i,
216
  serial_dat_i,
217
  auto_baud_locked_o,
218
  baud_clk_o
219
  );
220
 
221
 
222
// Parameters
223
 
224
// CLOCK_FACTOR_PP can be from [2..16] inclusive.
225
parameter CLOCK_FACTOR_PP = 8;     // Baud clock multiplier
226
parameter LOG2_MAX_COUNT_PP = 16;  // Bit width of measurement counter
227
 
228
// State encodings, provided as parameters
229
// for flexibility to the one instantiating the module.
230
// In general, the default values need not be changed.
231
 
232
// There is one state machines: m1.
233
// "default" state upon power-up and configuration is:
234
//    "m1_idle" because that is the all zero state.
235
 
236
parameter m1_idle          = 4'h0;  // Initial state (scanning)
237
parameter m1_measure_0     = 4'h1;  // start bit     (measuring)
238
parameter m1_measure_1     = 4'h2;  // debounce      (measuring)
239
parameter m1_measure_2     = 4'h3;  // data bit 0    (measuring)
240
parameter m1_measure_3     = 4'h4;  // debounce      (measuring)
241
parameter m1_measure_4     = 4'h5;  // measurement done (headed to verify)
242
parameter m1_verify_0      = 4'h8;  // data bit 1    (verifying)
243
parameter m1_verify_1      = 4'h9;  // data bit 2    (verifying)
244
parameter m1_run           = 4'h6;  // running
245
parameter m1_verify_failed = 4'h7;  // resetting   (headed back to idle)
246
 
247
// I/O declarations
248
input clk_i;                 // System clock input
249
input reset_i;               // Reset signal for this module
250
input serial_dat_i;          // TTL level serial data signal
251
 
252
output auto_baud_locked_o;   // Indicates BAUD clock is being generated
253
output baud_clk_o;           // BAUD clock output (actually a clock enable)
254
 
255
 
256
// Internal signal declarations
257
wire mid_bit_count;       // During measurement, advances measurement counter
258
                          // (Using the mid bit time to advance the
259
                          //  measurement timer accomplishes a timing "round"
260
                          //  so that the timing measurement is as accurate
261
                          //  as possible.)
262
                          // During verify, pulses at mid bit time are used
263
                          // to signal the state machine to check a data bit.
264
wire main_count_rollover;       // Causes main_count to reset
265
wire baud_count_rollover;       // Causes baud_count to reset
266
wire clock_count_rollover;      // Causes clock_count to reset
267
                                // (when clock_count is used as a 
268
                                //  clock_factor prescaler)
269
wire enable_clock_count;        // Logic that determines when clock_count
270
                                // should be counting
271
wire verify_done;               // Indicates finish of verification time
272
 
273
reg idle;                 // Indicates state
274
reg measure;              // Indicates state
275
reg clear_counters;       // Pulses once when measurement is done.
276
reg verify;               // Indicates state
277
reg verify_good;          // Indicates successful verify (pulse)
278
reg character_miscompare; // Indicates character did not verify
279
reg run;                  // flip-flop that indicates a valid output
280
                          // is being generated.
281
reg [`LOG2_MAX_CLOCK_FACTOR-1:0] clock_count; // Clock_factor prescaler,
282
                                              // and mid_bit counter.
283
reg [LOG2_MAX_COUNT_PP-1:0] main_count;       // Main counter register
284
reg [LOG2_MAX_COUNT_PP-1:0] baud_count;       // BAUD counter register
285
reg [LOG2_MAX_COUNT_PP-1:0] measurement;      // measurement for verify
286
reg [LOG2_MAX_COUNT_PP-1:0] baud;             // measurement for running
287
reg [`BITS_PER_CHAR:0] target_bits;           // Character bits to compare
288
// (lsb is not needed, since it is used up during measurement time,
289
//  but the stop bit and possible parity bit are needed.)
290
 
291
    // For the state machine
292
reg [3:0] m1_state;
293
reg [3:0] m1_next_state;
294
 
295
 
296
 
297
//--------------------------------------------------------------------------
298
// Instantiations
299
//--------------------------------------------------------------------------
300
 
301
 
302
//--------------------------------------------------------------------------
303
// Module code
304
//--------------------------------------------------------------------------
305
 
306
 
307
// This is the CLOCK_FACTOR_PP prescaler and also mid_bit_count counter
308
assign enable_clock_count = measure || (verify && main_count_rollover);
309
always @(posedge clk_i or posedge reset_i)
310
begin
311
  if (reset_i) clock_count <= 0;
312
  else if (clear_counters) clock_count <= 0;
313
  else if (enable_clock_count)
314
  begin  // Must have been clk_i edge
315
    if (clock_count_rollover) clock_count <= 0;
316
    else clock_count <= clock_count + 1;
317
  end
318
end
319
// Counter rollover condition
320
assign clock_count_rollover = (clock_count == (CLOCK_FACTOR_PP-1));
321
// This condition signals the middle of a bit time, for use during the
322
// verify stage.  Also, this signal is used to advance the main count,
323
// instead of "clock_count_rollover."  This produces an effective "rounding"
324
// operation for the measurement (which would otherwise "truncate" any
325
// fraction of time contained in this counter at the instant the measurement
326
// is finished.
327
// (The "enable_clock_count" is included in order to make the pulse narrow,
328
//  only one clock wide...)
329
assign mid_bit_count = (
330
                        (clock_count == ((CLOCK_FACTOR_PP>>1)-1))
331
                        && enable_clock_count
332
                        );
333
 
334
// This is the main counter.  During measurement, it advances once for
335
// each CLOCK_FACTOR_PP cycles of clk_i.  This accumulated measurement
336
// is then latched into "measurement" when the state machine determines that
337
// the measurement interval is finished.
338
// During verify time (when the new candidate baud rate clock is being tested)
339
// this counter is allowed to run freely, advancing once each clk_i, but being
340
// reset when it reaches a total count of "measurement" clock cycles.
341
always @(posedge clk_i or posedge reset_i)
342
begin
343
  if (reset_i) main_count <= 0;
344
  else // must have been clk_i edge
345
  begin
346
    // Clear main count when measurement is done
347
    if (clear_counters) main_count <= 0;
348
    // If measuring, advance once per CLOCK_FACTOR_PP clk_i pulses.
349
    else if (measure && mid_bit_count) main_count <= main_count + 1;
350
    // If verifying or running, check reset conditions, 
351
    // otherwise advance always.
352
    else if (verify)
353
    begin
354
      if (main_count_rollover) main_count <= 0;
355
      else main_count <= main_count + 1;
356
    end
357
  end
358
end
359
// This is the "verify" baud clock signal... not the final output one.
360
assign main_count_rollover = (main_count == measurement);
361
 
362
 
363
// This is the BAUD counter.  Once a measurement has been verified, it is
364
// stored in "baud" and the signal "run" goes high.  From then on, this
365
// counter is allowed to run freely, advancing once each clk_i, but being
366
// reset when it reaches a total count of "baud" clock cycles.  This
367
// counter's reset signal is the output baud rate clock.
368
always @(posedge clk_i or posedge reset_i)
369
begin
370
  if (reset_i) baud_count <= 0;
371
  else // must have been clk_i edge
372
  begin
373
    // If running, advance freely
374
    if (run)
375
    begin
376
      if (baud_count_rollover) baud_count <= 0;
377
      else baud_count <= baud_count + 1;
378
    end
379
  end
380
end
381
assign baud_count_rollover = (baud_count == baud);
382
 
383
// This is a shift register used to provide "target" character bits one at
384
// a time for verification as they are "received" (sampled) using the
385
// candidate baud clock.
386
always @(posedge clk_i or posedge reset_i)
387
begin
388
  if (reset_i) target_bits <= `TEMPLATE_BITS;
389
  else // must have been a clock edge
390
  begin
391
    if (~verify) target_bits <= `TEMPLATE_BITS;
392
    if (verify && mid_bit_count) target_bits <= {0,(target_bits>>1)};
393
  end
394
end
395
// It is done when only the stop bit is left in the shift register.
396
assign verify_done = (
397
                       (target_bits == 1)
398
                       && verify
399
                       && mid_bit_count
400
                      );
401
 
402
// This is a flip-flop used to keep track of whether the verify operation
403
// is succeeding or not.  Any target bits that do not match the received
404
// data at the sampling edge, will cause the verify_failed bit to go high.
405
// This is what the state machine looks at to determine whether it passed
406
// or not.
407
always @(posedge clk_i or posedge reset_i)
408
begin
409
  if (reset_i) character_miscompare <= 0;
410
  else  // Must have been a clock edge
411
  begin
412
    if (idle) character_miscompare <= 0;
413
    if (verify && mid_bit_count
414
        && (target_bits[0] ^ serial_dat_i)) character_miscompare <= 1;
415
  end
416
end
417
 
418
 
419
// This is the measurement storage latch.  The final measured time count
420
// from main_count is stored in this latch upon completion of the measurement
421
// interval.  The value stored in this latch is used for the baud clock
422
// generated during verify, but a different register holds the actual value
423
// being used to generate output.
424
always @(posedge clk_i or posedge idle)
425
begin
426
  // Set to all ones during idle (asynchronous).
427
  if (idle) measurement <= -1;
428
  // Otherwise, there must have been a clk_i edge
429
  // When the measurement is done, the counters are cleared, and the time
430
  // interval must be stored before it is cleared away...
431
  // This also causes a store following a failed verify state on the way back
432
  // into idle, but the idle state clears out the false measurement anyway.
433
  else if (clear_counters) measurement <= (main_count>>1);
434
end
435
 
436
// This is the BAUD storage latch.  The final verified time count
437
// from the "measurement" register is stored in this register after a good
438
// verify.  The value stored in this latch is used in conjunction with
439
// baud_count to produce the baud clock which is sent to the output.
440
always @(posedge clk_i or posedge reset_i)
441
begin
442
  // Set to all ones during reset (asynchronous).
443
  if (reset_i) baud <= -1;
444
  // Otherwise, there must have been a clk_i edge
445
  // When the measurement is done, the counters are cleared, and the time
446
  // interval must be stored before it is cleared away...
447
  // This also causes a store following a failed verify state on the way back
448
  // into idle, but the idle state clears out the false measurement anyway.
449
  else if (verify_good) baud <= measurement;
450
end
451
 
452
// This is a flip-flop used to keep track of whether the unit is producing
453
// a baud clock or not.  Initially following reset, there is no baud clock
454
// being produced.  But, once a single measurement is verified, then the
455
// clock is produced and tracking changes are made over time.  Thus, this
456
// bit goes high as a result of the first "verify_good" pulse, and it remains
457
// high forever, until the unit is reset.
458
always @(posedge clk_i or posedge reset_i)
459
begin
460
  if (reset_i) run <= 0;
461
  else  // Must have been a clock edge
462
  begin
463
    if (verify_good) run <= 1;
464
  end
465
end
466
 
467
assign baud_clk_o = baud_count_rollover;
468
 
469
 
470
// This is state machine m1.  It checks the status of the serial_dat_i line
471
// and coordinates the measurement of the time interval of the first two
472
// bits of the received character, which is the "measurement interval."
473
// Following the measurement interval, the state machine enters a new
474
// phase of bit verification.  If the measured time interval is accurate
475
// enough to measure the remaining 8 bits of the character correctly, then
476
// the measurement is accepted, and the baud rate clock is driven onto
477
// the baud_clk_o output pin.  Incidentally, the process of verification
478
// effectively filters out all characters which are not the desired target
479
// character for measurement.  In this case, the target character is the
480
// carriage return.
481
 
482
 
483
// State register
484
always @(posedge clk_i or posedge reset_i)
485
begin : m1_state_register
486
  if (reset_i) m1_state <= m1_idle;          // asynchronous reset
487
  else m1_state <= m1_next_state;
488
end
489
 
490
// State transition logic
491
always @(m1_state
492
         or mid_bit_count
493
         or serial_dat_i
494
         or verify_done
495
         or character_miscompare
496
         )
497
begin : m1_state_logic
498
 
499
  // Default values for outputs.  The individual states can override these.
500
  idle <= 1'b0;
501
  verify_good <= 1'b0;
502
  measure <= 1'b0;
503
  clear_counters <= 1'b0;
504
  verify <= 1'b0;
505
 
506
  case (m1_state) // synthesis parallel_case
507
 
508
    m1_idle :
509
      begin
510
        idle <= 1'b1;
511
        if (serial_dat_i == 0) m1_next_state <= m1_measure_0;
512
        else m1_next_state <= m1_idle;
513
      end
514
 
515
    m1_measure_0 :
516
      begin
517
        measure <= 1'b1;
518
        // Check at mid bit time, to make sure serial line is still low...
519
        // (At this time, "mid_bit_count" is simply CLOCK_FACTOR_PP>>1 clk_i's.)
520
        if (mid_bit_count && ~serial_dat_i) m1_next_state <= m1_measure_1;
521
        // If it is not low, then it must have been a "glitch"...
522
        else if (mid_bit_count && serial_dat_i) m1_next_state <= m1_idle;
523
        else m1_next_state <= m1_measure_0;
524
      end
525
 
526
    m1_measure_1 :
527
      begin
528
        measure <= 1'b1;
529
        // Look for first data bit (high).
530
        if (serial_dat_i) m1_next_state <= m1_measure_2;
531
        // If it is not high keep waiting...
532
        // (Put detection of measurement overflow in here if necessary...)
533
        else m1_next_state <= m1_measure_1;
534
      end
535
 
536
    m1_measure_2 :
537
      begin
538
        measure <= 1'b1;
539
        // Check using mid bit time, to make sure serial line is still high...
540
        // (At this time, "mid_bit_count" is simply CLOCK_FACTOR_PP>>1 clk_i's.)
541
        if (mid_bit_count && serial_dat_i) m1_next_state <= m1_measure_3;
542
        // If it is not high, then it must have been a "glitch"...
543
        else if (mid_bit_count && ~serial_dat_i) m1_next_state <= m1_idle;
544
        else m1_next_state <= m1_measure_2;
545
      end
546
 
547
    m1_measure_3 :
548
      begin
549
        measure <= 1'b1;
550
        // Look for end of measurement interval (low)
551
        if (!serial_dat_i) m1_next_state <= m1_measure_4;
552
        // If it is not high keep waiting...
553
        // (Put detection of measurement overflow in here if necessary...)
554
        else m1_next_state <= m1_measure_3;
555
      end
556
 
557
    // This state outputs a reset pulse, to clear counters and store the
558
    // measurement from main_count.
559
    m1_measure_4 :
560
      begin
561
        clear_counters <= 1'b1; // Clears counters, stores measurement
562
        m1_next_state <= m1_verify_0;
563
      end
564
 
565
    m1_verify_0 :  // Wait for verify operations to finish
566
      begin
567
        verify <= 1'b1;
568
        if (verify_done) m1_next_state <= m1_verify_1;
569
        else m1_next_state <= m1_verify_0;
570
      end
571
 
572
    // NOTE: This "extra" state is needed because the character_miscompare
573
    //       information is not valid until 1 cycle after verify_done is
574
    //       active.
575
    m1_verify_1 :  // Checks for character miscompare
576
      begin
577
        if (character_miscompare) m1_next_state <= m1_verify_failed;
578
        else m1_next_state <= m1_run;
579
      end
580
 
581
    m1_verify_failed : // Resets counters on the way back to idle
582
      begin
583
        clear_counters <= 1'b1;
584
        m1_next_state <= m1_idle;
585
      end
586
 
587
    // This state is for successful verification results!
588
    // Since this is a tracking unit, the "run" output is used as a pulse
589
    // to store the now verified rate.
590
    m1_run :
591
      begin
592
        verify_good <= 1'b1;
593
        m1_next_state <= m1_idle;
594
      end
595
 
596
    default : m1_next_state <= m1_idle;
597
  endcase
598
end
599
 
600
 
601
assign auto_baud_locked_o = run;
602
 
603
 
604
endmodule
605
 
606
//`undef LOG2_MAX_CLOCK_FACTOR

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