URL https://opencores.org/ocsvn/avalon-wishbone-bridge/avalon-wishbone-bridge/trunk

Subversion Repositories avalon-wishbone-bridge

[/] [avalon-wishbone-bridge/] [trunk/] [RTL/] [av2wb.sv] - Blame information for rev 2

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module av2wb #(AW=32,DW=64,TW=2,MAX_OUTSTANDING=2) (input clk,input rst_n,avalon_if.s_cb av, wb_if.m_drv_cb wb);
parameter STALL=2'b01,
          TRANSFER=2'b10;
 
logic [1:0] state, n_state;
logic av_valid,wb_ready;
always @* av_valid = av.chipselect && (av.read || av.write);
logic [1:0] n_count,count,ack_reg;
//conversion of req-ack to enable
//always @(wb.stb or wb.ack) begin
always @* begin
//      case({wb.stb,wb.ack})
//              2'b10: if(state ==TRANSFER) n_count<=count+1;
//              2'b11: if(state ==TRANSFER) n_count<=count; else n_count<=count-1;
//              2'b01: n_count<=count-1;
//              default: n_count<=count;
//      endcase
                if(n_count< MAX_OUTSTANDING)
                        wb_ready <=1'b1;
                else if(state==STALL || state ==TRANSFER)
                        wb_ready <=1'b0;
end
 
 
always @(posedge clk or negedge rst_n)
        if(!rst_n) begin
                        state <=STALL;
                        count<='0;
                   end
        else    begin
                   state <=n_state;
                   count<=n_count;
                end
 
 
 
//always @(state or av_valid or wb_ready or wb.stb) begin
always @* begin
        n_state<='bx;
 
        n_count<=count;
        //do_stall;
        case(state)
                STALL: begin
                                if(av_valid && wb_ready)
                                        n_state<=TRANSFER;
                                else
                                        n_state<=STALL;
                                //if(wb.ack) n_count<=count-1;
                                //if(wb.ack) wb_ready<=1'b1;
                                //else wb_ready<=1'b0;
                                if(wb.ack==1'b1)
                                        n_count<=count-1;
                                else
                                        n_count<=count;
 
                          end
 
                TRANSFER: begin
                                if(av_valid && wb_ready)
                                        n_state<=TRANSFER;
                                else
                                        n_state<=STALL;
                                //do_transfer;
                                //if(!wb.ack) n_count<=count+1;
                                //if(wb.ack) wb_ready<=1'b1;
                                //else wb_ready<=1'b0;
                                if(wb.ack==1'b1)
                                        n_count<=count;
                                else
                                        n_count<=count+1;
 
                          end
        endcase
end
 
always @(posedge clk or negedge rst_n)
        if(!rst_n) do_stall;
        else begin
                case(state)
                        STALL:do_stall();
                        TRANSFER:do_transfer();
                        default: do_stall();
                endcase
        end
always @* begin
        av.waitrequest<=!(wb_ready);
        av.readdata<=wb.dat_i;
        av.readdatavalid<=wb.ack;
 
end
task do_stall;
 
        wb.dat_o<='0;
        wb.tgd_o<='0;
        wb.adr<='0;
        //wb.cyc<=!(wb_ready);
        wb.cyc<=count[1] || count[0];
        wb.lock<=1'b0;
        wb.sel<=av.byteenable;
        wb.stb<=!(wb_ready);
        //wb.stb<=1'b0;
        wb.tga<='0;
        wb.tgc<='0;
        wb.we<='0;
endtask
//task do_transfer(avalon_if.s_cb av, wishbone_b3_if.m_drv_cb wb);
task do_transfer;
        wb.dat_i<=av.writedata;
        //wb.tgd_o<= av.tag;
        wb.adr<=av.address;
        wb.cyc<=1'b1;
        wb.stb<=1'b1;
        if(av.read) wb.we<=1'b0;
        else        wb.we<=1'b1;
endtask
endmodule
//task do_stall(avalon_if av, wishbone_b3_if  wb);

Line No.	Rev	Author	Line
1	2	sumanta.ch	`module av2wb #(AW=32,DW=64,TW=2,MAX_OUTSTANDING=2) (input clk,input rst_n,avalon_if.s_cb av, wb_if.m_drv_cb wb);`
2			`parameter STALL=2'b01,`
3			`TRANSFER=2'b10;`
4
5			`logic [1:0] state, n_state;`
6			`logic av_valid,wb_ready;`
7			`always @* av_valid = av.chipselect && (av.read \|\| av.write);`
8			`logic [1:0] n_count,count,ack_reg;`
9			`//conversion of req-ack to enable`
10			`//always @(wb.stb or wb.ack) begin`
11			`always @* begin`
12			`// case({wb.stb,wb.ack})`
13			`// 2'b10: if(state ==TRANSFER) n_count<=count+1;`
14			`// 2'b11: if(state ==TRANSFER) n_count<=count; else n_count<=count-1;`
15			`// 2'b01: n_count<=count-1;`
16			`// default: n_count<=count;`
17			`// endcase`
18			`if(n_count< MAX_OUTSTANDING)`
19			`wb_ready <=1'b1;`
20			`else if(state==STALL \|\| state ==TRANSFER)`
21			`wb_ready <=1'b0;`
22			`end`
23
24
25			`always @(posedge clk or negedge rst_n)`
26			`if(!rst_n) begin`
27			`state <=STALL;`
28			`count<='0;`
29			`end`
30			`else begin`
31			`state <=n_state;`
32			`count<=n_count;`
33			`end`
34
35
36
37			`//always @(state or av_valid or wb_ready or wb.stb) begin`
38			`always @* begin`
39			`n_state<='bx;`
40
41			`n_count<=count;`
42			`//do_stall;`
43			`case(state)`
44			`STALL: begin`
45			`if(av_valid && wb_ready)`
46			`n_state<=TRANSFER;`
47			`else`
48			`n_state<=STALL;`
49			`//if(wb.ack) n_count<=count-1;`
50			`//if(wb.ack) wb_ready<=1'b1;`
51			`//else wb_ready<=1'b0;`
52			`if(wb.ack==1'b1)`
53			`n_count<=count-1;`
54			`else`
55			`n_count<=count;`
56
57			`end`
58
59			`TRANSFER: begin`
60			`if(av_valid && wb_ready)`
61			`n_state<=TRANSFER;`
62			`else`
63			`n_state<=STALL;`
64			`//do_transfer;`
65			`//if(!wb.ack) n_count<=count+1;`
66			`//if(wb.ack) wb_ready<=1'b1;`
67			`//else wb_ready<=1'b0;`
68			`if(wb.ack==1'b1)`
69			`n_count<=count;`
70			`else`
71			`n_count<=count+1;`
72
73			`end`
74			`endcase`
75			`end`
76
77			`always @(posedge clk or negedge rst_n)`
78			`if(!rst_n) do_stall;`
79			`else begin`
80			`case(state)`
81			`STALL:do_stall();`
82			`TRANSFER:do_transfer();`
83			`default: do_stall();`
84			`endcase`
85			`end`
86			`always @* begin`
87			`av.waitrequest<=!(wb_ready);`
88			`av.readdata<=wb.dat_i;`
89			`av.readdatavalid<=wb.ack;`
90
91			`end`
92			`task do_stall;`
93
94			`wb.dat_o<='0;`
95			`wb.tgd_o<='0;`
96			`wb.adr<='0;`
97			`//wb.cyc<=!(wb_ready);`
98			`wb.cyc<=count[1] \|\| count[0];`
99			`wb.lock<=1'b0;`
100			`wb.sel<=av.byteenable;`
101			`wb.stb<=!(wb_ready);`
102			`//wb.stb<=1'b0;`
103			`wb.tga<='0;`
104			`wb.tgc<='0;`
105			`wb.we<='0;`
106			`endtask`
107			`//task do_transfer(avalon_if.s_cb av, wishbone_b3_if.m_drv_cb wb);`
108			`task do_transfer;`
109			`wb.dat_i<=av.writedata;`
110			`//wb.tgd_o<= av.tag;`
111			`wb.adr<=av.address;`
112			`wb.cyc<=1'b1;`
113			`wb.stb<=1'b1;`
114			`if(av.read) wb.we<=1'b0;`
115			`else wb.we<=1'b1;`
116			`endtask`
117			`endmodule`
118			`//task do_stall(avalon_if av, wishbone_b3_if wb);`

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[/] [avalon-wishbone-bridge/] [trunk/] [RTL/] [av2wb.sv] - Blame information for rev 2