1 |
2 |
tobil |
--------------------------------------------------------------------------------
|
2 |
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Release 11.1 Trace (nt)
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3 |
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Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
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4 |
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5 |
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C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
|
6 |
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C:/EDAptability/coremultiplier/reference/avr/ise/ise_s3_cm3_one_syneda/ise_s3_cm3_one_syneda/ise_s3_cm3_one_syneda.ise
|
7 |
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-intstyle ise -v 3 -s 4 -fastpaths -xml avr_core_cm3_top.twx
|
8 |
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avr_core_cm3_top.ncd -o avr_core_cm3_top.twr avr_core_cm3_top.pcf -ucf
|
9 |
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avr_core_cm3_top.ucf
|
10 |
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|
11 |
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Design file: avr_core_cm3_top.ncd
|
12 |
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Physical constraint file: avr_core_cm3_top.pcf
|
13 |
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Device,package,speed: xc3s200a,fg320,-4 (PRODUCTION 1.41 2009-03-03)
|
14 |
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Report level: verbose report
|
15 |
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|
16 |
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Environment Variable Effect
|
17 |
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-------------------- ------
|
18 |
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NONE No environment variables were set
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19 |
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--------------------------------------------------------------------------------
|
20 |
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21 |
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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22 |
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option. All paths that are not constrained will be reported in the
|
23 |
|
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unconstrained paths section(s) of the report.
|
24 |
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
|
25 |
|
|
a 50 Ohm transmission line loading model. For the details of this model,
|
26 |
|
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and for more information on accounting for different loading conditions,
|
27 |
|
|
please see the device datasheet.
|
28 |
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|
29 |
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================================================================================
|
30 |
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Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 10 ns HIGH 50%;
|
31 |
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|
32 |
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203315 paths analyzed, 3358 endpoints analyzed, 877 failing endpoints
|
33 |
|
|
877 timing errors detected. (877 setup errors, 0 hold errors, 0 component switching limit errors)
|
34 |
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Minimum period is 12.532ns.
|
35 |
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--------------------------------------------------------------------------------
|
36 |
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Slack (setup path): -2.532ns (requirement - (data path - clock path skew + uncertainty))
|
37 |
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Source: AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_7_cml_1_7 (FF)
|
38 |
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Destination: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/bit_test_op_out_cml_2 (FF)
|
39 |
|
|
Requirement: 10.000ns
|
40 |
|
|
Data Path Delay: 12.400ns (Levels of Logic = 9)
|
41 |
|
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Clock Path Skew: -0.132ns (0.555 - 0.687)
|
42 |
|
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Source Clock: cp2_BUFGP rising at 0.000ns
|
43 |
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Destination Clock: cp2_BUFGP rising at 10.000ns
|
44 |
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Clock Uncertainty: 0.000ns
|
45 |
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|
46 |
|
|
Maximum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_7_cml_1_7 to AVR_Core_cm3_Inst/pm_fetch_dec_Inst/bit_test_op_out_cml_2
|
47 |
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Location Delay type Delay(ns) Physical Resource
|
48 |
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Logical Resource(s)
|
49 |
|
|
------------------------------------------------- -------------------
|
50 |
|
|
SLICE_X15Y35.XQ Tcko 0.591 AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_7_cml_1<7>
|
51 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_7_cml_1_7
|
52 |
|
|
SLICE_X20Y18.F3 net (fanout=1) 1.251 AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_7_cml_1<7>
|
53 |
|
|
SLICE_X20Y18.X Tilo 0.692 N507
|
54 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>86_SW0
|
55 |
|
|
SLICE_X29Y16.G4 net (fanout=1) 1.137 N507
|
56 |
|
|
SLICE_X29Y16.Y Tilo 0.648 AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>87
|
57 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>86
|
58 |
|
|
SLICE_X29Y16.F3 net (fanout=1) 0.043 AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>86/O
|
59 |
|
|
SLICE_X29Y16.X Tilo 0.643 AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>87
|
60 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>87
|
61 |
|
|
SLICE_X29Y18.G4 net (fanout=1) 0.330 AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>87
|
62 |
|
|
SLICE_X29Y18.X Tif5x 0.924 AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>104
|
63 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>104_F
|
64 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>104
|
65 |
|
|
SLICE_X25Y22.G2 net (fanout=1) 0.741 AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>104
|
66 |
|
|
SLICE_X25Y22.Y Tilo 0.648 AVR_Core_cm3_Inst/ALU_Inst/swap_out_cml_2<3>
|
67 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>170
|
68 |
|
|
SLICE_X25Y22.F3 net (fanout=1) 0.043 AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>170/O
|
69 |
|
|
SLICE_X25Y22.X Tilo 0.643 AVR_Core_cm3_Inst/ALU_Inst/swap_out_cml_2<3>
|
70 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/sg_tmp_rd_data_31<7>236
|
71 |
|
|
SLICE_X14Y13.G4 net (fanout=11) 1.312 AVR_Core_cm3_Inst/reg_rd_out<7>
|
72 |
|
|
SLICE_X14Y13.Y Tilo 0.707 N288
|
73 |
|
|
AVR_Core_cm3_Inst/BP_Inst/bit_test_mux_out_7_mux000012
|
74 |
|
|
SLICE_X15Y12.BX net (fanout=2) 0.446 AVR_Core_cm3_Inst/BP_Inst/bit_test_mux_out_7_mux000012
|
75 |
|
|
SLICE_X15Y12.X Tbxx 0.756 N289
|
76 |
|
|
AVR_Core_cm3_Inst/BP_Inst/bit_test_mux_out_7_mux0000294_SW1
|
77 |
|
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SLICE_X15Y13.F2 net (fanout=1) 0.123 N289
|
78 |
|
|
SLICE_X15Y13.CLK Tfck 0.722 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/bit_test_op_out_cml_2
|
79 |
|
|
AVR_Core_cm3_Inst/BP_Inst/bit_test_op_out281
|
80 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/bit_test_op_out_cml_2
|
81 |
|
|
------------------------------------------------- ---------------------------
|
82 |
|
|
Total 12.400ns (6.974ns logic, 5.426ns route)
|
83 |
|
|
(56.2% logic, 43.8% route)
|
84 |
|
|
|
85 |
|
|
--------------------------------------------------------------------------------
|
86 |
|
|
Slack (setup path): -2.487ns (requirement - (data path - clock path skew + uncertainty))
|
87 |
|
|
Source: AVR_Core_cm3_Inst/ALU_Inst/idc_adiw_cml_2 (FF)
|
88 |
|
|
Destination: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0 (FF)
|
89 |
|
|
Requirement: 10.000ns
|
90 |
|
|
Data Path Delay: 12.424ns (Levels of Logic = 9)
|
91 |
|
|
Clock Path Skew: -0.063ns (0.666 - 0.729)
|
92 |
|
|
Source Clock: cp2_BUFGP rising at 0.000ns
|
93 |
|
|
Destination Clock: cp2_BUFGP rising at 10.000ns
|
94 |
|
|
Clock Uncertainty: 0.000ns
|
95 |
|
|
|
96 |
|
|
Maximum Data Path: AVR_Core_cm3_Inst/ALU_Inst/idc_adiw_cml_2 to AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0
|
97 |
|
|
Location Delay type Delay(ns) Physical Resource
|
98 |
|
|
Logical Resource(s)
|
99 |
|
|
------------------------------------------------- -------------------
|
100 |
|
|
SLICE_X13Y22.XQ Tcko 0.591 AVR_Core_cm3_Inst/ALU_Inst/idc_adiw_cml_2
|
101 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/idc_adiw_cml_2
|
102 |
|
|
SLICE_X25Y19.G4 net (fanout=8) 1.082 AVR_Core_cm3_Inst/ALU_Inst/idc_adiw_cml_2
|
103 |
|
|
SLICE_X25Y19.Y Tilo 0.648 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or0000
|
104 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or000020
|
105 |
|
|
SLICE_X25Y19.F2 net (fanout=1) 0.430 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or000020/O
|
106 |
|
|
SLICE_X25Y19.X Tilo 0.643 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or0000
|
107 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or000030
|
108 |
|
|
SLICE_X26Y14.G3 net (fanout=8) 0.829 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or0000
|
109 |
|
|
SLICE_X26Y14.Y Tilo 0.707 AVR_Core_cm3_Inst/alu_data_out<6>
|
110 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_6_or000038
|
111 |
|
|
SLICE_X26Y14.F4 net (fanout=1) 0.060 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_6_or000038/O
|
112 |
|
|
SLICE_X26Y14.X Tilo 0.692 AVR_Core_cm3_Inst/alu_data_out<6>
|
113 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_6_or000046
|
114 |
|
|
SLICE_X24Y15.F4 net (fanout=2) 0.363 AVR_Core_cm3_Inst/alu_data_out<6>
|
115 |
|
|
SLICE_X24Y15.X Tilo 0.692 AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq000025
|
116 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq000025
|
117 |
|
|
SLICE_X13Y20.G2 net (fanout=2) 1.032 AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq000025
|
118 |
|
|
SLICE_X13Y20.Y Tilo 0.648 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
|
119 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_cml_out
|
120 |
|
|
SLICE_X13Y20.F3 net (fanout=2) 0.059 AVR_Core_cm3_Inst/alu_z_flag_out
|
121 |
|
|
SLICE_X13Y20.X Tilo 0.643 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
|
122 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
|
123 |
|
|
SLICE_X9Y22.G4 net (fanout=3) 0.670 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
|
124 |
|
|
SLICE_X9Y22.Y Tilo 0.648 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/pc_for_interrupt<9>
|
125 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<0>141
|
126 |
|
|
SLICE_X8Y33.G3 net (fanout=19) 1.170 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/N12
|
127 |
|
|
SLICE_X8Y33.CLK Tgck 0.817 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nicall_st0
|
128 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0_mux00011
|
129 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0
|
130 |
|
|
------------------------------------------------- ---------------------------
|
131 |
|
|
Total 12.424ns (6.729ns logic, 5.695ns route)
|
132 |
|
|
(54.2% logic, 45.8% route)
|
133 |
|
|
|
134 |
|
|
--------------------------------------------------------------------------------
|
135 |
|
|
Slack (setup path): -2.468ns (requirement - (data path - clock path skew + uncertainty))
|
136 |
|
|
Source: AVR_Core_cm3_Inst/ALU_Inst/idc_cpse_cml_2 (FF)
|
137 |
|
|
Destination: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0 (FF)
|
138 |
|
|
Requirement: 10.000ns
|
139 |
|
|
Data Path Delay: 12.429ns (Levels of Logic = 9)
|
140 |
|
|
Clock Path Skew: -0.039ns (0.666 - 0.705)
|
141 |
|
|
Source Clock: cp2_BUFGP rising at 0.000ns
|
142 |
|
|
Destination Clock: cp2_BUFGP rising at 10.000ns
|
143 |
|
|
Clock Uncertainty: 0.000ns
|
144 |
|
|
|
145 |
|
|
Maximum Data Path: AVR_Core_cm3_Inst/ALU_Inst/idc_cpse_cml_2 to AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0
|
146 |
|
|
Location Delay type Delay(ns) Physical Resource
|
147 |
|
|
Logical Resource(s)
|
148 |
|
|
------------------------------------------------- -------------------
|
149 |
|
|
SLICE_X12Y21.XQ Tcko 0.631 AVR_Core_cm3_Inst/ALU_Inst/idc_cpse_cml_2
|
150 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/idc_cpse_cml_2
|
151 |
|
|
SLICE_X12Y22.F1 net (fanout=2) 0.763 AVR_Core_cm3_Inst/ALU_Inst/idc_cpse_cml_2
|
152 |
|
|
SLICE_X12Y22.X Tilo 0.692 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/sbiw_st
|
153 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or000015
|
154 |
|
|
SLICE_X25Y19.F4 net (fanout=1) 0.670 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or000015
|
155 |
|
|
SLICE_X25Y19.X Tilo 0.643 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or0000
|
156 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or000030
|
157 |
|
|
SLICE_X26Y14.G3 net (fanout=8) 0.829 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_0_or0000
|
158 |
|
|
SLICE_X26Y14.Y Tilo 0.707 AVR_Core_cm3_Inst/alu_data_out<6>
|
159 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_6_or000038
|
160 |
|
|
SLICE_X26Y14.F4 net (fanout=1) 0.060 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_6_or000038/O
|
161 |
|
|
SLICE_X26Y14.X Tilo 0.692 AVR_Core_cm3_Inst/alu_data_out<6>
|
162 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_6_or000046
|
163 |
|
|
SLICE_X24Y15.F4 net (fanout=2) 0.363 AVR_Core_cm3_Inst/alu_data_out<6>
|
164 |
|
|
SLICE_X24Y15.X Tilo 0.692 AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq000025
|
165 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq000025
|
166 |
|
|
SLICE_X13Y20.G2 net (fanout=2) 1.032 AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq000025
|
167 |
|
|
SLICE_X13Y20.Y Tilo 0.648 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
|
168 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_z_flag_out_cml_out
|
169 |
|
|
SLICE_X13Y20.F3 net (fanout=2) 0.059 AVR_Core_cm3_Inst/alu_z_flag_out
|
170 |
|
|
SLICE_X13Y20.X Tilo 0.643 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
|
171 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
|
172 |
|
|
SLICE_X9Y22.G4 net (fanout=3) 0.670 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/skip_inst_start
|
173 |
|
|
SLICE_X9Y22.Y Tilo 0.648 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/pc_for_interrupt<9>
|
174 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<0>141
|
175 |
|
|
SLICE_X8Y33.G3 net (fanout=19) 1.170 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/N12
|
176 |
|
|
SLICE_X8Y33.CLK Tgck 0.817 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nicall_st0
|
177 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0_mux00011
|
178 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/nirq_st0
|
179 |
|
|
------------------------------------------------- ---------------------------
|
180 |
|
|
Total 12.429ns (6.813ns logic, 5.616ns route)
|
181 |
|
|
(54.8% logic, 45.2% route)
|
182 |
|
|
|
183 |
|
|
--------------------------------------------------------------------------------
|
184 |
|
|
|
185 |
|
|
Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 10 ns HIGH 50%;
|
186 |
|
|
--------------------------------------------------------------------------------
|
187 |
|
|
Slack (hold path): 0.656ns (requirement - (clock path skew + uncertainty - data path))
|
188 |
|
|
Source: AVR_Core_cm3_Inst/GPRF_Inst/register_file_6_6 (FF)
|
189 |
|
|
Destination: AVR_Core_cm3_Inst/GPRF_Inst/Mshreg_register_file_cml_2_6_6/SRL16E (FF)
|
190 |
|
|
Requirement: 0.000ns
|
191 |
|
|
Data Path Delay: 0.722ns (Levels of Logic = 1)
|
192 |
|
|
Clock Path Skew: 0.066ns (0.383 - 0.317)
|
193 |
|
|
Source Clock: cp2_BUFGP rising at 10.000ns
|
194 |
|
|
Destination Clock: cp2_BUFGP rising at 10.000ns
|
195 |
|
|
Clock Uncertainty: 0.000ns
|
196 |
|
|
|
197 |
|
|
Minimum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/register_file_6_6 to AVR_Core_cm3_Inst/GPRF_Inst/Mshreg_register_file_cml_2_6_6/SRL16E
|
198 |
|
|
Location Delay type Delay(ns) Physical Resource
|
199 |
|
|
Logical Resource(s)
|
200 |
|
|
------------------------------------------------- -------------------
|
201 |
|
|
SLICE_X29Y41.YQ Tcko 0.464 AVR_Core_cm3_Inst/GPRF_Inst/register_file_6_7
|
202 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/register_file_6_6
|
203 |
|
|
SLICE_X30Y40.BY net (fanout=4) 0.384 AVR_Core_cm3_Inst/GPRF_Inst/register_file_6_6
|
204 |
|
|
SLICE_X30Y40.CLK Tdh (-Th) 0.126 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_6_7
|
205 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/Mshreg_register_file_cml_2_6_6/SRL16E
|
206 |
|
|
------------------------------------------------- ---------------------------
|
207 |
|
|
Total 0.722ns (0.338ns logic, 0.384ns route)
|
208 |
|
|
(46.8% logic, 53.2% route)
|
209 |
|
|
|
210 |
|
|
--------------------------------------------------------------------------------
|
211 |
|
|
Slack (hold path): 0.657ns (requirement - (clock path skew + uncertainty - data path))
|
212 |
|
|
Source: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/irqackad_int_1 (FF)
|
213 |
|
|
Destination: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/Mshreg_irqackad_int_cml_2_1/SRL16E (FF)
|
214 |
|
|
Requirement: 0.000ns
|
215 |
|
|
Data Path Delay: 0.670ns (Levels of Logic = 1)
|
216 |
|
|
Clock Path Skew: 0.013ns (0.090 - 0.077)
|
217 |
|
|
Source Clock: cp2_BUFGP rising at 10.000ns
|
218 |
|
|
Destination Clock: cp2_BUFGP rising at 10.000ns
|
219 |
|
|
Clock Uncertainty: 0.000ns
|
220 |
|
|
|
221 |
|
|
Minimum Data Path: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/irqackad_int_1 to AVR_Core_cm3_Inst/pm_fetch_dec_Inst/Mshreg_irqackad_int_cml_2_1/SRL16E
|
222 |
|
|
Location Delay type Delay(ns) Physical Resource
|
223 |
|
|
Logical Resource(s)
|
224 |
|
|
------------------------------------------------- -------------------
|
225 |
|
|
SLICE_X29Y6.XQ Tcko 0.473 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/irqackad_int<1>
|
226 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/irqackad_int_1
|
227 |
|
|
SLICE_X28Y7.BX net (fanout=1) 0.343 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/irqackad_int<1>
|
228 |
|
|
SLICE_X28Y7.CLK Tdh (-Th) 0.146 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/irqackad_int_cml_2<1>
|
229 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/Mshreg_irqackad_int_cml_2_1/SRL16E
|
230 |
|
|
------------------------------------------------- ---------------------------
|
231 |
|
|
Total 0.670ns (0.327ns logic, 0.343ns route)
|
232 |
|
|
(48.8% logic, 51.2% route)
|
233 |
|
|
|
234 |
|
|
--------------------------------------------------------------------------------
|
235 |
|
|
Slack (hold path): 0.659ns (requirement - (clock path skew + uncertainty - data path))
|
236 |
|
|
Source: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/program_counter_tmp_7 (FF)
|
237 |
|
|
Destination: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/Mshreg_program_counter_tmp_cml_2_7/SRL16E (FF)
|
238 |
|
|
Requirement: 0.000ns
|
239 |
|
|
Data Path Delay: 0.670ns (Levels of Logic = 1)
|
240 |
|
|
Clock Path Skew: 0.011ns (0.078 - 0.067)
|
241 |
|
|
Source Clock: cp2_BUFGP rising at 10.000ns
|
242 |
|
|
Destination Clock: cp2_BUFGP rising at 10.000ns
|
243 |
|
|
Clock Uncertainty: 0.000ns
|
244 |
|
|
|
245 |
|
|
Minimum Data Path: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/program_counter_tmp_7 to AVR_Core_cm3_Inst/pm_fetch_dec_Inst/Mshreg_program_counter_tmp_cml_2_7/SRL16E
|
246 |
|
|
Location Delay type Delay(ns) Physical Resource
|
247 |
|
|
Logical Resource(s)
|
248 |
|
|
------------------------------------------------- -------------------
|
249 |
|
|
SLICE_X5Y8.XQ Tcko 0.473 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/program_counter_tmp<7>
|
250 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/program_counter_tmp_7
|
251 |
|
|
SLICE_X4Y9.BX net (fanout=1) 0.343 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/program_counter_tmp<7>
|
252 |
|
|
SLICE_X4Y9.CLK Tdh (-Th) 0.146 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/program_counter_tmp_cml_2<7>
|
253 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/Mshreg_program_counter_tmp_cml_2_7/SRL16E
|
254 |
|
|
------------------------------------------------- ---------------------------
|
255 |
|
|
Total 0.670ns (0.327ns logic, 0.343ns route)
|
256 |
|
|
(48.8% logic, 51.2% route)
|
257 |
|
|
|
258 |
|
|
--------------------------------------------------------------------------------
|
259 |
|
|
|
260 |
|
|
Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 10 ns HIGH 50%;
|
261 |
|
|
--------------------------------------------------------------------------------
|
262 |
|
|
Slack: 6.796ns (period - (min low pulse limit / (low pulse / period)))
|
263 |
|
|
Period: 10.000ns
|
264 |
|
|
Low pulse: 5.000ns
|
265 |
|
|
Low pulse limit: 1.602ns (Trpw)
|
266 |
|
|
Physical resource: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/sts_st/SR
|
267 |
|
|
Logical resource: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/sts_st/SR
|
268 |
|
|
Location pin: SLICE_X8Y42.SR
|
269 |
|
|
Clock network: ireset_IBUF
|
270 |
|
|
--------------------------------------------------------------------------------
|
271 |
|
|
Slack: 6.796ns (period - (min high pulse limit / (high pulse / period)))
|
272 |
|
|
Period: 10.000ns
|
273 |
|
|
High pulse: 5.000ns
|
274 |
|
|
High pulse limit: 1.602ns (Trpw)
|
275 |
|
|
Physical resource: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/sts_st/SR
|
276 |
|
|
Logical resource: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/sts_st/SR
|
277 |
|
|
Location pin: SLICE_X8Y42.SR
|
278 |
|
|
Clock network: ireset_IBUF
|
279 |
|
|
--------------------------------------------------------------------------------
|
280 |
|
|
Slack: 6.796ns (period - (min low pulse limit / (low pulse / period)))
|
281 |
|
|
Period: 10.000ns
|
282 |
|
|
Low pulse: 5.000ns
|
283 |
|
|
Low pulse limit: 1.602ns (Trpw)
|
284 |
|
|
Physical resource: AVR_Core_cm3_Inst/GPRF_Inst/r27h<6>/SR
|
285 |
|
|
Logical resource: AVR_Core_cm3_Inst/GPRF_Inst/r27h_6/SR
|
286 |
|
|
Location pin: SLICE_X18Y47.SR
|
287 |
|
|
Clock network: ireset_IBUF
|
288 |
|
|
--------------------------------------------------------------------------------
|
289 |
|
|
|
290 |
|
|
|
291 |
|
|
1 constraint not met.
|
292 |
|
|
|
293 |
|
|
|
294 |
|
|
Data Sheet report:
|
295 |
|
|
-----------------
|
296 |
|
|
All values displayed in nanoseconds (ns)
|
297 |
|
|
|
298 |
|
|
Clock to Setup on destination clock cp2
|
299 |
|
|
---------------+---------+---------+---------+---------+
|
300 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
301 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
302 |
|
|
---------------+---------+---------+---------+---------+
|
303 |
|
|
cp2 | 12.532| | | |
|
304 |
|
|
---------------+---------+---------+---------+---------+
|
305 |
|
|
|
306 |
|
|
|
307 |
|
|
Timing summary:
|
308 |
|
|
---------------
|
309 |
|
|
|
310 |
|
|
Timing errors: 877 Score: 991383 (Setup/Max: 991383, Hold: 0)
|
311 |
|
|
|
312 |
|
|
Constraints cover 203315 paths, 0 nets, and 9716 connections
|
313 |
|
|
|
314 |
|
|
Design statistics:
|
315 |
|
|
Minimum period: 12.532ns{1} (Maximum frequency: 79.796MHz)
|
316 |
|
|
|
317 |
|
|
|
318 |
|
|
------------------------------------Footnotes-----------------------------------
|
319 |
|
|
1) The minimum period statistic assumes all single cycle delays.
|
320 |
|
|
|
321 |
|
|
Analysis completed Mon Oct 04 22:47:51 2010
|
322 |
|
|
--------------------------------------------------------------------------------
|
323 |
|
|
|
324 |
|
|
Trace Settings:
|
325 |
|
|
-------------------------
|
326 |
|
|
Trace Settings
|
327 |
|
|
|
328 |
|
|
Peak Memory Usage: 160 MB
|
329 |
|
|
|
330 |
|
|
|
331 |
|
|
|