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tobil |
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Release 11.1 Trace (nt)
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Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
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C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
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C:/EDAptability/coremultiplier/reference/avr/ise/ise_v5/ise_v5/ise_v5.ise
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-intstyle ise -v 3 -s 3 -fastpaths -xml avr_core.twx avr_core.ncd -o
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avr_core.twr avr_core.pcf -ucf avr_core.ucf
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Design file: avr_core.ncd
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Physical constraint file: avr_core.pcf
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Device,package,speed: xc5vlx50,ff324,-3 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
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Report level: verbose report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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================================================================================
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Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 8 ns HIGH 50%;
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106838544 paths analyzed, 1535 endpoints analyzed, 170 failing endpoints
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170 timing errors detected. (170 setup errors, 0 hold errors, 0 component switching limit errors)
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Minimum period is 9.385ns.
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--------------------------------------------------------------------------------
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Slack (setup path): -1.385ns (requirement - (data path - clock path skew + uncertainty))
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Source: pm_fetch_dec_Inst/ld_st (FF)
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Destination: pm_fetch_dec_Inst/pc_for_interrupt_6 (FF)
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Requirement: 8.000ns
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Data Path Delay: 9.206ns (Levels of Logic = 13)
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Clock Path Skew: -0.144ns (1.017 - 1.161)
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Source Clock: cp2_BUFGP rising at 0.000ns
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Destination Clock: cp2_BUFGP rising at 8.000ns
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Clock Uncertainty: 0.035ns
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Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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Total System Jitter (TSJ): 0.070ns
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Total Input Jitter (TIJ): 0.000ns
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Discrete Jitter (DJ): 0.000ns
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Phase Error (PE): 0.000ns
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Maximum Data Path: pm_fetch_dec_Inst/ld_st to pm_fetch_dec_Inst/pc_for_interrupt_6
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X17Y39.AQ Tcko 0.326 pm_fetch_dec_Inst/lds_st
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pm_fetch_dec_Inst/ld_st
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SLICE_X17Y45.D1 net (fanout=14) 0.827 pm_fetch_dec_Inst/ld_st
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SLICE_X17Y45.D Tilo 0.080 pm_fetch_dec_Inst/sts_st
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pm_fetch_dec_Inst/nop_insert_st46
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SLICE_X16Y41.A3 net (fanout=16) 0.724 pm_fetch_dec_Inst/nop_insert_st46
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| 61 |
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SLICE_X16Y41.A Tilo 0.080 pm_fetch_dec_Inst/instruction_reg<11>
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pm_fetch_dec_Inst/idc_elpm_cmp_eq000011
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SLICE_X16Y41.D1 net (fanout=28) 0.606 pm_fetch_dec_Inst/N65
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SLICE_X16Y41.D Tilo 0.080 pm_fetch_dec_Inst/instruction_reg<11>
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pm_fetch_dec_Inst/reg_rd_adr<2>60_SW2
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| 66 |
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SLICE_X14Y37.C4 net (fanout=1) 0.528 N465
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| 67 |
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SLICE_X14Y37.C Tilo 0.080 GPRF_Inst/register_file_9_not0001
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pm_fetch_dec_Inst/reg_rd_adr<2>60
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SLICE_X14Y35.D6 net (fanout=100) 0.511 reg_rd_adr<2>
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SLICE_X14Y35.CMUX Topdc 0.313 GPRF_Inst/sg_tmp_rd_data_31<0>37
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GPRF_Inst/sg_tmp_rd_data_31<0>37_F
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GPRF_Inst/sg_tmp_rd_data_31<0>37
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| 73 |
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SLICE_X12Y35.B1 net (fanout=3) 0.682 GPRF_Inst/sg_tmp_rd_data_31<0>37
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| 74 |
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SLICE_X12Y35.B Tilo 0.080 pm_fetch_dec_Inst/gp_reg_tmp<1>
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| 75 |
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GPRF_Inst/sg_tmp_rd_data_31<0>295
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| 76 |
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SLICE_X11Y38.B4 net (fanout=26) 0.744 reg_rd_out<0>
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| 77 |
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SLICE_X11Y38.B Tilo 0.080 N210
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| 78 |
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ALU_Inst/neg_op_carry_2_and00001
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SLICE_X11Y38.A5 net (fanout=4) 0.172 ALU_Inst/neg_op_carry<2>
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SLICE_X11Y38.A Tilo 0.080 N210
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ALU_Inst/alu_data_out_int_6_or000047
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SLICE_X11Y38.D3 net (fanout=2) 0.466 ALU_Inst/alu_data_out_int_6_or000047
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SLICE_X11Y38.D Tilo 0.080 N210
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ALU_Inst/alu_data_out_int_6_or0000174_SW1
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SLICE_X10Y42.C5 net (fanout=2) 0.432 N210
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| 86 |
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SLICE_X10Y42.C Tilo 0.080 IORegs_Inst/sreg<4>
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ALU_Inst/alu_data_out_int_6_or0000174
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SLICE_X11Y43.A2 net (fanout=2) 0.552 alu_data_out<6>
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SLICE_X11Y43.A Tilo 0.080 pm_fetch_dec_Inst/irqack_int
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pm_fetch_dec_Inst/skip_inst_start_SW0
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SLICE_X10Y67.A6 net (fanout=6) 1.012 N198
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| 92 |
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SLICE_X10Y67.A Tilo 0.080 pm_fetch_dec_Inst/pc_for_interrupt<15>
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pm_fetch_dec_Inst/pc_for_interrupt_not00011
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SLICE_X11Y68.C6 net (fanout=16) 0.401 pm_fetch_dec_Inst/pc_for_interrupt_not0001
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SLICE_X11Y68.CLK Tas 0.030 pm_fetch_dec_Inst/pc_for_interrupt<7>
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pm_fetch_dec_Inst/pc_for_interrupt_6_rstpot
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pm_fetch_dec_Inst/pc_for_interrupt_6
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------------------------------------------------- ---------------------------
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Total 9.206ns (1.549ns logic, 7.657ns route)
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(16.8% logic, 83.2% route)
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--------------------------------------------------------------------------------
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Slack (setup path): -1.383ns (requirement - (data path - clock path skew + uncertainty))
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Source: pm_fetch_dec_Inst/ld_st (FF)
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Destination: pm_fetch_dec_Inst/pc_for_interrupt_6 (FF)
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Requirement: 8.000ns
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Data Path Delay: 9.204ns (Levels of Logic = 13)
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| 108 |
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Clock Path Skew: -0.144ns (1.017 - 1.161)
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| 109 |
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Source Clock: cp2_BUFGP rising at 0.000ns
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Destination Clock: cp2_BUFGP rising at 8.000ns
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Clock Uncertainty: 0.035ns
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| 112 |
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| 113 |
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Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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Total System Jitter (TSJ): 0.070ns
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| 115 |
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Total Input Jitter (TIJ): 0.000ns
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| 116 |
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Discrete Jitter (DJ): 0.000ns
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| 117 |
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Phase Error (PE): 0.000ns
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| 118 |
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| 119 |
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Maximum Data Path: pm_fetch_dec_Inst/ld_st to pm_fetch_dec_Inst/pc_for_interrupt_6
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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| 122 |
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------------------------------------------------- -------------------
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| 123 |
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SLICE_X17Y39.AQ Tcko 0.326 pm_fetch_dec_Inst/lds_st
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| 124 |
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pm_fetch_dec_Inst/ld_st
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| 125 |
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SLICE_X17Y45.D1 net (fanout=14) 0.827 pm_fetch_dec_Inst/ld_st
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| 126 |
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SLICE_X17Y45.D Tilo 0.080 pm_fetch_dec_Inst/sts_st
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| 127 |
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pm_fetch_dec_Inst/nop_insert_st46
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| 128 |
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SLICE_X16Y41.A3 net (fanout=16) 0.724 pm_fetch_dec_Inst/nop_insert_st46
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| 129 |
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SLICE_X16Y41.A Tilo 0.080 pm_fetch_dec_Inst/instruction_reg<11>
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| 130 |
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pm_fetch_dec_Inst/idc_elpm_cmp_eq000011
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| 131 |
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SLICE_X16Y41.D1 net (fanout=28) 0.606 pm_fetch_dec_Inst/N65
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| 132 |
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SLICE_X16Y41.D Tilo 0.080 pm_fetch_dec_Inst/instruction_reg<11>
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| 133 |
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pm_fetch_dec_Inst/reg_rd_adr<2>60_SW2
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| 134 |
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SLICE_X14Y37.C4 net (fanout=1) 0.528 N465
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| 135 |
|
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SLICE_X14Y37.C Tilo 0.080 GPRF_Inst/register_file_9_not0001
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| 136 |
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pm_fetch_dec_Inst/reg_rd_adr<2>60
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| 137 |
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SLICE_X14Y35.C6 net (fanout=100) 0.512 reg_rd_adr<2>
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| 138 |
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SLICE_X14Y35.CMUX Tilo 0.310 GPRF_Inst/sg_tmp_rd_data_31<0>37
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| 139 |
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GPRF_Inst/sg_tmp_rd_data_31<0>37_G
|
| 140 |
|
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GPRF_Inst/sg_tmp_rd_data_31<0>37
|
| 141 |
|
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SLICE_X12Y35.B1 net (fanout=3) 0.682 GPRF_Inst/sg_tmp_rd_data_31<0>37
|
| 142 |
|
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SLICE_X12Y35.B Tilo 0.080 pm_fetch_dec_Inst/gp_reg_tmp<1>
|
| 143 |
|
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GPRF_Inst/sg_tmp_rd_data_31<0>295
|
| 144 |
|
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SLICE_X11Y38.B4 net (fanout=26) 0.744 reg_rd_out<0>
|
| 145 |
|
|
SLICE_X11Y38.B Tilo 0.080 N210
|
| 146 |
|
|
ALU_Inst/neg_op_carry_2_and00001
|
| 147 |
|
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SLICE_X11Y38.A5 net (fanout=4) 0.172 ALU_Inst/neg_op_carry<2>
|
| 148 |
|
|
SLICE_X11Y38.A Tilo 0.080 N210
|
| 149 |
|
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ALU_Inst/alu_data_out_int_6_or000047
|
| 150 |
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SLICE_X11Y38.D3 net (fanout=2) 0.466 ALU_Inst/alu_data_out_int_6_or000047
|
| 151 |
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SLICE_X11Y38.D Tilo 0.080 N210
|
| 152 |
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ALU_Inst/alu_data_out_int_6_or0000174_SW1
|
| 153 |
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SLICE_X10Y42.C5 net (fanout=2) 0.432 N210
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| 154 |
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SLICE_X10Y42.C Tilo 0.080 IORegs_Inst/sreg<4>
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| 155 |
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ALU_Inst/alu_data_out_int_6_or0000174
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| 156 |
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SLICE_X11Y43.A2 net (fanout=2) 0.552 alu_data_out<6>
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| 157 |
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SLICE_X11Y43.A Tilo 0.080 pm_fetch_dec_Inst/irqack_int
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| 158 |
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pm_fetch_dec_Inst/skip_inst_start_SW0
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| 159 |
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SLICE_X10Y67.A6 net (fanout=6) 1.012 N198
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| 160 |
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SLICE_X10Y67.A Tilo 0.080 pm_fetch_dec_Inst/pc_for_interrupt<15>
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| 161 |
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pm_fetch_dec_Inst/pc_for_interrupt_not00011
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| 162 |
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SLICE_X11Y68.C6 net (fanout=16) 0.401 pm_fetch_dec_Inst/pc_for_interrupt_not0001
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| 163 |
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SLICE_X11Y68.CLK Tas 0.030 pm_fetch_dec_Inst/pc_for_interrupt<7>
|
| 164 |
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pm_fetch_dec_Inst/pc_for_interrupt_6_rstpot
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| 165 |
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pm_fetch_dec_Inst/pc_for_interrupt_6
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| 166 |
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------------------------------------------------- ---------------------------
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| 167 |
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Total 9.204ns (1.546ns logic, 7.658ns route)
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| 168 |
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(16.8% logic, 83.2% route)
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| 169 |
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| 170 |
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--------------------------------------------------------------------------------
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Slack (setup path): -1.366ns (requirement - (data path - clock path skew + uncertainty))
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| 172 |
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Source: pm_fetch_dec_Inst/ld_st (FF)
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| 173 |
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Destination: pm_fetch_dec_Inst/pc_for_interrupt_6 (FF)
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| 174 |
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Requirement: 8.000ns
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| 175 |
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Data Path Delay: 9.187ns (Levels of Logic = 13)
|
| 176 |
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Clock Path Skew: -0.144ns (1.017 - 1.161)
|
| 177 |
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Source Clock: cp2_BUFGP rising at 0.000ns
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| 178 |
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Destination Clock: cp2_BUFGP rising at 8.000ns
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| 179 |
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Clock Uncertainty: 0.035ns
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| 180 |
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|
| 181 |
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Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
| 182 |
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Total System Jitter (TSJ): 0.070ns
|
| 183 |
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Total Input Jitter (TIJ): 0.000ns
|
| 184 |
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Discrete Jitter (DJ): 0.000ns
|
| 185 |
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Phase Error (PE): 0.000ns
|
| 186 |
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|
| 187 |
|
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Maximum Data Path: pm_fetch_dec_Inst/ld_st to pm_fetch_dec_Inst/pc_for_interrupt_6
|
| 188 |
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Location Delay type Delay(ns) Physical Resource
|
| 189 |
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Logical Resource(s)
|
| 190 |
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------------------------------------------------- -------------------
|
| 191 |
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SLICE_X17Y39.AQ Tcko 0.326 pm_fetch_dec_Inst/lds_st
|
| 192 |
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pm_fetch_dec_Inst/ld_st
|
| 193 |
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SLICE_X17Y45.D1 net (fanout=14) 0.827 pm_fetch_dec_Inst/ld_st
|
| 194 |
|
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SLICE_X17Y45.D Tilo 0.080 pm_fetch_dec_Inst/sts_st
|
| 195 |
|
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pm_fetch_dec_Inst/nop_insert_st46
|
| 196 |
|
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SLICE_X16Y41.A3 net (fanout=16) 0.724 pm_fetch_dec_Inst/nop_insert_st46
|
| 197 |
|
|
SLICE_X16Y41.A Tilo 0.080 pm_fetch_dec_Inst/instruction_reg<11>
|
| 198 |
|
|
pm_fetch_dec_Inst/idc_elpm_cmp_eq000011
|
| 199 |
|
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SLICE_X16Y41.D1 net (fanout=28) 0.606 pm_fetch_dec_Inst/N65
|
| 200 |
|
|
SLICE_X16Y41.D Tilo 0.080 pm_fetch_dec_Inst/instruction_reg<11>
|
| 201 |
|
|
pm_fetch_dec_Inst/reg_rd_adr<2>60_SW2
|
| 202 |
|
|
SLICE_X14Y37.C4 net (fanout=1) 0.528 N465
|
| 203 |
|
|
SLICE_X14Y37.C Tilo 0.080 GPRF_Inst/register_file_9_not0001
|
| 204 |
|
|
pm_fetch_dec_Inst/reg_rd_adr<2>60
|
| 205 |
|
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SLICE_X14Y35.D6 net (fanout=100) 0.511 reg_rd_adr<2>
|
| 206 |
|
|
SLICE_X14Y35.CMUX Topdc 0.313 GPRF_Inst/sg_tmp_rd_data_31<0>37
|
| 207 |
|
|
GPRF_Inst/sg_tmp_rd_data_31<0>37_F
|
| 208 |
|
|
GPRF_Inst/sg_tmp_rd_data_31<0>37
|
| 209 |
|
|
SLICE_X12Y35.B1 net (fanout=3) 0.682 GPRF_Inst/sg_tmp_rd_data_31<0>37
|
| 210 |
|
|
SLICE_X12Y35.B Tilo 0.080 pm_fetch_dec_Inst/gp_reg_tmp<1>
|
| 211 |
|
|
GPRF_Inst/sg_tmp_rd_data_31<0>295
|
| 212 |
|
|
SLICE_X11Y38.B4 net (fanout=26) 0.744 reg_rd_out<0>
|
| 213 |
|
|
SLICE_X11Y38.B Tilo 0.080 N210
|
| 214 |
|
|
ALU_Inst/neg_op_carry_2_and00001
|
| 215 |
|
|
SLICE_X11Y38.A5 net (fanout=4) 0.172 ALU_Inst/neg_op_carry<2>
|
| 216 |
|
|
SLICE_X11Y38.A Tilo 0.080 N210
|
| 217 |
|
|
ALU_Inst/alu_data_out_int_6_or000047
|
| 218 |
|
|
SLICE_X10Y38.D3 net (fanout=2) 0.486 ALU_Inst/alu_data_out_int_6_or000047
|
| 219 |
|
|
SLICE_X10Y38.D Tilo 0.080 N209
|
| 220 |
|
|
ALU_Inst/alu_data_out_int_6_or0000174_SW0
|
| 221 |
|
|
SLICE_X10Y42.C6 net (fanout=2) 0.393 N209
|
| 222 |
|
|
SLICE_X10Y42.C Tilo 0.080 IORegs_Inst/sreg<4>
|
| 223 |
|
|
ALU_Inst/alu_data_out_int_6_or0000174
|
| 224 |
|
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SLICE_X11Y43.A2 net (fanout=2) 0.552 alu_data_out<6>
|
| 225 |
|
|
SLICE_X11Y43.A Tilo 0.080 pm_fetch_dec_Inst/irqack_int
|
| 226 |
|
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pm_fetch_dec_Inst/skip_inst_start_SW0
|
| 227 |
|
|
SLICE_X10Y67.A6 net (fanout=6) 1.012 N198
|
| 228 |
|
|
SLICE_X10Y67.A Tilo 0.080 pm_fetch_dec_Inst/pc_for_interrupt<15>
|
| 229 |
|
|
pm_fetch_dec_Inst/pc_for_interrupt_not00011
|
| 230 |
|
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SLICE_X11Y68.C6 net (fanout=16) 0.401 pm_fetch_dec_Inst/pc_for_interrupt_not0001
|
| 231 |
|
|
SLICE_X11Y68.CLK Tas 0.030 pm_fetch_dec_Inst/pc_for_interrupt<7>
|
| 232 |
|
|
pm_fetch_dec_Inst/pc_for_interrupt_6_rstpot
|
| 233 |
|
|
pm_fetch_dec_Inst/pc_for_interrupt_6
|
| 234 |
|
|
------------------------------------------------- ---------------------------
|
| 235 |
|
|
Total 9.187ns (1.549ns logic, 7.638ns route)
|
| 236 |
|
|
(16.9% logic, 83.1% route)
|
| 237 |
|
|
|
| 238 |
|
|
--------------------------------------------------------------------------------
|
| 239 |
|
|
|
| 240 |
|
|
Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 8 ns HIGH 50%;
|
| 241 |
|
|
--------------------------------------------------------------------------------
|
| 242 |
|
|
Slack (hold path): 0.353ns (requirement - (clock path skew + uncertainty - data path))
|
| 243 |
|
|
Source: pm_fetch_dec_Inst/pc_high_0 (FF)
|
| 244 |
|
|
Destination: pm_fetch_dec_Inst/program_counter_tmp_8 (FF)
|
| 245 |
|
|
Requirement: 0.000ns
|
| 246 |
|
|
Data Path Delay: 0.381ns (Levels of Logic = 0)
|
| 247 |
|
|
Clock Path Skew: 0.028ns (0.467 - 0.439)
|
| 248 |
|
|
Source Clock: cp2_BUFGP rising at 8.000ns
|
| 249 |
|
|
Destination Clock: cp2_BUFGP rising at 8.000ns
|
| 250 |
|
|
Clock Uncertainty: 0.000ns
|
| 251 |
|
|
|
| 252 |
|
|
Minimum Data Path: pm_fetch_dec_Inst/pc_high_0 to pm_fetch_dec_Inst/program_counter_tmp_8
|
| 253 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 254 |
|
|
Logical Resource(s)
|
| 255 |
|
|
------------------------------------------------- -------------------
|
| 256 |
|
|
SLICE_X13Y56.BQ Tcko 0.300 pm_fetch_dec_Inst/pc_high<2>
|
| 257 |
|
|
pm_fetch_dec_Inst/pc_high_0
|
| 258 |
|
|
SLICE_X15Y57.AX net (fanout=6) 0.245 pm_fetch_dec_Inst/pc_high<0>
|
| 259 |
|
|
SLICE_X15Y57.CLK Tckdi (-Th) 0.164 pm_fetch_dec_Inst/program_counter_tmp<11>
|
| 260 |
|
|
pm_fetch_dec_Inst/program_counter_tmp_8
|
| 261 |
|
|
------------------------------------------------- ---------------------------
|
| 262 |
|
|
Total 0.381ns (0.136ns logic, 0.245ns route)
|
| 263 |
|
|
(35.7% logic, 64.3% route)
|
| 264 |
|
|
|
| 265 |
|
|
--------------------------------------------------------------------------------
|
| 266 |
|
|
Slack (hold path): 0.371ns (requirement - (clock path skew + uncertainty - data path))
|
| 267 |
|
|
Source: pm_fetch_dec_Inst/ret_st3 (FF)
|
| 268 |
|
|
Destination: pm_fetch_dec_Inst/nret_st0 (FF)
|
| 269 |
|
|
Requirement: 0.000ns
|
| 270 |
|
|
Data Path Delay: 0.395ns (Levels of Logic = 1)
|
| 271 |
|
|
Clock Path Skew: 0.024ns (0.442 - 0.418)
|
| 272 |
|
|
Source Clock: cp2_BUFGP rising at 8.000ns
|
| 273 |
|
|
Destination Clock: cp2_BUFGP rising at 8.000ns
|
| 274 |
|
|
Clock Uncertainty: 0.000ns
|
| 275 |
|
|
|
| 276 |
|
|
Minimum Data Path: pm_fetch_dec_Inst/ret_st3 to pm_fetch_dec_Inst/nret_st0
|
| 277 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 278 |
|
|
Logical Resource(s)
|
| 279 |
|
|
------------------------------------------------- -------------------
|
| 280 |
|
|
SLICE_X12Y48.CQ Tcko 0.318 pm_fetch_dec_Inst/ret_st3
|
| 281 |
|
|
pm_fetch_dec_Inst/ret_st3
|
| 282 |
|
|
SLICE_X16Y48.D6 net (fanout=2) 0.227 pm_fetch_dec_Inst/ret_st3
|
| 283 |
|
|
SLICE_X16Y48.CLK Tah (-Th) 0.150 pm_fetch_dec_Inst/nret_st0
|
| 284 |
|
|
pm_fetch_dec_Inst/nret_st0_or00001
|
| 285 |
|
|
pm_fetch_dec_Inst/nret_st0
|
| 286 |
|
|
------------------------------------------------- ---------------------------
|
| 287 |
|
|
Total 0.395ns (0.168ns logic, 0.227ns route)
|
| 288 |
|
|
(42.5% logic, 57.5% route)
|
| 289 |
|
|
|
| 290 |
|
|
--------------------------------------------------------------------------------
|
| 291 |
|
|
Slack (hold path): 0.377ns (requirement - (clock path skew + uncertainty - data path))
|
| 292 |
|
|
Source: pm_fetch_dec_Inst/pc_high_5 (FF)
|
| 293 |
|
|
Destination: pm_fetch_dec_Inst/program_counter_high_fr_5 (FF)
|
| 294 |
|
|
Requirement: 0.000ns
|
| 295 |
|
|
Data Path Delay: 0.389ns (Levels of Logic = 0)
|
| 296 |
|
|
Clock Path Skew: 0.012ns (0.128 - 0.116)
|
| 297 |
|
|
Source Clock: cp2_BUFGP rising at 8.000ns
|
| 298 |
|
|
Destination Clock: cp2_BUFGP rising at 8.000ns
|
| 299 |
|
|
Clock Uncertainty: 0.000ns
|
| 300 |
|
|
|
| 301 |
|
|
Minimum Data Path: pm_fetch_dec_Inst/pc_high_5 to pm_fetch_dec_Inst/program_counter_high_fr_5
|
| 302 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 303 |
|
|
Logical Resource(s)
|
| 304 |
|
|
------------------------------------------------- -------------------
|
| 305 |
|
|
SLICE_X10Y56.CQ Tcko 0.318 pm_fetch_dec_Inst/pc_high<6>
|
| 306 |
|
|
pm_fetch_dec_Inst/pc_high_5
|
| 307 |
|
|
SLICE_X10Y58.BX net (fanout=6) 0.248 pm_fetch_dec_Inst/pc_high<5>
|
| 308 |
|
|
SLICE_X10Y58.CLK Tckdi (-Th) 0.177 pm_fetch_dec_Inst/program_counter_high_fr<7>
|
| 309 |
|
|
pm_fetch_dec_Inst/program_counter_high_fr_5
|
| 310 |
|
|
------------------------------------------------- ---------------------------
|
| 311 |
|
|
Total 0.389ns (0.141ns logic, 0.248ns route)
|
| 312 |
|
|
(36.2% logic, 63.8% route)
|
| 313 |
|
|
|
| 314 |
|
|
--------------------------------------------------------------------------------
|
| 315 |
|
|
|
| 316 |
|
|
Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 8 ns HIGH 50%;
|
| 317 |
|
|
--------------------------------------------------------------------------------
|
| 318 |
|
|
Slack: 6.450ns (period - (min high pulse limit / (high pulse / period)))
|
| 319 |
|
|
Period: 8.000ns
|
| 320 |
|
|
High pulse: 4.000ns
|
| 321 |
|
|
High pulse limit: 0.775ns (Tospwh)
|
| 322 |
|
|
Physical resource: pm_fetch_dec_Inst/irqackad_int_0_1/SR
|
| 323 |
|
|
Logical resource: pm_fetch_dec_Inst/irqackad_int_0_1/SR
|
| 324 |
|
|
Location pin: OLOGIC_X0Y121.SR
|
| 325 |
|
|
Clock network: BP_Inst/ireset_inv
|
| 326 |
|
|
--------------------------------------------------------------------------------
|
| 327 |
|
|
Slack: 6.450ns (period - (min high pulse limit / (high pulse / period)))
|
| 328 |
|
|
Period: 8.000ns
|
| 329 |
|
|
High pulse: 4.000ns
|
| 330 |
|
|
High pulse limit: 0.775ns (Tospwh)
|
| 331 |
|
|
Physical resource: pm_fetch_dec_Inst/irqackad_int_1_1/SR
|
| 332 |
|
|
Logical resource: pm_fetch_dec_Inst/irqackad_int_1_1/SR
|
| 333 |
|
|
Location pin: OLOGIC_X0Y130.SR
|
| 334 |
|
|
Clock network: BP_Inst/ireset_inv
|
| 335 |
|
|
--------------------------------------------------------------------------------
|
| 336 |
|
|
Slack: 6.450ns (period - (min high pulse limit / (high pulse / period)))
|
| 337 |
|
|
Period: 8.000ns
|
| 338 |
|
|
High pulse: 4.000ns
|
| 339 |
|
|
High pulse limit: 0.775ns (Tospwh)
|
| 340 |
|
|
Physical resource: pm_fetch_dec_Inst/irqackad_int_2_1/SR
|
| 341 |
|
|
Logical resource: pm_fetch_dec_Inst/irqackad_int_2_1/SR
|
| 342 |
|
|
Location pin: OLOGIC_X0Y128.SR
|
| 343 |
|
|
Clock network: BP_Inst/ireset_inv
|
| 344 |
|
|
--------------------------------------------------------------------------------
|
| 345 |
|
|
|
| 346 |
|
|
|
| 347 |
|
|
1 constraint not met.
|
| 348 |
|
|
|
| 349 |
|
|
|
| 350 |
|
|
Data Sheet report:
|
| 351 |
|
|
-----------------
|
| 352 |
|
|
All values displayed in nanoseconds (ns)
|
| 353 |
|
|
|
| 354 |
|
|
Clock to Setup on destination clock cp2
|
| 355 |
|
|
---------------+---------+---------+---------+---------+
|
| 356 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
| 357 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
| 358 |
|
|
---------------+---------+---------+---------+---------+
|
| 359 |
|
|
cp2 | 9.385| | | |
|
| 360 |
|
|
---------------+---------+---------+---------+---------+
|
| 361 |
|
|
|
| 362 |
|
|
|
| 363 |
|
|
Timing summary:
|
| 364 |
|
|
---------------
|
| 365 |
|
|
|
| 366 |
|
|
Timing errors: 170 Score: 54513 (Setup/Max: 54513, Hold: 0)
|
| 367 |
|
|
|
| 368 |
|
|
Constraints cover 106838544 paths, 0 nets, and 6316 connections
|
| 369 |
|
|
|
| 370 |
|
|
Design statistics:
|
| 371 |
|
|
Minimum period: 9.385ns{1} (Maximum frequency: 106.553MHz)
|
| 372 |
|
|
|
| 373 |
|
|
|
| 374 |
|
|
------------------------------------Footnotes-----------------------------------
|
| 375 |
|
|
1) The minimum period statistic assumes all single cycle delays.
|
| 376 |
|
|
|
| 377 |
|
|
Analysis completed Sun Oct 03 11:56:26 2010
|
| 378 |
|
|
--------------------------------------------------------------------------------
|
| 379 |
|
|
|
| 380 |
|
|
Trace Settings:
|
| 381 |
|
|
-------------------------
|
| 382 |
|
|
Trace Settings
|
| 383 |
|
|
|
| 384 |
|
|
Peak Memory Usage: 257 MB
|
| 385 |
|
|
|
| 386 |
|
|
|
| 387 |
|
|
|
