1 |
2 |
tobil |
--------------------------------------------------------------------------------
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2 |
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Release 11.1 Trace (nt)
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3 |
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Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
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4 |
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5 |
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C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
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6 |
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C:/EDAptability/coremultiplier/reference/avr/ise/ise_v5_cm3_one_syneda/ise_v5_cm3_one_syneda/ise_v5_cm3_one_syneda.ise
|
7 |
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-intstyle ise -v 3 -s 3 -fastpaths -xml avr_core_cm3_top.twx
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8 |
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avr_core_cm3_top.ncd -o avr_core_cm3_top.twr avr_core_cm3_top.pcf -ucf
|
9 |
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avr_core_cm3_top.ucf
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10 |
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11 |
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Design file: avr_core_cm3_top.ncd
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12 |
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Physical constraint file: avr_core_cm3_top.pcf
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13 |
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Device,package,speed: xc5vlx50,ff324,-3 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
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14 |
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Report level: verbose report
|
15 |
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16 |
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Environment Variable Effect
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17 |
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-------------------- ------
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18 |
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NONE No environment variables were set
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19 |
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--------------------------------------------------------------------------------
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20 |
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21 |
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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22 |
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option. All paths that are not constrained will be reported in the
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23 |
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unconstrained paths section(s) of the report.
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24 |
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
|
25 |
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a 50 Ohm transmission line loading model. For the details of this model,
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26 |
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and for more information on accounting for different loading conditions,
|
27 |
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please see the device datasheet.
|
28 |
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29 |
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================================================================================
|
30 |
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Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 4.5 ns HIGH 50%;
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31 |
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32 |
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184139 paths analyzed, 3843 endpoints analyzed, 33 failing endpoints
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33 |
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33 timing errors detected. (33 setup errors, 0 hold errors, 0 component switching limit errors)
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34 |
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Minimum period is 4.819ns.
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35 |
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--------------------------------------------------------------------------------
|
36 |
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Slack (setup path): -0.319ns (requirement - (data path - clock path skew + uncertainty))
|
37 |
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Source: AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1_16 (FF)
|
38 |
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Destination: AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2 (FF)
|
39 |
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Requirement: 4.500ns
|
40 |
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Data Path Delay: 4.660ns (Levels of Logic = 11)
|
41 |
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Clock Path Skew: -0.124ns (1.023 - 1.147)
|
42 |
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Source Clock: cp2_BUFGP rising at 0.000ns
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43 |
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Destination Clock: cp2_BUFGP rising at 4.500ns
|
44 |
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Clock Uncertainty: 0.035ns
|
45 |
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|
46 |
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Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
47 |
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Total System Jitter (TSJ): 0.070ns
|
48 |
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Total Input Jitter (TIJ): 0.000ns
|
49 |
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Discrete Jitter (DJ): 0.000ns
|
50 |
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Phase Error (PE): 0.000ns
|
51 |
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|
52 |
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Maximum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1_16 to AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
|
53 |
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Location Delay type Delay(ns) Physical Resource
|
54 |
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Logical Resource(s)
|
55 |
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------------------------------------------------- -------------------
|
56 |
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|
SLICE_X16Y32.CQ Tcko 0.346 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
|
57 |
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AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1_16
|
58 |
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SLICE_X16Y32.D4 net (fanout=8) 0.429 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
|
59 |
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SLICE_X16Y32.D Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
|
60 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>22
|
61 |
|
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SLICE_X16Y32.B5 net (fanout=1) 0.285 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>22
|
62 |
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SLICE_X16Y32.B Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
|
63 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>71
|
64 |
|
|
SLICE_X16Y32.A5 net (fanout=1) 0.178 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>71
|
65 |
|
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SLICE_X16Y32.A Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
|
66 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>142
|
67 |
|
|
SLICE_X16Y36.A6 net (fanout=1) 0.372 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>142
|
68 |
|
|
SLICE_X16Y36.A Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<24>
|
69 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>226
|
70 |
|
|
SLICE_X16Y36.B6 net (fanout=1) 0.121 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>226
|
71 |
|
|
SLICE_X16Y36.B Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<24>
|
72 |
|
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AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>310
|
73 |
|
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SLICE_X23Y41.A6 net (fanout=1) 0.505 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>310
|
74 |
|
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SLICE_X23Y41.A Tilo 0.080 AVR_Core_cm3_Inst/BP_Inst/reg_rd_out_cml_2<2>
|
75 |
|
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AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>396
|
76 |
|
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SLICE_X23Y41.B6 net (fanout=1) 0.105 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>396
|
77 |
|
|
SLICE_X23Y41.B Tilo 0.080 AVR_Core_cm3_Inst/BP_Inst/reg_rd_out_cml_2<2>
|
78 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>480
|
79 |
|
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SLICE_X22Y41.A3 net (fanout=19) 0.491 AVR_Core_cm3_Inst/reg_rd_out<1>
|
80 |
|
|
SLICE_X22Y41.A Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry_cml_2<6>
|
81 |
|
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AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry_3_and00001
|
82 |
|
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SLICE_X22Y41.D6 net (fanout=6) 0.268 AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry<3>
|
83 |
|
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SLICE_X22Y41.D Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry_cml_2<6>
|
84 |
|
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AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000043
|
85 |
|
|
SLICE_X21Y42.D1 net (fanout=1) 0.624 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000043
|
86 |
|
|
SLICE_X21Y42.D Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
|
87 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000062
|
88 |
|
|
SLICE_X21Y42.C6 net (fanout=1) 0.106 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000062
|
89 |
|
|
SLICE_X21Y42.CLK Tas 0.030 AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
|
90 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2_rstpot
|
91 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
|
92 |
|
|
------------------------------------------------- ---------------------------
|
93 |
|
|
Total 4.660ns (1.176ns logic, 3.484ns route)
|
94 |
|
|
(25.2% logic, 74.8% route)
|
95 |
|
|
|
96 |
|
|
--------------------------------------------------------------------------------
|
97 |
|
|
Slack (setup path): -0.286ns (requirement - (data path - clock path skew + uncertainty))
|
98 |
|
|
Source: AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1_18 (FF)
|
99 |
|
|
Destination: AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_cml_2_5 (FF)
|
100 |
|
|
Requirement: 4.500ns
|
101 |
|
|
Data Path Delay: 4.600ns (Levels of Logic = 9)
|
102 |
|
|
Clock Path Skew: -0.151ns (1.022 - 1.173)
|
103 |
|
|
Source Clock: cp2_BUFGP rising at 0.000ns
|
104 |
|
|
Destination Clock: cp2_BUFGP rising at 4.500ns
|
105 |
|
|
Clock Uncertainty: 0.035ns
|
106 |
|
|
|
107 |
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
108 |
|
|
Total System Jitter (TSJ): 0.070ns
|
109 |
|
|
Total Input Jitter (TIJ): 0.000ns
|
110 |
|
|
Discrete Jitter (DJ): 0.000ns
|
111 |
|
|
Phase Error (PE): 0.000ns
|
112 |
|
|
|
113 |
|
|
Maximum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1_18 to AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_cml_2_5
|
114 |
|
|
Location Delay type Delay(ns) Physical Resource
|
115 |
|
|
Logical Resource(s)
|
116 |
|
|
------------------------------------------------- -------------------
|
117 |
|
|
SLICE_X15Y37.AQ Tcko 0.326 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<26>
|
118 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1_18
|
119 |
|
|
SLICE_X13Y35.A1 net (fanout=8) 0.750 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<18>
|
120 |
|
|
SLICE_X13Y35.A Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_17_7
|
121 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>71
|
122 |
|
|
SLICE_X13Y35.C6 net (fanout=1) 0.226 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>71
|
123 |
|
|
SLICE_X13Y35.C Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_17_7
|
124 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>142
|
125 |
|
|
SLICE_X13Y35.D5 net (fanout=1) 0.164 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>142
|
126 |
|
|
SLICE_X13Y35.D Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_17_7
|
127 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>226
|
128 |
|
|
SLICE_X12Y37.A6 net (fanout=1) 0.224 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>226
|
129 |
|
|
SLICE_X12Y37.A Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_1<7>
|
130 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>310
|
131 |
|
|
SLICE_X12Y37.B6 net (fanout=1) 0.121 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>310
|
132 |
|
|
SLICE_X12Y37.B Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_1<7>
|
133 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>396
|
134 |
|
|
SLICE_X22Y42.C6 net (fanout=1) 0.558 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>396
|
135 |
|
|
SLICE_X22Y42.C Tilo 0.080 AVR_Core_cm3_Inst/BP_Inst/reg_rd_out_cml_2<4>
|
136 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>480
|
137 |
|
|
SLICE_X22Y42.D5 net (fanout=19) 0.233 AVR_Core_cm3_Inst/reg_rd_out<4>
|
138 |
|
|
SLICE_X22Y42.D Tilo 0.080 AVR_Core_cm3_Inst/BP_Inst/reg_rd_out_cml_2<4>
|
139 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_5_or000086
|
140 |
|
|
SLICE_X22Y43.B2 net (fanout=1) 0.927 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_5_or000086
|
141 |
|
|
SLICE_X22Y43.B Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_3_or000047
|
142 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_5_or0000113
|
143 |
|
|
SLICE_X22Y45.B4 net (fanout=1) 0.402 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_5_or0000113
|
144 |
|
|
SLICE_X22Y45.CLK Tas 0.029 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_cml_2<5>
|
145 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_5_or00001891
|
146 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_cml_2_5
|
147 |
|
|
------------------------------------------------- ---------------------------
|
148 |
|
|
Total 4.600ns (0.995ns logic, 3.605ns route)
|
149 |
|
|
(21.6% logic, 78.4% route)
|
150 |
|
|
|
151 |
|
|
--------------------------------------------------------------------------------
|
152 |
|
|
Slack (setup path): -0.285ns (requirement - (data path - clock path skew + uncertainty))
|
153 |
|
|
Source: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_18_1 (FF)
|
154 |
|
|
Destination: AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2 (FF)
|
155 |
|
|
Requirement: 4.500ns
|
156 |
|
|
Data Path Delay: 4.626ns (Levels of Logic = 10)
|
157 |
|
|
Clock Path Skew: -0.124ns (1.023 - 1.147)
|
158 |
|
|
Source Clock: cp2_BUFGP rising at 0.000ns
|
159 |
|
|
Destination Clock: cp2_BUFGP rising at 4.500ns
|
160 |
|
|
Clock Uncertainty: 0.035ns
|
161 |
|
|
|
162 |
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
163 |
|
|
Total System Jitter (TSJ): 0.070ns
|
164 |
|
|
Total Input Jitter (TIJ): 0.000ns
|
165 |
|
|
Discrete Jitter (DJ): 0.000ns
|
166 |
|
|
Phase Error (PE): 0.000ns
|
167 |
|
|
|
168 |
|
|
Maximum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_18_1 to AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
|
169 |
|
|
Location Delay type Delay(ns) Physical Resource
|
170 |
|
|
Logical Resource(s)
|
171 |
|
|
------------------------------------------------- -------------------
|
172 |
|
|
SLICE_X17Y32.BQ Tcko 0.326 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_18_3
|
173 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_18_1
|
174 |
|
|
SLICE_X16Y32.B1 net (fanout=2) 0.780 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_18_1
|
175 |
|
|
SLICE_X16Y32.B Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
|
176 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>71
|
177 |
|
|
SLICE_X16Y32.A5 net (fanout=1) 0.178 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>71
|
178 |
|
|
SLICE_X16Y32.A Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
|
179 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>142
|
180 |
|
|
SLICE_X16Y36.A6 net (fanout=1) 0.372 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>142
|
181 |
|
|
SLICE_X16Y36.A Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<24>
|
182 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>226
|
183 |
|
|
SLICE_X16Y36.B6 net (fanout=1) 0.121 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>226
|
184 |
|
|
SLICE_X16Y36.B Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<24>
|
185 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>310
|
186 |
|
|
SLICE_X23Y41.A6 net (fanout=1) 0.505 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>310
|
187 |
|
|
SLICE_X23Y41.A Tilo 0.080 AVR_Core_cm3_Inst/BP_Inst/reg_rd_out_cml_2<2>
|
188 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>396
|
189 |
|
|
SLICE_X23Y41.B6 net (fanout=1) 0.105 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>396
|
190 |
|
|
SLICE_X23Y41.B Tilo 0.080 AVR_Core_cm3_Inst/BP_Inst/reg_rd_out_cml_2<2>
|
191 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>480
|
192 |
|
|
SLICE_X22Y41.A3 net (fanout=19) 0.491 AVR_Core_cm3_Inst/reg_rd_out<1>
|
193 |
|
|
SLICE_X22Y41.A Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry_cml_2<6>
|
194 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry_3_and00001
|
195 |
|
|
SLICE_X22Y41.D6 net (fanout=6) 0.268 AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry<3>
|
196 |
|
|
SLICE_X22Y41.D Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry_cml_2<6>
|
197 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000043
|
198 |
|
|
SLICE_X21Y42.D1 net (fanout=1) 0.624 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000043
|
199 |
|
|
SLICE_X21Y42.D Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
|
200 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000062
|
201 |
|
|
SLICE_X21Y42.C6 net (fanout=1) 0.106 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000062
|
202 |
|
|
SLICE_X21Y42.CLK Tas 0.030 AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
|
203 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2_rstpot
|
204 |
|
|
AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
|
205 |
|
|
------------------------------------------------- ---------------------------
|
206 |
|
|
Total 4.626ns (1.076ns logic, 3.550ns route)
|
207 |
|
|
(23.3% logic, 76.7% route)
|
208 |
|
|
|
209 |
|
|
--------------------------------------------------------------------------------
|
210 |
|
|
|
211 |
|
|
Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 4.5 ns HIGH 50%;
|
212 |
|
|
--------------------------------------------------------------------------------
|
213 |
|
|
Slack (hold path): 0.289ns (requirement - (clock path skew + uncertainty - data path))
|
214 |
|
|
Source: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/idc_rcall_cml_2 (FF)
|
215 |
|
|
Destination: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/rcall_st1 (FF)
|
216 |
|
|
Requirement: 0.000ns
|
217 |
|
|
Data Path Delay: 0.398ns (Levels of Logic = 1)
|
218 |
|
|
Clock Path Skew: 0.109ns (1.150 - 1.041)
|
219 |
|
|
Source Clock: cp2_BUFGP rising at 4.500ns
|
220 |
|
|
Destination Clock: cp2_BUFGP rising at 4.500ns
|
221 |
|
|
Clock Uncertainty: 0.000ns
|
222 |
|
|
|
223 |
|
|
Minimum Data Path: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/idc_rcall_cml_2 to AVR_Core_cm3_Inst/pm_fetch_dec_Inst/rcall_st1
|
224 |
|
|
Location Delay type Delay(ns) Physical Resource
|
225 |
|
|
Logical Resource(s)
|
226 |
|
|
------------------------------------------------- -------------------
|
227 |
|
|
SLICE_X9Y60.BQ Tcko 0.300 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/idc_rcall_cml_2
|
228 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/idc_rcall_cml_2
|
229 |
|
|
SLICE_X11Y59.A6 net (fanout=21) 0.228 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/idc_rcall_cml_2
|
230 |
|
|
SLICE_X11Y59.CLK Tah (-Th) 0.130 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/icall_st2
|
231 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/rcall_st1_mux00011
|
232 |
|
|
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/rcall_st1
|
233 |
|
|
------------------------------------------------- ---------------------------
|
234 |
|
|
Total 0.398ns (0.170ns logic, 0.228ns route)
|
235 |
|
|
(42.7% logic, 57.3% route)
|
236 |
|
|
|
237 |
|
|
--------------------------------------------------------------------------------
|
238 |
|
|
Slack (hold path): 0.305ns (requirement - (clock path skew + uncertainty - data path))
|
239 |
|
|
Source: AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_2_0 (FF)
|
240 |
|
|
Destination: AVR_Core_cm3_Inst/GPRF_Inst/r26h_0 (FF)
|
241 |
|
|
Requirement: 0.000ns
|
242 |
|
|
Data Path Delay: 0.357ns (Levels of Logic = 1)
|
243 |
|
|
Clock Path Skew: 0.052ns (0.511 - 0.459)
|
244 |
|
|
Source Clock: cp2_BUFGP rising at 4.500ns
|
245 |
|
|
Destination Clock: cp2_BUFGP rising at 4.500ns
|
246 |
|
|
Clock Uncertainty: 0.000ns
|
247 |
|
|
|
248 |
|
|
Minimum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_2_0 to AVR_Core_cm3_Inst/GPRF_Inst/r26h_0
|
249 |
|
|
Location Delay type Delay(ns) Physical Resource
|
250 |
|
|
Logical Resource(s)
|
251 |
|
|
------------------------------------------------- -------------------
|
252 |
|
|
SLICE_X11Y37.AQ Tcko 0.300 AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_2<3>
|
253 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_2_0
|
254 |
|
|
SLICE_X8Y37.A6 net (fanout=1) 0.208 AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_2<0>
|
255 |
|
|
SLICE_X8Y37.CLK Tah (-Th) 0.151 AVR_Core_cm3_Inst/GPRF_Inst/r26h<3>
|
256 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/r26h_mux0003<0>1
|
257 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/r26h_0
|
258 |
|
|
------------------------------------------------- ---------------------------
|
259 |
|
|
Total 0.357ns (0.149ns logic, 0.208ns route)
|
260 |
|
|
(41.7% logic, 58.3% route)
|
261 |
|
|
|
262 |
|
|
--------------------------------------------------------------------------------
|
263 |
|
|
Slack (hold path): 0.308ns (requirement - (clock path skew + uncertainty - data path))
|
264 |
|
|
Source: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_25_1 (FF)
|
265 |
|
|
Destination: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_25_1 (FF)
|
266 |
|
|
Requirement: 0.000ns
|
267 |
|
|
Data Path Delay: 0.357ns (Levels of Logic = 0)
|
268 |
|
|
Clock Path Skew: 0.049ns (0.443 - 0.394)
|
269 |
|
|
Source Clock: cp2_BUFGP rising at 4.500ns
|
270 |
|
|
Destination Clock: cp2_BUFGP rising at 4.500ns
|
271 |
|
|
Clock Uncertainty: 0.000ns
|
272 |
|
|
|
273 |
|
|
Minimum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_25_1 to AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_25_1
|
274 |
|
|
Location Delay type Delay(ns) Physical Resource
|
275 |
|
|
Logical Resource(s)
|
276 |
|
|
------------------------------------------------- -------------------
|
277 |
|
|
SLICE_X23Y33.BQ Tcko 0.300 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_25_3
|
278 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_25_1
|
279 |
|
|
SLICE_X21Y33.BX net (fanout=2) 0.224 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_25_1
|
280 |
|
|
SLICE_X21Y33.CLK Tckdi (-Th) 0.167 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_25_3
|
281 |
|
|
AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_25_1
|
282 |
|
|
------------------------------------------------- ---------------------------
|
283 |
|
|
Total 0.357ns (0.133ns logic, 0.224ns route)
|
284 |
|
|
(37.3% logic, 62.7% route)
|
285 |
|
|
|
286 |
|
|
--------------------------------------------------------------------------------
|
287 |
|
|
|
288 |
|
|
Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 4.5 ns HIGH 50%;
|
289 |
|
|
--------------------------------------------------------------------------------
|
290 |
|
|
Slack: 3.300ns (period - (min low pulse limit / (low pulse / period)))
|
291 |
|
|
Period: 4.500ns
|
292 |
|
|
Low pulse: 2.250ns
|
293 |
|
|
Low pulse limit: 0.600ns (Twpl)
|
294 |
|
|
Physical resource: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_0_7/CLK
|
295 |
|
|
Logical resource: AVR_Core_cm3_Inst/GPRF_Inst/Mshreg_register_file_cml_2_0_4/CLK
|
296 |
|
|
Location pin: SLICE_X0Y21.CLK
|
297 |
|
|
Clock network: cp2_BUFGP
|
298 |
|
|
--------------------------------------------------------------------------------
|
299 |
|
|
Slack: 3.300ns (period - (min high pulse limit / (high pulse / period)))
|
300 |
|
|
Period: 4.500ns
|
301 |
|
|
High pulse: 2.250ns
|
302 |
|
|
High pulse limit: 0.600ns (Twph)
|
303 |
|
|
Physical resource: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_0_7/CLK
|
304 |
|
|
Logical resource: AVR_Core_cm3_Inst/GPRF_Inst/Mshreg_register_file_cml_2_0_4/CLK
|
305 |
|
|
Location pin: SLICE_X0Y21.CLK
|
306 |
|
|
Clock network: cp2_BUFGP
|
307 |
|
|
--------------------------------------------------------------------------------
|
308 |
|
|
Slack: 3.300ns (period - (min low pulse limit / (low pulse / period)))
|
309 |
|
|
Period: 4.500ns
|
310 |
|
|
Low pulse: 2.250ns
|
311 |
|
|
Low pulse limit: 0.600ns (Twpl)
|
312 |
|
|
Physical resource: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_0_7/CLK
|
313 |
|
|
Logical resource: AVR_Core_cm3_Inst/GPRF_Inst/Mshreg_register_file_cml_2_0_5/CLK
|
314 |
|
|
Location pin: SLICE_X0Y21.CLK
|
315 |
|
|
Clock network: cp2_BUFGP
|
316 |
|
|
--------------------------------------------------------------------------------
|
317 |
|
|
|
318 |
|
|
|
319 |
|
|
1 constraint not met.
|
320 |
|
|
|
321 |
|
|
|
322 |
|
|
Data Sheet report:
|
323 |
|
|
-----------------
|
324 |
|
|
All values displayed in nanoseconds (ns)
|
325 |
|
|
|
326 |
|
|
Clock to Setup on destination clock cp2
|
327 |
|
|
---------------+---------+---------+---------+---------+
|
328 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
329 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
330 |
|
|
---------------+---------+---------+---------+---------+
|
331 |
|
|
cp2 | 4.819| | | |
|
332 |
|
|
---------------+---------+---------+---------+---------+
|
333 |
|
|
|
334 |
|
|
|
335 |
|
|
Timing summary:
|
336 |
|
|
---------------
|
337 |
|
|
|
338 |
|
|
Timing errors: 33 Score: 3958 (Setup/Max: 3958, Hold: 0)
|
339 |
|
|
|
340 |
|
|
Constraints cover 184139 paths, 0 nets, and 8330 connections
|
341 |
|
|
|
342 |
|
|
Design statistics:
|
343 |
|
|
Minimum period: 4.819ns{1} (Maximum frequency: 207.512MHz)
|
344 |
|
|
|
345 |
|
|
|
346 |
|
|
------------------------------------Footnotes-----------------------------------
|
347 |
|
|
1) The minimum period statistic assumes all single cycle delays.
|
348 |
|
|
|
349 |
|
|
Analysis completed Wed Oct 06 16:53:13 2010
|
350 |
|
|
--------------------------------------------------------------------------------
|
351 |
|
|
|
352 |
|
|
Trace Settings:
|
353 |
|
|
-------------------------
|
354 |
|
|
Trace Settings
|
355 |
|
|
|
356 |
|
|
Peak Memory Usage: 271 MB
|
357 |
|
|
|
358 |
|
|
|
359 |
|
|
|