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Release 11.1 Trace  (nt)

Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise

C:/EDAptability/coremultiplier/reference/avr/ise/ise_v5_cm4_one_syneda/ise_v5_cm4_one_syneda/ise_v5_cm4_one_syneda.ise

-intstyle ise -v 3 -s 3 -fastpaths -xml avr_core_cm4_top.twx

avr_core_cm4_top.ncd -o avr_core_cm4_top.twr avr_core_cm4_top.pcf -ucf

avr_core_cm4_top.ucf

Design file:              avr_core_cm4_top.ncd

Physical constraint file: avr_core_cm4_top.pcf

Device,package,speed:     xc5vlx50,ff324,-3 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)

Report level:             verbose report

Environment Variable      Effect

--------------------      ------

NONE                      No environment variables were set

--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths

   option. All paths that are not constrained will be reported in the

   unconstrained paths section(s) of the report.

INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on

   a 50 Ohm transmission line loading model.  For the details of this model,

   and for more information on accounting for different loading conditions,

   please see the device datasheet.

================================================================================

Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 3 ns HIGH 50%;

 47967 paths analyzed, 3840 endpoints analyzed, 564 failing endpoints

 564 timing errors detected. (564 setup errors, 0 hold errors, 0 component switching limit errors)

 Minimum period is   4.064ns.

--------------------------------------------------------------------------------

Slack (setup path):     -1.064ns (requirement - (data path - clock path skew + uncertainty))

  Source:               AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st (FF)

  Destination:          AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_push_cml_1 (FF)

  Requirement:          3.000ns

  Data Path Delay:      3.845ns (Levels of Logic = 5)

  Clock Path Skew:      -0.184ns (1.061 - 1.245)

  Source Clock:         cp2_BUFGP rising at 0.000ns

  Destination Clock:    cp2_BUFGP rising at 3.000ns

  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE

    Total System Jitter (TSJ):  0.070ns

    Total Input Jitter (TIJ):   0.000ns

    Discrete Jitter (DJ):       0.000ns

    Phase Error (PE):           0.000ns

  Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st to AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_push_cml_1

    Location             Delay type         Delay(ns)  Physical Resource

                                                       Logical Resource(s)

    -------------------------------------------------  -------------------

    SLICE_X7Y18.CQ       Tcko                  0.326   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st

    SLICE_X11Y35.D5      net (fanout=13)       1.099   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st

    SLICE_X11Y35.D       Tilo                  0.080   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ld_st

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st4

    SLICE_X10Y36.C6      net (fanout=16)       0.279   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st4

    SLICE_X10Y36.C       Tilo                  0.080   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<13>

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/instruction_code_reg<13>1

    SLICE_X11Y33.C2      net (fanout=20)       0.706   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/instruction_code_reg<13>

    SLICE_X11Y33.C       Tilo                  0.080   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_ret_cmp_eq000011

    SLICE_X10Y44.B6      net (fanout=15)       0.789   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N74

    SLICE_X10Y44.B       Tilo                  0.080   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/rjmp_st_cml_3

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_pop_cmp_eq000011

    SLICE_X11Y44.A5      net (fanout=3)        0.298   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N101

    SLICE_X11Y44.CLK     Tas                   0.028   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_push_cml_3

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_push_cmp_eq00001

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_push_cml_1

    -------------------------------------------------  ---------------------------

    Total                                      3.845ns (0.674ns logic, 3.171ns route)

                                                       (17.5% logic, 82.5% route)

--------------------------------------------------------------------------------

Slack (setup path):     -1.042ns (requirement - (data path - clock path skew + uncertainty))

  Source:               AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramadr_int_4 (FF)

  Destination:          AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1_5 (FF)

  Requirement:          3.000ns

  Data Path Delay:      3.853ns (Levels of Logic = 5)

  Clock Path Skew:      -0.154ns (1.113 - 1.267)

  Source Clock:         cp2_BUFGP rising at 0.000ns

  Destination Clock:    cp2_BUFGP rising at 3.000ns

  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE

    Total System Jitter (TSJ):  0.070ns

    Total Input Jitter (TIJ):   0.000ns

    Discrete Jitter (DJ):       0.000ns

    Phase Error (PE):           0.000ns

  Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramadr_int_4 to AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1_5

    Location             Delay type         Delay(ns)  Physical Resource

                                                       Logical Resource(s)

    -------------------------------------------------  -------------------

    SLICE_X6Y19.AQ       Tcko                  0.326   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramadr_int<7>

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramadr_int_4

    SLICE_X10Y11.B6      net (fanout=131)      1.285   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramadr_int<4>

    SLICE_X10Y11.B       Tilo                  0.080   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_8_7

                                                       AVR_Core_cm4_Inst/GPRF_Inst/reg_rr_out<5>201_SW1

    SLICE_X10Y16.C1      net (fanout=1)        0.880   N389

    SLICE_X10Y16.C       Tilo                  0.080   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_20_3

                                                       AVR_Core_cm4_Inst/GPRF_Inst/reg_rr_out<5>201

    SLICE_X10Y16.B5      net (fanout=1)        0.290   AVR_Core_cm4_Inst/GPRF_Inst/reg_rr_out<5>201

    SLICE_X10Y16.B       Tilo                  0.080   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_20_3

                                                       AVR_Core_cm4_Inst/GPRF_Inst/reg_rr_out<5>249

    SLICE_X11Y21.C4      net (fanout=1)        0.560   AVR_Core_cm4_Inst/GPRF_Inst/reg_rr_out<5>249

    SLICE_X11Y21.C       Tilo                  0.080   AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1<5>

                                                       AVR_Core_cm4_Inst/GPRF_Inst/reg_rr_out<5>617

    SLICE_X11Y21.D5      net (fanout=1)        0.164   AVR_Core_cm4_Inst/reg_rr_out<5>

    SLICE_X11Y21.CLK     Tas                   0.028   AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1<5>

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/alu_data_r_in<5>1

                                                       AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1_5

    -------------------------------------------------  ---------------------------

    Total                                      3.853ns (0.674ns logic, 3.179ns route)

                                                       (17.5% logic, 82.5% route)

--------------------------------------------------------------------------------

Slack (setup path):     -1.041ns (requirement - (data path - clock path skew + uncertainty))

  Source:               AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st (FF)

  Destination:          AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1_1 (FF)

  Requirement:          3.000ns

  Data Path Delay:      3.875ns (Levels of Logic = 5)

  Clock Path Skew:      -0.131ns (1.114 - 1.245)

  Source Clock:         cp2_BUFGP rising at 0.000ns

  Destination Clock:    cp2_BUFGP rising at 3.000ns

  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE

    Total System Jitter (TSJ):  0.070ns

    Total Input Jitter (TIJ):   0.000ns

    Discrete Jitter (DJ):       0.000ns

    Phase Error (PE):           0.000ns

  Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st to AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1_1

    Location             Delay type         Delay(ns)  Physical Resource

                                                       Logical Resource(s)

    -------------------------------------------------  -------------------

    SLICE_X7Y18.CQ       Tcko                  0.326   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st

    SLICE_X11Y35.D5      net (fanout=13)       1.099   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st

    SLICE_X11Y35.D       Tilo                  0.080   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ld_st

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st4

    SLICE_X10Y36.C6      net (fanout=16)       0.279   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st4

    SLICE_X10Y36.C       Tilo                  0.080   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<13>

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/instruction_code_reg<13>1

    SLICE_X11Y33.C2      net (fanout=20)       0.706   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/instruction_code_reg<13>

    SLICE_X11Y33.C       Tilo                  0.080   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_ret_cmp_eq000011

    SLICE_X11Y33.D5      net (fanout=15)       0.186   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N74

    SLICE_X11Y33.D       Tilo                  0.080   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011

    SLICE_X11Y20.C3      net (fanout=13)       0.929   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001

    SLICE_X11Y20.CLK     Tas                   0.030   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rr_out_cml_1<1>

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/alu_data_r_in<1>1

                                                       AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1_1

    -------------------------------------------------  ---------------------------

    Total                                      3.875ns (0.676ns logic, 3.199ns route)

                                                       (17.4% logic, 82.6% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 3 ns HIGH 50%;

--------------------------------------------------------------------------------

Slack (hold path):      0.233ns (requirement - (clock path skew + uncertainty - data path))

  Source:               AVR_Core_cm4_Inst/IORegs_Inst/rampz_4 (FF)

  Destination:          AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1_4 (FF)

  Requirement:          0.000ns

  Data Path Delay:      0.242ns (Levels of Logic = 0)

  Clock Path Skew:      0.009ns (0.122 - 0.113)

  Source Clock:         cp2_BUFGP rising at 3.000ns

  Destination Clock:    cp2_BUFGP rising at 3.000ns

  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm4_Inst/IORegs_Inst/rampz_4 to AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1_4

    Location             Delay type         Delay(ns)  Physical Resource

                                                       Logical Resource(s)

    -------------------------------------------------  -------------------

    SLICE_X13Y76.BQ      Tcko                  0.300   AVR_Core_cm4_Inst/IORegs_Inst/rampz<6>

                                                       AVR_Core_cm4_Inst/IORegs_Inst/rampz_4

    SLICE_X12Y76.AX      net (fanout=1)        0.115   AVR_Core_cm4_Inst/IORegs_Inst/rampz<4>

    SLICE_X12Y76.CLK     Tckdi       (-Th)     0.173   AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1<7>

                                                       AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1_4

    -------------------------------------------------  ---------------------------

    Total                                      0.242ns (0.127ns logic, 0.115ns route)

                                                       (52.5% logic, 47.5% route)

--------------------------------------------------------------------------------

Slack (hold path):      0.236ns (requirement - (clock path skew + uncertainty - data path))

  Source:               AVR_Core_cm4_Inst/IORegs_Inst/rampz_6 (FF)

  Destination:          AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1_6 (FF)

  Requirement:          0.000ns

  Data Path Delay:      0.245ns (Levels of Logic = 0)

  Clock Path Skew:      0.009ns (0.122 - 0.113)

  Source Clock:         cp2_BUFGP rising at 3.000ns

  Destination Clock:    cp2_BUFGP rising at 3.000ns

  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm4_Inst/IORegs_Inst/rampz_6 to AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1_6

    Location             Delay type         Delay(ns)  Physical Resource

                                                       Logical Resource(s)

    -------------------------------------------------  -------------------

    SLICE_X13Y76.DQ      Tcko                  0.300   AVR_Core_cm4_Inst/IORegs_Inst/rampz<6>

                                                       AVR_Core_cm4_Inst/IORegs_Inst/rampz_6

    SLICE_X12Y76.CX      net (fanout=1)        0.115   AVR_Core_cm4_Inst/IORegs_Inst/rampz<6>

    SLICE_X12Y76.CLK     Tckdi       (-Th)     0.170   AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1<7>

                                                       AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1_6

    -------------------------------------------------  ---------------------------

    Total                                      0.245ns (0.130ns logic, 0.115ns route)

                                                       (53.1% logic, 46.9% route)

--------------------------------------------------------------------------------

Slack (hold path):      0.312ns (requirement - (clock path skew + uncertainty - data path))

  Source:               AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_0 (FF)

  Destination:          AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_cml_1_0 (FF)

  Requirement:          0.000ns

  Data Path Delay:      0.358ns (Levels of Logic = 0)

  Clock Path Skew:      0.046ns (0.508 - 0.462)

  Source Clock:         cp2_BUFGP rising at 3.000ns

  Destination Clock:    cp2_BUFGP rising at 3.000ns

  Clock Uncertainty:    0.000ns

  Minimum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_0 to AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_cml_1_0

    Location             Delay type         Delay(ns)  Physical Resource

                                                       Logical Resource(s)

    -------------------------------------------------  -------------------

    SLICE_X7Y47.AQ       Tcko                  0.300   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp<3>

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_0

    SLICE_X4Y46.DX       net (fanout=1)        0.228   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp<0>

    SLICE_X4Y46.CLK      Tckdi       (-Th)     0.170   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_cml_1<0>

                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_cml_1_0

    -------------------------------------------------  ---------------------------

    Total                                      0.358ns (0.130ns logic, 0.228ns route)

                                                       (36.3% logic, 63.7% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 3 ns HIGH 50%;

--------------------------------------------------------------------------------

Slack: 1.800ns (period - (min low pulse limit / (low pulse / period)))

  Period: 3.000ns

  Low pulse: 1.500ns

  Low pulse limit: 0.600ns (Twpl)

  Physical resource: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_24_3/CLK

  Logical resource: AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_24_0/CLK

  Location pin: SLICE_X0Y5.CLK

  Clock network: cp2_BUFGP

--------------------------------------------------------------------------------

Slack: 1.800ns (period - (min high pulse limit / (high pulse / period)))

  Period: 3.000ns

  High pulse: 1.500ns

  High pulse limit: 0.600ns (Twph)

  Physical resource: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_24_3/CLK

  Logical resource: AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_24_0/CLK

  Location pin: SLICE_X0Y5.CLK

  Clock network: cp2_BUFGP

--------------------------------------------------------------------------------

Slack: 1.800ns (period - (min low pulse limit / (low pulse / period)))

  Period: 3.000ns

  Low pulse: 1.500ns

  Low pulse limit: 0.600ns (Twpl)

  Physical resource: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_24_3/CLK

  Logical resource: AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_24_1/CLK

  Location pin: SLICE_X0Y5.CLK

  Clock network: cp2_BUFGP

--------------------------------------------------------------------------------

1 constraint not met.

Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)

Clock to Setup on destination clock cp2

---------------+---------+---------+---------+---------+

               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|

Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|

---------------+---------+---------+---------+---------+

cp2            |    4.064|         |         |         |

---------------+---------+---------+---------+---------+

Timing summary:

---------------

Timing errors: 564  Score: 211258  (Setup/Max: 211258, Hold: 0)

Constraints cover 47967 paths, 0 nets, and 10466 connections

Design statistics:

   Minimum period:   4.064ns{1}   (Maximum frequency: 246.063MHz)

------------------------------------Footnotes-----------------------------------

1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Sun Oct 03 22:09:03 2010

--------------------------------------------------------------------------------

Trace Settings:

-------------------------

Trace Settings

Peak Memory Usage: 279 MB