1 |
2 |
tobil |
--------------------------------------------------------------------------------
|
2 |
|
|
Release 11.1 Trace (nt)
|
3 |
|
|
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
|
4 |
|
|
|
5 |
|
|
C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
|
6 |
|
|
C:/EDAptability/coremultiplier/reference/avr/ise/ise_v5_cm4_one_syneda/ise_v5_cm4_one_syneda/ise_v5_cm4_one_syneda.ise
|
7 |
|
|
-intstyle ise -v 3 -s 3 -fastpaths -xml avr_core_cm4_top.twx
|
8 |
|
|
avr_core_cm4_top.ncd -o avr_core_cm4_top.twr avr_core_cm4_top.pcf -ucf
|
9 |
|
|
avr_core_cm4_top.ucf
|
10 |
|
|
|
11 |
|
|
Design file: avr_core_cm4_top.ncd
|
12 |
|
|
Physical constraint file: avr_core_cm4_top.pcf
|
13 |
|
|
Device,package,speed: xc5vlx50,ff324,-3 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
|
14 |
|
|
Report level: verbose report
|
15 |
|
|
|
16 |
|
|
Environment Variable Effect
|
17 |
|
|
-------------------- ------
|
18 |
|
|
NONE No environment variables were set
|
19 |
|
|
--------------------------------------------------------------------------------
|
20 |
|
|
|
21 |
|
|
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
|
22 |
|
|
option. All paths that are not constrained will be reported in the
|
23 |
|
|
unconstrained paths section(s) of the report.
|
24 |
|
|
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
|
25 |
|
|
a 50 Ohm transmission line loading model. For the details of this model,
|
26 |
|
|
and for more information on accounting for different loading conditions,
|
27 |
|
|
please see the device datasheet.
|
28 |
|
|
|
29 |
|
|
================================================================================
|
30 |
|
|
Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 3 ns HIGH 50%;
|
31 |
|
|
|
32 |
|
|
47967 paths analyzed, 3840 endpoints analyzed, 564 failing endpoints
|
33 |
|
|
564 timing errors detected. (564 setup errors, 0 hold errors, 0 component switching limit errors)
|
34 |
|
|
Minimum period is 4.064ns.
|
35 |
|
|
--------------------------------------------------------------------------------
|
36 |
|
|
Slack (setup path): -1.064ns (requirement - (data path - clock path skew + uncertainty))
|
37 |
|
|
Source: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st (FF)
|
38 |
|
|
Destination: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_push_cml_1 (FF)
|
39 |
|
|
Requirement: 3.000ns
|
40 |
|
|
Data Path Delay: 3.845ns (Levels of Logic = 5)
|
41 |
|
|
Clock Path Skew: -0.184ns (1.061 - 1.245)
|
42 |
|
|
Source Clock: cp2_BUFGP rising at 0.000ns
|
43 |
|
|
Destination Clock: cp2_BUFGP rising at 3.000ns
|
44 |
|
|
Clock Uncertainty: 0.035ns
|
45 |
|
|
|
46 |
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
47 |
|
|
Total System Jitter (TSJ): 0.070ns
|
48 |
|
|
Total Input Jitter (TIJ): 0.000ns
|
49 |
|
|
Discrete Jitter (DJ): 0.000ns
|
50 |
|
|
Phase Error (PE): 0.000ns
|
51 |
|
|
|
52 |
|
|
Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st to AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_push_cml_1
|
53 |
|
|
Location Delay type Delay(ns) Physical Resource
|
54 |
|
|
Logical Resource(s)
|
55 |
|
|
------------------------------------------------- -------------------
|
56 |
|
|
SLICE_X7Y18.CQ Tcko 0.326 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st
|
57 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st
|
58 |
|
|
SLICE_X11Y35.D5 net (fanout=13) 1.099 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st
|
59 |
|
|
SLICE_X11Y35.D Tilo 0.080 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ld_st
|
60 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st4
|
61 |
|
|
SLICE_X10Y36.C6 net (fanout=16) 0.279 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st4
|
62 |
|
|
SLICE_X10Y36.C Tilo 0.080 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<13>
|
63 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/instruction_code_reg<13>1
|
64 |
|
|
SLICE_X11Y33.C2 net (fanout=20) 0.706 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/instruction_code_reg<13>
|
65 |
|
|
SLICE_X11Y33.C Tilo 0.080 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1
|
66 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_ret_cmp_eq000011
|
67 |
|
|
SLICE_X10Y44.B6 net (fanout=15) 0.789 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N74
|
68 |
|
|
SLICE_X10Y44.B Tilo 0.080 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/rjmp_st_cml_3
|
69 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_pop_cmp_eq000011
|
70 |
|
|
SLICE_X11Y44.A5 net (fanout=3) 0.298 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N101
|
71 |
|
|
SLICE_X11Y44.CLK Tas 0.028 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_push_cml_3
|
72 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_push_cmp_eq00001
|
73 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_push_cml_1
|
74 |
|
|
------------------------------------------------- ---------------------------
|
75 |
|
|
Total 3.845ns (0.674ns logic, 3.171ns route)
|
76 |
|
|
(17.5% logic, 82.5% route)
|
77 |
|
|
|
78 |
|
|
--------------------------------------------------------------------------------
|
79 |
|
|
Slack (setup path): -1.042ns (requirement - (data path - clock path skew + uncertainty))
|
80 |
|
|
Source: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramadr_int_4 (FF)
|
81 |
|
|
Destination: AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1_5 (FF)
|
82 |
|
|
Requirement: 3.000ns
|
83 |
|
|
Data Path Delay: 3.853ns (Levels of Logic = 5)
|
84 |
|
|
Clock Path Skew: -0.154ns (1.113 - 1.267)
|
85 |
|
|
Source Clock: cp2_BUFGP rising at 0.000ns
|
86 |
|
|
Destination Clock: cp2_BUFGP rising at 3.000ns
|
87 |
|
|
Clock Uncertainty: 0.035ns
|
88 |
|
|
|
89 |
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
90 |
|
|
Total System Jitter (TSJ): 0.070ns
|
91 |
|
|
Total Input Jitter (TIJ): 0.000ns
|
92 |
|
|
Discrete Jitter (DJ): 0.000ns
|
93 |
|
|
Phase Error (PE): 0.000ns
|
94 |
|
|
|
95 |
|
|
Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramadr_int_4 to AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1_5
|
96 |
|
|
Location Delay type Delay(ns) Physical Resource
|
97 |
|
|
Logical Resource(s)
|
98 |
|
|
------------------------------------------------- -------------------
|
99 |
|
|
SLICE_X6Y19.AQ Tcko 0.326 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramadr_int<7>
|
100 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramadr_int_4
|
101 |
|
|
SLICE_X10Y11.B6 net (fanout=131) 1.285 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramadr_int<4>
|
102 |
|
|
SLICE_X10Y11.B Tilo 0.080 AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_8_7
|
103 |
|
|
AVR_Core_cm4_Inst/GPRF_Inst/reg_rr_out<5>201_SW1
|
104 |
|
|
SLICE_X10Y16.C1 net (fanout=1) 0.880 N389
|
105 |
|
|
SLICE_X10Y16.C Tilo 0.080 AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_20_3
|
106 |
|
|
AVR_Core_cm4_Inst/GPRF_Inst/reg_rr_out<5>201
|
107 |
|
|
SLICE_X10Y16.B5 net (fanout=1) 0.290 AVR_Core_cm4_Inst/GPRF_Inst/reg_rr_out<5>201
|
108 |
|
|
SLICE_X10Y16.B Tilo 0.080 AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_20_3
|
109 |
|
|
AVR_Core_cm4_Inst/GPRF_Inst/reg_rr_out<5>249
|
110 |
|
|
SLICE_X11Y21.C4 net (fanout=1) 0.560 AVR_Core_cm4_Inst/GPRF_Inst/reg_rr_out<5>249
|
111 |
|
|
SLICE_X11Y21.C Tilo 0.080 AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1<5>
|
112 |
|
|
AVR_Core_cm4_Inst/GPRF_Inst/reg_rr_out<5>617
|
113 |
|
|
SLICE_X11Y21.D5 net (fanout=1) 0.164 AVR_Core_cm4_Inst/reg_rr_out<5>
|
114 |
|
|
SLICE_X11Y21.CLK Tas 0.028 AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1<5>
|
115 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/alu_data_r_in<5>1
|
116 |
|
|
AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1_5
|
117 |
|
|
------------------------------------------------- ---------------------------
|
118 |
|
|
Total 3.853ns (0.674ns logic, 3.179ns route)
|
119 |
|
|
(17.5% logic, 82.5% route)
|
120 |
|
|
|
121 |
|
|
--------------------------------------------------------------------------------
|
122 |
|
|
Slack (setup path): -1.041ns (requirement - (data path - clock path skew + uncertainty))
|
123 |
|
|
Source: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st (FF)
|
124 |
|
|
Destination: AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1_1 (FF)
|
125 |
|
|
Requirement: 3.000ns
|
126 |
|
|
Data Path Delay: 3.875ns (Levels of Logic = 5)
|
127 |
|
|
Clock Path Skew: -0.131ns (1.114 - 1.245)
|
128 |
|
|
Source Clock: cp2_BUFGP rising at 0.000ns
|
129 |
|
|
Destination Clock: cp2_BUFGP rising at 3.000ns
|
130 |
|
|
Clock Uncertainty: 0.035ns
|
131 |
|
|
|
132 |
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
133 |
|
|
Total System Jitter (TSJ): 0.070ns
|
134 |
|
|
Total Input Jitter (TIJ): 0.000ns
|
135 |
|
|
Discrete Jitter (DJ): 0.000ns
|
136 |
|
|
Phase Error (PE): 0.000ns
|
137 |
|
|
|
138 |
|
|
Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st to AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1_1
|
139 |
|
|
Location Delay type Delay(ns) Physical Resource
|
140 |
|
|
Logical Resource(s)
|
141 |
|
|
------------------------------------------------- -------------------
|
142 |
|
|
SLICE_X7Y18.CQ Tcko 0.326 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st
|
143 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st
|
144 |
|
|
SLICE_X11Y35.D5 net (fanout=13) 1.099 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/st_st
|
145 |
|
|
SLICE_X11Y35.D Tilo 0.080 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ld_st
|
146 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st4
|
147 |
|
|
SLICE_X10Y36.C6 net (fanout=16) 0.279 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st4
|
148 |
|
|
SLICE_X10Y36.C Tilo 0.080 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<13>
|
149 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/instruction_code_reg<13>1
|
150 |
|
|
SLICE_X11Y33.C2 net (fanout=20) 0.706 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/instruction_code_reg<13>
|
151 |
|
|
SLICE_X11Y33.C Tilo 0.080 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1
|
152 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_ret_cmp_eq000011
|
153 |
|
|
SLICE_X11Y33.D5 net (fanout=15) 0.186 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N74
|
154 |
|
|
SLICE_X11Y33.D Tilo 0.080 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1
|
155 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011
|
156 |
|
|
SLICE_X11Y20.C3 net (fanout=13) 0.929 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001
|
157 |
|
|
SLICE_X11Y20.CLK Tas 0.030 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rr_out_cml_1<1>
|
158 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/alu_data_r_in<1>1
|
159 |
|
|
AVR_Core_cm4_Inst/ALU_Inst/alu_data_r_in_cml_1_1
|
160 |
|
|
------------------------------------------------- ---------------------------
|
161 |
|
|
Total 3.875ns (0.676ns logic, 3.199ns route)
|
162 |
|
|
(17.4% logic, 82.6% route)
|
163 |
|
|
|
164 |
|
|
--------------------------------------------------------------------------------
|
165 |
|
|
|
166 |
|
|
Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 3 ns HIGH 50%;
|
167 |
|
|
--------------------------------------------------------------------------------
|
168 |
|
|
Slack (hold path): 0.233ns (requirement - (clock path skew + uncertainty - data path))
|
169 |
|
|
Source: AVR_Core_cm4_Inst/IORegs_Inst/rampz_4 (FF)
|
170 |
|
|
Destination: AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1_4 (FF)
|
171 |
|
|
Requirement: 0.000ns
|
172 |
|
|
Data Path Delay: 0.242ns (Levels of Logic = 0)
|
173 |
|
|
Clock Path Skew: 0.009ns (0.122 - 0.113)
|
174 |
|
|
Source Clock: cp2_BUFGP rising at 3.000ns
|
175 |
|
|
Destination Clock: cp2_BUFGP rising at 3.000ns
|
176 |
|
|
Clock Uncertainty: 0.000ns
|
177 |
|
|
|
178 |
|
|
Minimum Data Path: AVR_Core_cm4_Inst/IORegs_Inst/rampz_4 to AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1_4
|
179 |
|
|
Location Delay type Delay(ns) Physical Resource
|
180 |
|
|
Logical Resource(s)
|
181 |
|
|
------------------------------------------------- -------------------
|
182 |
|
|
SLICE_X13Y76.BQ Tcko 0.300 AVR_Core_cm4_Inst/IORegs_Inst/rampz<6>
|
183 |
|
|
AVR_Core_cm4_Inst/IORegs_Inst/rampz_4
|
184 |
|
|
SLICE_X12Y76.AX net (fanout=1) 0.115 AVR_Core_cm4_Inst/IORegs_Inst/rampz<4>
|
185 |
|
|
SLICE_X12Y76.CLK Tckdi (-Th) 0.173 AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1<7>
|
186 |
|
|
AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1_4
|
187 |
|
|
------------------------------------------------- ---------------------------
|
188 |
|
|
Total 0.242ns (0.127ns logic, 0.115ns route)
|
189 |
|
|
(52.5% logic, 47.5% route)
|
190 |
|
|
|
191 |
|
|
--------------------------------------------------------------------------------
|
192 |
|
|
Slack (hold path): 0.236ns (requirement - (clock path skew + uncertainty - data path))
|
193 |
|
|
Source: AVR_Core_cm4_Inst/IORegs_Inst/rampz_6 (FF)
|
194 |
|
|
Destination: AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1_6 (FF)
|
195 |
|
|
Requirement: 0.000ns
|
196 |
|
|
Data Path Delay: 0.245ns (Levels of Logic = 0)
|
197 |
|
|
Clock Path Skew: 0.009ns (0.122 - 0.113)
|
198 |
|
|
Source Clock: cp2_BUFGP rising at 3.000ns
|
199 |
|
|
Destination Clock: cp2_BUFGP rising at 3.000ns
|
200 |
|
|
Clock Uncertainty: 0.000ns
|
201 |
|
|
|
202 |
|
|
Minimum Data Path: AVR_Core_cm4_Inst/IORegs_Inst/rampz_6 to AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1_6
|
203 |
|
|
Location Delay type Delay(ns) Physical Resource
|
204 |
|
|
Logical Resource(s)
|
205 |
|
|
------------------------------------------------- -------------------
|
206 |
|
|
SLICE_X13Y76.DQ Tcko 0.300 AVR_Core_cm4_Inst/IORegs_Inst/rampz<6>
|
207 |
|
|
AVR_Core_cm4_Inst/IORegs_Inst/rampz_6
|
208 |
|
|
SLICE_X12Y76.CX net (fanout=1) 0.115 AVR_Core_cm4_Inst/IORegs_Inst/rampz<6>
|
209 |
|
|
SLICE_X12Y76.CLK Tckdi (-Th) 0.170 AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1<7>
|
210 |
|
|
AVR_Core_cm4_Inst/IORegs_Inst/rampz_cml_1_6
|
211 |
|
|
------------------------------------------------- ---------------------------
|
212 |
|
|
Total 0.245ns (0.130ns logic, 0.115ns route)
|
213 |
|
|
(53.1% logic, 46.9% route)
|
214 |
|
|
|
215 |
|
|
--------------------------------------------------------------------------------
|
216 |
|
|
Slack (hold path): 0.312ns (requirement - (clock path skew + uncertainty - data path))
|
217 |
|
|
Source: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_0 (FF)
|
218 |
|
|
Destination: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_cml_1_0 (FF)
|
219 |
|
|
Requirement: 0.000ns
|
220 |
|
|
Data Path Delay: 0.358ns (Levels of Logic = 0)
|
221 |
|
|
Clock Path Skew: 0.046ns (0.508 - 0.462)
|
222 |
|
|
Source Clock: cp2_BUFGP rising at 3.000ns
|
223 |
|
|
Destination Clock: cp2_BUFGP rising at 3.000ns
|
224 |
|
|
Clock Uncertainty: 0.000ns
|
225 |
|
|
|
226 |
|
|
Minimum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_0 to AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_cml_1_0
|
227 |
|
|
Location Delay type Delay(ns) Physical Resource
|
228 |
|
|
Logical Resource(s)
|
229 |
|
|
------------------------------------------------- -------------------
|
230 |
|
|
SLICE_X7Y47.AQ Tcko 0.300 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp<3>
|
231 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_0
|
232 |
|
|
SLICE_X4Y46.DX net (fanout=1) 0.228 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp<0>
|
233 |
|
|
SLICE_X4Y46.CLK Tckdi (-Th) 0.170 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_cml_1<0>
|
234 |
|
|
AVR_Core_cm4_Inst/pm_fetch_dec_Inst/cbi_sbi_io_adr_tmp_cml_1_0
|
235 |
|
|
------------------------------------------------- ---------------------------
|
236 |
|
|
Total 0.358ns (0.130ns logic, 0.228ns route)
|
237 |
|
|
(36.3% logic, 63.7% route)
|
238 |
|
|
|
239 |
|
|
--------------------------------------------------------------------------------
|
240 |
|
|
|
241 |
|
|
Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 3 ns HIGH 50%;
|
242 |
|
|
--------------------------------------------------------------------------------
|
243 |
|
|
Slack: 1.800ns (period - (min low pulse limit / (low pulse / period)))
|
244 |
|
|
Period: 3.000ns
|
245 |
|
|
Low pulse: 1.500ns
|
246 |
|
|
Low pulse limit: 0.600ns (Twpl)
|
247 |
|
|
Physical resource: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_24_3/CLK
|
248 |
|
|
Logical resource: AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_24_0/CLK
|
249 |
|
|
Location pin: SLICE_X0Y5.CLK
|
250 |
|
|
Clock network: cp2_BUFGP
|
251 |
|
|
--------------------------------------------------------------------------------
|
252 |
|
|
Slack: 1.800ns (period - (min high pulse limit / (high pulse / period)))
|
253 |
|
|
Period: 3.000ns
|
254 |
|
|
High pulse: 1.500ns
|
255 |
|
|
High pulse limit: 0.600ns (Twph)
|
256 |
|
|
Physical resource: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_24_3/CLK
|
257 |
|
|
Logical resource: AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_24_0/CLK
|
258 |
|
|
Location pin: SLICE_X0Y5.CLK
|
259 |
|
|
Clock network: cp2_BUFGP
|
260 |
|
|
--------------------------------------------------------------------------------
|
261 |
|
|
Slack: 1.800ns (period - (min low pulse limit / (low pulse / period)))
|
262 |
|
|
Period: 3.000ns
|
263 |
|
|
Low pulse: 1.500ns
|
264 |
|
|
Low pulse limit: 0.600ns (Twpl)
|
265 |
|
|
Physical resource: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_24_3/CLK
|
266 |
|
|
Logical resource: AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_24_1/CLK
|
267 |
|
|
Location pin: SLICE_X0Y5.CLK
|
268 |
|
|
Clock network: cp2_BUFGP
|
269 |
|
|
--------------------------------------------------------------------------------
|
270 |
|
|
|
271 |
|
|
|
272 |
|
|
1 constraint not met.
|
273 |
|
|
|
274 |
|
|
|
275 |
|
|
Data Sheet report:
|
276 |
|
|
-----------------
|
277 |
|
|
All values displayed in nanoseconds (ns)
|
278 |
|
|
|
279 |
|
|
Clock to Setup on destination clock cp2
|
280 |
|
|
---------------+---------+---------+---------+---------+
|
281 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
282 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
283 |
|
|
---------------+---------+---------+---------+---------+
|
284 |
|
|
cp2 | 4.064| | | |
|
285 |
|
|
---------------+---------+---------+---------+---------+
|
286 |
|
|
|
287 |
|
|
|
288 |
|
|
Timing summary:
|
289 |
|
|
---------------
|
290 |
|
|
|
291 |
|
|
Timing errors: 564 Score: 211258 (Setup/Max: 211258, Hold: 0)
|
292 |
|
|
|
293 |
|
|
Constraints cover 47967 paths, 0 nets, and 10466 connections
|
294 |
|
|
|
295 |
|
|
Design statistics:
|
296 |
|
|
Minimum period: 4.064ns{1} (Maximum frequency: 246.063MHz)
|
297 |
|
|
|
298 |
|
|
|
299 |
|
|
------------------------------------Footnotes-----------------------------------
|
300 |
|
|
1) The minimum period statistic assumes all single cycle delays.
|
301 |
|
|
|
302 |
|
|
Analysis completed Sun Oct 03 22:09:03 2010
|
303 |
|
|
--------------------------------------------------------------------------------
|
304 |
|
|
|
305 |
|
|
Trace Settings:
|
306 |
|
|
-------------------------
|
307 |
|
|
Trace Settings
|
308 |
|
|
|
309 |
|
|
Peak Memory Usage: 279 MB
|
310 |
|
|
|
311 |
|
|
|
312 |
|
|
|