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tobil |
--************************************************************************************************
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-- ALU(internal module) for AVR core
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-- Version 1.2
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-- Designed by Ruslan Lepetenok
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-- Modified 02.08.2003
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-- (CPC/SBC/SBCI Z-flag bug found)
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-- H-flag with NEG instruction found
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--************************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity alu_avr_cm2 is port(
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cp2_cml_1 : in std_logic;
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alu_data_r_in : in std_logic_vector(7 downto 0);
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alu_data_d_in : in std_logic_vector(7 downto 0);
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alu_c_flag_in : in std_logic;
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alu_z_flag_in : in std_logic;
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-- OPERATION SIGNALS INPUTS
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idc_add :in std_logic;
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idc_adc :in std_logic;
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idc_adiw :in std_logic;
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idc_sub :in std_logic;
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idc_subi :in std_logic;
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idc_sbc :in std_logic;
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idc_sbci :in std_logic;
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idc_sbiw :in std_logic;
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adiw_st : in std_logic;
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sbiw_st : in std_logic;
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idc_and :in std_logic;
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idc_andi :in std_logic;
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idc_or :in std_logic;
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idc_ori :in std_logic;
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idc_eor :in std_logic;
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idc_com :in std_logic;
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idc_neg :in std_logic;
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idc_inc :in std_logic;
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idc_dec :in std_logic;
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idc_cp :in std_logic;
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idc_cpc :in std_logic;
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idc_cpi :in std_logic;
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idc_cpse :in std_logic;
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idc_lsr :in std_logic;
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idc_ror :in std_logic;
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idc_asr :in std_logic;
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idc_swap :in std_logic;
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-- DATA OUTPUT
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alu_data_out : out std_logic_vector(7 downto 0);
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-- FLAGS OUTPUT
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alu_c_flag_out : out std_logic;
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alu_z_flag_out : out std_logic;
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alu_n_flag_out : out std_logic;
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alu_v_flag_out : out std_logic;
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alu_s_flag_out : out std_logic;
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alu_h_flag_out : out std_logic
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);
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end alu_avr_cm2;
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architecture rtl of alu_avr_cm2 is
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-- ####################################################
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-- INTERNAL SIGNALS
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-- ####################################################
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signal alu_data_out_int : std_logic_vector (7 downto 0);
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-- ALU FLAGS (INTERNAL)
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signal alu_z_flag_out_int : std_logic;
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signal alu_c_flag_in_int : std_logic; -- INTERNAL CARRY FLAG
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signal alu_n_flag_out_int : std_logic;
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signal alu_v_flag_out_int : std_logic;
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signal alu_c_flag_out_int : std_logic;
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-- ADDER SIGNALS --
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signal adder_nadd_sub : std_logic; -- 0 -> ADD ,1 -> SUB
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signal adder_v_flag_out : std_logic;
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signal adder_carry : std_logic_vector(8 downto 0);
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signal adder_d_in : std_logic_vector(8 downto 0);
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signal adder_r_in : std_logic_vector(8 downto 0);
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signal adder_out : std_logic_vector(8 downto 0);
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-- NEG OPERATOR SIGNALS
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signal neg_op_in : std_logic_vector(7 downto 0);
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signal neg_op_carry : std_logic_vector(8 downto 0);
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signal neg_op_out : std_logic_vector(8 downto 0);
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-- INC, DEC OPERATOR SIGNALS
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signal incdec_op_in : std_logic_vector (7 downto 0);
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signal incdec_op_carry : std_logic_vector(7 downto 0);
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signal incdec_op_out : std_logic_vector(7 downto 0);
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signal com_op_out : std_logic_vector(7 downto 0);
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signal and_op_out : std_logic_vector(7 downto 0);
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signal or_op_out : std_logic_vector(7 downto 0);
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signal eor_op_out : std_logic_vector(7 downto 0);
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-- SHIFT SIGNALS
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signal right_shift_out : std_logic_vector(7 downto 0);
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-- SWAP SIGNALS
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signal swap_out : std_logic_vector(7 downto 0);
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signal alu_data_r_in_cml_1 : std_logic_vector ( 7 downto 0 );
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signal alu_data_d_in_cml_1 : std_logic_vector ( 7 downto 0 );
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signal alu_z_flag_out_cml_out : std_logic;
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signal alu_z_flag_in_cml_1 : std_logic;
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signal alu_h_flag_out_cml_out : std_logic;
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signal idc_add_cml_1 : std_logic;
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signal idc_adc_cml_1 : std_logic;
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signal idc_adiw_cml_1 : std_logic;
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signal idc_sub_cml_1 : std_logic;
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signal idc_subi_cml_1 : std_logic;
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signal idc_sbc_cml_1 : std_logic;
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signal idc_sbci_cml_1 : std_logic;
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signal idc_sbiw_cml_1 : std_logic;
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signal adiw_st_cml_1 : std_logic;
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signal sbiw_st_cml_1 : std_logic;
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signal idc_and_cml_1 : std_logic;
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signal idc_andi_cml_1 : std_logic;
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signal idc_or_cml_1 : std_logic;
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signal idc_ori_cml_1 : std_logic;
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signal idc_eor_cml_1 : std_logic;
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signal idc_com_cml_1 : std_logic;
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signal idc_neg_cml_1 : std_logic;
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signal idc_inc_cml_1 : std_logic;
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signal idc_dec_cml_1 : std_logic;
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signal idc_cp_cml_1 : std_logic;
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signal idc_cpc_cml_1 : std_logic;
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signal idc_cpi_cml_1 : std_logic;
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signal idc_cpse_cml_1 : std_logic;
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signal idc_lsr_cml_1 : std_logic;
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signal idc_ror_cml_1 : std_logic;
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signal idc_asr_cml_1 : std_logic;
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signal idc_swap_cml_1 : std_logic;
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signal alu_c_flag_in_int_cml_1 : std_logic;
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signal adder_nadd_sub_cml_1 : std_logic;
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signal adder_d_in_cml_1 : std_logic_vector ( 8 downto 0 );
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signal adder_r_in_cml_1 : std_logic_vector ( 8 downto 0 );
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signal right_shift_out_cml_1 : std_logic_vector ( 7 downto 0 );
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signal swap_out_cml_1 : std_logic_vector ( 7 downto 0 );
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begin
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process(cp2_cml_1) begin
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if (cp2_cml_1 = '1' and cp2_cml_1'event) then
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alu_data_r_in_cml_1 <= alu_data_r_in;
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alu_data_d_in_cml_1 <= alu_data_d_in;
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alu_z_flag_in_cml_1 <= alu_z_flag_in;
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idc_add_cml_1 <= idc_add;
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idc_adc_cml_1 <= idc_adc;
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idc_adiw_cml_1 <= idc_adiw;
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idc_sub_cml_1 <= idc_sub;
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idc_subi_cml_1 <= idc_subi;
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idc_sbc_cml_1 <= idc_sbc;
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idc_sbci_cml_1 <= idc_sbci;
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idc_sbiw_cml_1 <= idc_sbiw;
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adiw_st_cml_1 <= adiw_st;
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sbiw_st_cml_1 <= sbiw_st;
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idc_and_cml_1 <= idc_and;
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idc_andi_cml_1 <= idc_andi;
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idc_or_cml_1 <= idc_or;
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idc_ori_cml_1 <= idc_ori;
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idc_eor_cml_1 <= idc_eor;
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idc_com_cml_1 <= idc_com;
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idc_neg_cml_1 <= idc_neg;
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idc_inc_cml_1 <= idc_inc;
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idc_dec_cml_1 <= idc_dec;
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idc_cp_cml_1 <= idc_cp;
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idc_cpc_cml_1 <= idc_cpc;
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idc_cpi_cml_1 <= idc_cpi;
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idc_cpse_cml_1 <= idc_cpse;
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idc_lsr_cml_1 <= idc_lsr;
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idc_ror_cml_1 <= idc_ror;
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idc_asr_cml_1 <= idc_asr;
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idc_swap_cml_1 <= idc_swap;
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alu_c_flag_in_int_cml_1 <= alu_c_flag_in_int;
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adder_nadd_sub_cml_1 <= adder_nadd_sub;
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adder_d_in_cml_1 <= adder_d_in;
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adder_r_in_cml_1 <= adder_r_in;
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right_shift_out_cml_1 <= right_shift_out;
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swap_out_cml_1 <= swap_out;
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end if;
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end process;
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alu_z_flag_out <= alu_z_flag_out_cml_out;
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alu_h_flag_out <= alu_h_flag_out_cml_out;
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-- ########################################################################
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-- ############### ALU
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-- ########################################################################
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adder_nadd_sub <=(idc_sub or idc_subi or idc_sbc or idc_sbci or idc_sbiw or sbiw_st or
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idc_cp or idc_cpc or idc_cpi or idc_cpse ); -- '0' -> '+'; '1' -> '-'
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-- SREG C FLAG (ALU INPUT)
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alu_c_flag_in_int <= alu_c_flag_in and
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(idc_adc or adiw_st or idc_sbc or idc_sbci or sbiw_st or
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idc_cpc or
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idc_ror);
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-- SynEDA CoreMultiplier
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-- assignment(s): alu_z_flag_out
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-- replace(s): alu_z_flag_in, idc_sbc, idc_sbci, adiw_st, sbiw_st, idc_cpc
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-- SREG Z FLAG ()
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-- alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st)) or
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-- ((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st));
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alu_z_flag_out_cml_out <= (alu_z_flag_out_int and not(adiw_st_cml_1 or sbiw_st_cml_1 or idc_cpc_cml_1 or idc_sbc_cml_1 or idc_sbci_cml_1)) or
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((alu_z_flag_in_cml_1 and alu_z_flag_out_int) and (adiw_st_cml_1 or sbiw_st_cml_1))or
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(alu_z_flag_in_cml_1 and alu_z_flag_out_int and(idc_cpc_cml_1 or idc_sbc_cml_1 or idc_sbci_cml_1)); -- Previous value (for CPC/SBC/SBCI instructions)
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-- SREG N FLAG
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alu_n_flag_out <= alu_n_flag_out_int;
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-- SREG V FLAG
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alu_v_flag_out <= alu_v_flag_out_int;
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alu_c_flag_out <= alu_c_flag_out_int;
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alu_data_out <= alu_data_out_int;
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-- #########################################################################################
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adder_d_in <= '0'&alu_data_d_in;
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adder_r_in <= '0'&alu_data_r_in;
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--########################## ADDEER ###################################
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adder_out(0) <= adder_d_in_cml_1(0) xor adder_r_in_cml_1(0) xor alu_c_flag_in_int_cml_1;
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summator:for i in 1 to 8 generate
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-- SynEDA CoreMultiplier
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-- assignment(s): adder_out
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-- replace(s): alu_c_flag_in_int, adder_d_in, adder_r_in
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adder_out(i) <= adder_d_in_cml_1(i) xor adder_r_in_cml_1(i) xor adder_carry(i-1);
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end generate;
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adder_carry(0) <= ((adder_d_in_cml_1(0) xor adder_nadd_sub_cml_1) and adder_r_in_cml_1(0)) or
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(((adder_d_in_cml_1(0) xor adder_nadd_sub_cml_1) or adder_r_in_cml_1(0)) and alu_c_flag_in_int_cml_1);
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summator2:for i in 1 to 8 generate
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-- SynEDA CoreMultiplier
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-- assignment(s): adder_carry
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-- replace(s): alu_c_flag_in_int, adder_nadd_sub, adder_d_in, adder_r_in
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adder_carry(i) <= ((adder_d_in_cml_1(i) xor adder_nadd_sub_cml_1) and adder_r_in_cml_1(i)) or
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(((adder_d_in_cml_1(i) xor adder_nadd_sub_cml_1) or adder_r_in_cml_1(i)) and adder_carry(i-1));
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end generate;
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-- FLAGS FOR ADDER INSTRUCTIONS:
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-- CARRY FLAG (C) -> adder_out(8)
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-- HALF CARRY FLAG (H) -> adder_carry(3)
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-- TOW'S COMPLEMENT OVERFLOW (V) ->
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-- SynEDA CoreMultiplier
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-- assignment(s): adder_v_flag_out
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-- replace(s): adder_nadd_sub, adder_d_in, adder_r_in
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adder_v_flag_out <= (((adder_d_in_cml_1(7) and adder_r_in_cml_1(7) and not adder_out(7)) or
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(not adder_d_in_cml_1(7) and not adder_r_in_cml_1(7) and adder_out(7))) and not adder_nadd_sub_cml_1) or -- ADD
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(((adder_d_in_cml_1(7) and not adder_r_in_cml_1(7) and not adder_out(7)) or
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(not adder_d_in_cml_1(7) and adder_r_in_cml_1(7) and adder_out(7))) and adder_nadd_sub_cml_1);
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-- SUB
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--#####################################################################
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-- LOGICAL OPERATIONS FOR ONE OPERAND
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--########################## NEG OPERATION ####################
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294 |
|
|
|
295 |
|
|
neg_op_out(0) <= not alu_data_d_in_cml_1(0) xor '1';
|
296 |
|
|
neg_op:for i in 1 to 7 generate
|
297 |
|
|
neg_op_out(i) <= not alu_data_d_in_cml_1(i) xor neg_op_carry(i-1);
|
298 |
|
|
end generate;
|
299 |
|
|
-- SynEDA CoreMultiplier
|
300 |
|
|
-- assignment(s): neg_op_out
|
301 |
|
|
-- replace(s): alu_data_d_in
|
302 |
|
|
|
303 |
|
|
neg_op_out(8) <= neg_op_carry(7) xor '1';
|
304 |
|
|
|
305 |
|
|
|
306 |
|
|
neg_op_carry(0) <= not alu_data_d_in_cml_1(0) and '1';
|
307 |
|
|
neg_op2:for i in 1 to 7 generate
|
308 |
|
|
neg_op_carry(i) <= not alu_data_d_in_cml_1(i) and neg_op_carry(i-1);
|
309 |
|
|
end generate;
|
310 |
|
|
-- SynEDA CoreMultiplier
|
311 |
|
|
-- assignment(s): neg_op_carry
|
312 |
|
|
-- replace(s): alu_data_d_in
|
313 |
|
|
|
314 |
|
|
neg_op_carry(8) <= neg_op_carry(7); -- ??!!
|
315 |
|
|
|
316 |
|
|
|
317 |
|
|
-- CARRY FLAGS FOR NEG INSTRUCTION:
|
318 |
|
|
-- CARRY FLAG -> neg_op_out(8)
|
319 |
|
|
-- HALF CARRY FLAG -> neg_op_carry(3)
|
320 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG -> alu_data_d_in(7) and neg_op_carry(6)
|
321 |
|
|
--############################################################################
|
322 |
|
|
|
323 |
|
|
|
324 |
|
|
--########################## INC, DEC OPERATIONS ####################
|
325 |
|
|
|
326 |
|
|
incdec_op_out(0) <= alu_data_d_in_cml_1(0) xor '1';
|
327 |
|
|
inc_dec:for i in 1 to 7 generate
|
328 |
|
|
-- SynEDA CoreMultiplier
|
329 |
|
|
-- assignment(s): incdec_op_out
|
330 |
|
|
-- replace(s): alu_data_d_in
|
331 |
|
|
|
332 |
|
|
incdec_op_out(i) <= alu_data_d_in_cml_1(i) xor incdec_op_carry(i-1);
|
333 |
|
|
end generate;
|
334 |
|
|
|
335 |
|
|
|
336 |
|
|
incdec_op_carry(0) <= alu_data_d_in_cml_1(0) xor idc_dec_cml_1;
|
337 |
|
|
inc_dec2:for i in 1 to 7 generate
|
338 |
|
|
-- SynEDA CoreMultiplier
|
339 |
|
|
-- assignment(s): incdec_op_carry
|
340 |
|
|
-- replace(s): alu_data_d_in, idc_dec
|
341 |
|
|
|
342 |
|
|
incdec_op_carry(i) <= (alu_data_d_in_cml_1(i) xor idc_dec_cml_1) and incdec_op_carry(i-1);
|
343 |
|
|
end generate;
|
344 |
|
|
|
345 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG -> (alu_data_d_in(7) xor idc_dec) and incdec_op_carry(6)
|
346 |
|
|
--####################################################################
|
347 |
|
|
|
348 |
|
|
|
349 |
|
|
-- SynEDA CoreMultiplier
|
350 |
|
|
-- assignment(s): com_op_out
|
351 |
|
|
-- replace(s): alu_data_d_in
|
352 |
|
|
|
353 |
|
|
--########################## COM OPERATION ###################################
|
354 |
|
|
com_op_out <= not alu_data_d_in_cml_1;
|
355 |
|
|
-- FLAGS
|
356 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
|
357 |
|
|
-- CARRY FLAG (C) -> '1'
|
358 |
|
|
--############################################################################
|
359 |
|
|
|
360 |
|
|
-- LOGICAL OPERATIONS FOR TWO OPERANDS
|
361 |
|
|
|
362 |
|
|
-- SynEDA CoreMultiplier
|
363 |
|
|
-- assignment(s): and_op_out
|
364 |
|
|
-- replace(s): alu_data_r_in, alu_data_d_in
|
365 |
|
|
|
366 |
|
|
--########################## AND OPERATION ###################################
|
367 |
|
|
and_op_out <= alu_data_d_in_cml_1 and alu_data_r_in_cml_1;
|
368 |
|
|
-- FLAGS
|
369 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
|
370 |
|
|
--############################################################################
|
371 |
|
|
|
372 |
|
|
-- SynEDA CoreMultiplier
|
373 |
|
|
-- assignment(s): or_op_out
|
374 |
|
|
-- replace(s): alu_data_r_in, alu_data_d_in
|
375 |
|
|
|
376 |
|
|
--########################## OR OPERATION ###################################
|
377 |
|
|
or_op_out <= alu_data_d_in_cml_1 or alu_data_r_in_cml_1;
|
378 |
|
|
-- FLAGS
|
379 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
|
380 |
|
|
--############################################################################
|
381 |
|
|
|
382 |
|
|
-- SynEDA CoreMultiplier
|
383 |
|
|
-- assignment(s): eor_op_out
|
384 |
|
|
-- replace(s): alu_data_r_in, alu_data_d_in
|
385 |
|
|
|
386 |
|
|
--########################## EOR OPERATION ###################################
|
387 |
|
|
eor_op_out <= alu_data_d_in_cml_1 xor alu_data_r_in_cml_1;
|
388 |
|
|
-- FLAGS
|
389 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
|
390 |
|
|
--############################################################################
|
391 |
|
|
|
392 |
|
|
-- SHIFT OPERATIONS
|
393 |
|
|
|
394 |
|
|
-- ########################## RIGHT(LSR, ROR, ASR) #######################
|
395 |
|
|
|
396 |
|
|
right_shift_out(7) <= (idc_ror and alu_c_flag_in_int) or (idc_asr and alu_data_d_in(7)); -- right_shift_out(7)
|
397 |
|
|
shift_right:for i in 6 downto 0 generate
|
398 |
|
|
right_shift_out(i) <= alu_data_d_in(i+1);
|
399 |
|
|
end generate;
|
400 |
|
|
|
401 |
|
|
-- FLAGS
|
402 |
|
|
-- CARRY FLAG (C) -> alu_data_d_in(0)
|
403 |
|
|
-- NEGATIVE FLAG (N) -> right_shift_out(7)
|
404 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> N xor C (left_shift_out(7) xor alu_data_d_in(0))
|
405 |
|
|
|
406 |
|
|
-- #######################################################################
|
407 |
|
|
|
408 |
|
|
|
409 |
|
|
-- ################################## SWAP ###############################
|
410 |
|
|
|
411 |
|
|
swap_h:for i in 7 downto 4 generate
|
412 |
|
|
swap_out(i) <= alu_data_d_in(i-4);
|
413 |
|
|
end generate;
|
414 |
|
|
swap_l:for i in 3 downto 0 generate
|
415 |
|
|
swap_out(i) <= alu_data_d_in(i+4);
|
416 |
|
|
end generate;
|
417 |
|
|
-- #######################################################################
|
418 |
|
|
|
419 |
|
|
-- ALU OUTPUT MUX
|
420 |
|
|
|
421 |
|
|
alu_data_out_mux:for i in alu_data_out_int'range generate
|
422 |
|
|
-- SynEDA CoreMultiplier
|
423 |
|
|
-- assignment(s): alu_data_out_int
|
424 |
|
|
-- replace(s): idc_add, idc_adc, idc_adiw, idc_sub, idc_subi, idc_sbc, idc_sbci, idc_sbiw, adiw_st, sbiw_st, idc_and, idc_andi, idc_or, idc_ori, idc_eor, idc_com, idc_neg, idc_inc, idc_dec, idc_cp, idc_cpc, idc_cpi, idc_cpse, idc_lsr, idc_ror, idc_asr, idc_swap, right_shift_out, swap_out
|
425 |
|
|
|
426 |
|
|
alu_data_out_int(i) <= (adder_out(i) and (idc_add_cml_1 or idc_adc_cml_1 or (idc_adiw_cml_1 or adiw_st_cml_1) or -- !!!!!
|
427 |
|
|
idc_sub_cml_1 or idc_subi_cml_1 or idc_sbc_cml_1 or idc_sbci_cml_1 or
|
428 |
|
|
(idc_sbiw_cml_1 or sbiw_st_cml_1) or -- !!!!!
|
429 |
|
|
idc_cpse_cml_1 or idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1)) or
|
430 |
|
|
(neg_op_out(i) and idc_neg_cml_1) or -- NEG
|
431 |
|
|
(incdec_op_out(i) and (idc_inc_cml_1 or idc_dec_cml_1)) or -- INC/DEC
|
432 |
|
|
(com_op_out(i) and idc_com_cml_1) or -- COM
|
433 |
|
|
(and_op_out(i) and (idc_and_cml_1 or idc_andi_cml_1)) or -- AND/ANDI
|
434 |
|
|
(or_op_out(i) and (idc_or_cml_1 or idc_ori_cml_1)) or -- OR/ORI
|
435 |
|
|
(eor_op_out(i) and idc_eor_cml_1) or -- EOR
|
436 |
|
|
(right_shift_out_cml_1(i) and (idc_lsr_cml_1 or idc_ror_cml_1 or idc_asr_cml_1)) or -- LSR/ROR/ASR
|
437 |
|
|
(swap_out_cml_1(i) and idc_swap_cml_1); -- SWAP
|
438 |
|
|
|
439 |
|
|
|
440 |
|
|
end generate;
|
441 |
|
|
|
442 |
|
|
--@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ALU FLAGS OUTPUTS @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
|
443 |
|
|
|
444 |
|
|
-- SynEDA CoreMultiplier
|
445 |
|
|
-- assignment(s): alu_h_flag_out
|
446 |
|
|
-- replace(s): idc_add, idc_adc, idc_sub, idc_subi, idc_sbc, idc_sbci, idc_neg, idc_cp, idc_cpc, idc_cpi
|
447 |
|
|
|
448 |
|
|
alu_h_flag_out_cml_out <= (adder_carry(3) and -- ADDER INSTRUCTIONS
|
449 |
|
|
(idc_add_cml_1 or idc_adc_cml_1 or idc_sub_cml_1 or idc_subi_cml_1 or idc_sbc_cml_1 or idc_sbci_cml_1 or idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1)) or
|
450 |
|
|
(not neg_op_carry(3) and idc_neg_cml_1); -- H-flag problem with NEG instruction fixing -- NEG
|
451 |
|
|
|
452 |
|
|
|
453 |
|
|
alu_s_flag_out <= alu_n_flag_out_int xor alu_v_flag_out_int;
|
454 |
|
|
|
455 |
|
|
-- SynEDA CoreMultiplier
|
456 |
|
|
-- assignment(s): alu_v_flag_out_int
|
457 |
|
|
-- replace(s): alu_data_d_in, idc_add, idc_adc, idc_sub, idc_subi, idc_sbc, idc_sbci, adiw_st, sbiw_st, idc_neg, idc_inc, idc_dec, idc_cp, idc_cpc, idc_cpi, idc_lsr, idc_ror, idc_asr
|
458 |
|
|
|
459 |
|
|
alu_v_flag_out_int <= (adder_v_flag_out and
|
460 |
|
|
(idc_add_cml_1 or idc_adc_cml_1 or idc_sub_cml_1 or idc_subi_cml_1 or idc_sbc_cml_1 or idc_sbci_cml_1 or adiw_st_cml_1 or sbiw_st_cml_1 or idc_cp_cml_1 or idc_cpi_cml_1 or idc_cpc_cml_1)) or
|
461 |
|
|
((alu_data_d_in_cml_1(7) and neg_op_carry(6)) and idc_neg_cml_1) or -- NEG
|
462 |
|
|
(not alu_data_d_in_cml_1(7) and incdec_op_carry(6) and idc_inc_cml_1) or -- INC
|
463 |
|
|
(alu_data_d_in_cml_1(7) and incdec_op_carry(6) and idc_dec_cml_1) or -- DEC
|
464 |
|
|
((alu_n_flag_out_int xor alu_c_flag_out_int) and (idc_lsr_cml_1 or idc_ror_cml_1 or idc_asr_cml_1)); -- LSR,ROR,ASR
|
465 |
|
|
|
466 |
|
|
|
467 |
|
|
alu_n_flag_out_int <= alu_data_out_int(7);
|
468 |
|
|
|
469 |
|
|
alu_z_flag_out_int <= '1' when alu_data_out_int="00000000" else '0';
|
470 |
|
|
|
471 |
|
|
-- SynEDA CoreMultiplier
|
472 |
|
|
-- assignment(s): alu_c_flag_out_int
|
473 |
|
|
-- replace(s): alu_data_d_in, idc_add, idc_adc, idc_adiw, idc_sub, idc_subi, idc_sbc, idc_sbci, idc_sbiw, adiw_st, sbiw_st, idc_com, idc_neg, idc_cp, idc_cpc, idc_cpi, idc_lsr, idc_ror, idc_asr
|
474 |
|
|
|
475 |
|
|
alu_c_flag_out_int <= (adder_out(8) and
|
476 |
|
|
(idc_add_cml_1 or idc_adc_cml_1 or (idc_adiw_cml_1 or adiw_st_cml_1) or idc_sub_cml_1 or idc_subi_cml_1 or idc_sbc_cml_1 or idc_sbci_cml_1 or (idc_sbiw_cml_1 or sbiw_st_cml_1) or idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1)) or -- ADDER
|
477 |
|
|
(not alu_z_flag_out_int and idc_neg_cml_1) or -- NEG
|
478 |
|
|
(alu_data_d_in_cml_1(0) and (idc_lsr_cml_1 or idc_ror_cml_1 or idc_asr_cml_1)) or idc_com_cml_1;
|
479 |
|
|
|
480 |
|
|
-- @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
|
481 |
|
|
|
482 |
|
|
|
483 |
|
|
end rtl;
|