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[/] [avr_hp/] [trunk/] [rtl/] [rtl_s3_cm2/] [pm_fetch_dec.vhd] - Blame information for rev 2

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1 2 tobil 
--************************************************************************************************
2 
--  PM_FETCH_DEC(internal module) for AVR core
3 
--      Version 2.6! (Special version for the JTAG OCD)
4 
--  Designed by Ruslan Lepetenok 14.11.2001
5 
--  Modified 31.05.06
6 
--  Modification:
7 
--  Registered ramre/ramwe outputs
8 
--  cpu_busy logic modified(affects RCALL/ICALL/CALL instruction interract with interrupt)
9 
--  SLEEP and CLRWDT instructions support was added
10 
--  V-flag bug fixed (AND/ANDI/OR/ORI/EOR)
11 
--  V-flag bug fixed (ADIW/SBIW)
12 
--  Unused outputs(sreg_bit_num[2..0],idc_sbi_out,idc_cbi_out,idc_bld_out) were removed.
13 
--  Output alu_data_d_in[7..0] was removed.
14 
--  Gloabal clock enable(cp2en) was added
15 
--  cpu_busy(push/pop) + irq bug was fixed 14.07.05
16 
--  BRXX+IRQ interaction was modified -> cpu_busy
17 
--  LDS/STS now requires only two cycles for execution (13.01.06 -> last modificatioon)
18 
--************************************************************************************************
19 
 
20 
library IEEE;
21 
use IEEE.std_logic_1164.all;
22 
use IEEE.std_logic_unsigned.all;
23 
 
24 
use WORK.AVRuCPackage.all;
25 
 
26 
entity pm_fetch_dec_cm2 is port(
27 
                cp2_cml_1 : in std_logic;
28 
 
29 
                              -- Clock and reset
30 
                              cp2              : in  std_logic;
31 
                                                          cp2en            : in  std_logic;
32 
                              ireset           : in  std_logic;
33 
                                                          -- JTAG OCD support
34 
                                                          valid_instr      : out  std_logic;
35 
                                                      insert_nop       : in   std_logic;
36 
                                                      block_irq        : in   std_logic;
37 
                                                      change_flow      : out  std_logic;
38 
                                                          -- Program memory
39 
                              pc               : out std_logic_vector (15 downto 0);
40 
                              inst             : in  std_logic_vector (15 downto 0);
41 
                              -- I/O control
42 
                              adr              : out std_logic_vector (5 downto 0);
43 
                              iore             : out std_logic;
44 
                              iowe             : out std_logic;
45 
                              -- Data memory control
46 
                              ramadr           : out std_logic_vector (15 downto 0);
47 
                              ramre            : out std_logic;
48 
                              ramwe            : out std_logic;
49 
                              cpuwait          : in  std_logic;
50 
                                                          -- Data paths
51 
                              dbusin           : in  std_logic_vector (7 downto 0);
52 
                              dbusout          : out std_logic_vector (7 downto 0);
53 
                              dbusout_int_route : out std_logic_vector (7 downto 0);
54 
                              -- Interrupt
55 
                              irqlines         : in  std_logic_vector (22 downto 0);
56 
                              irqack           : out std_logic;
57 
                              irqackad         : out std_logic_vector(4 downto 0);
58 
                                                      --Sleep
59 
                              sleepi           : out std_logic;
60 
                              irqok                : out std_logic;
61 
                              --Watchdog
62 
                              wdri                 : out std_logic;
63 
                                                          -- ALU interface(Data inputs)
64 
                              alu_data_r_in    : out std_logic_vector(7 downto 0);
65 
                                                          -- ALU interface(Instruction inputs)
66 
                                                          idc_add_out      : out std_logic;
67 
                              idc_adc_out      : out std_logic;
68 
                              idc_adiw_out     : out std_logic;
69 
                              idc_sub_out      : out std_logic;
70 
                              idc_subi_out     : out std_logic;
71 
                              idc_sbc_out      : out std_logic;
72 
                              idc_sbci_out     : out std_logic;
73 
                              idc_sbiw_out     : out std_logic;
74 
 
75 
                              adiw_st_out      : out std_logic;
76 
                              sbiw_st_out      : out std_logic;
77 
 
78 
                              idc_and_out      : out std_logic;
79 
                              idc_andi_out     : out std_logic;
80 
                              idc_or_out       : out std_logic;
81 
                              idc_ori_out      : out std_logic;
82 
                              idc_eor_out      : out std_logic;
83 
                              idc_com_out      : out std_logic;
84 
                              idc_neg_out      : out std_logic;
85 
 
86 
                              idc_inc_out      : out std_logic;
87 
                              idc_dec_out      : out std_logic;
88 
 
89 
                              idc_cp_out       : out std_logic;
90 
                              idc_cpc_out      : out std_logic;
91 
                              idc_cpi_out      : out std_logic;
92 
                              idc_cpse_out     : out std_logic;
93 
 
94 
                              idc_lsr_out      : out std_logic;
95 
                              idc_ror_out      : out std_logic;
96 
                              idc_asr_out      : out std_logic;
97 
                              idc_swap_out     : out std_logic;
98 
 
99 
                               -- ALU interface(Data output)
100 
                               alu_data_out    : in std_logic_vector(7 downto 0);
101 
 
102 
                               -- ALU interface(Flag outputs)
103 
                               alu_c_flag_out  : in std_logic;
104 
                               alu_z_flag_out  : in std_logic;
105 
                               alu_n_flag_out  : in std_logic;
106 
                               alu_v_flag_out  : in std_logic;
107 
                               alu_s_flag_out  : in std_logic;
108 
                               alu_h_flag_out  : in std_logic;
109 
 
110 
                                                           -- General purpose register file interface
111 
                               reg_rd_in       : out std_logic_vector  (7 downto 0);
112 
                               reg_rd_out      : in  std_logic_vector  (7 downto 0);
113 
                               reg_rd_out_int  : in std_logic_vector(7 downto 0);
114 
                               reg_rd_adr      : out std_logic_vector  (4 downto 0);
115 
                               reg_rd_adr_int      : out std_logic_vector  (4 downto 0);
116 
                               reg_rr_out      : in  std_logic_vector  (7 downto 0);
117 
                               reg_rr_adr      : out std_logic_vector  (4 downto 0);
118 
                               reg_rd_wr       : out std_logic;
119 
 
120 
                               post_inc        : out std_logic;                       -- POST INCREMENT FOR LD/ST INSTRUCTIONS
121 
                               pre_dec         : out std_logic;                        -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
122 
                               reg_h_wr        : out std_logic;
123 
                               reg_h_out       : in  std_logic_vector (15 downto 0);
124 
                               reg_h_adr       : out std_logic_vector (2 downto 0);    -- x,y,z
125 
                                       reg_z_out       : in  std_logic_vector (15 downto 0);  -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
126 
 
127 
                               -- I/O register file interface
128 
                               sreg_fl_in      : out std_logic_vector(7 downto 0);
129 
                               globint         : in  std_logic; -- SREG I flag
130 
 
131 
                               sreg_fl_wr_en   : out std_logic_vector(7 downto 0);   --FLAGS WRITE ENABLE SIGNALS
132 
 
133 
                               spl_out         : in  std_logic_vector(7 downto 0);
134 
                               sph_out         : in  std_logic_vector(7 downto 0);
135 
                               sp_ndown_up     : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
136 
                               sp_en           : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
137 
 
138 
                               rampz_out       : in  std_logic_vector(7 downto 0);
139 
 
140 
                                                           -- Bit processor interface
141 
                               bit_num_r_io    : out std_logic_vector (2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS
142 
                               bitpr_io_out    : in  std_logic_vector(7 downto 0);  -- SBI/CBI OUT
143 
                               branch          : out std_logic_vector (2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION
144 
                               bit_pr_sreg_out : in  std_logic_vector(7 downto 0);  -- BCLR/BSET/BST(T-FLAG ONLY)
145 
                               bld_op_out      : in  std_logic_vector(7 downto 0);  -- BLD OUT (T FLAG)
146 
                               bit_test_op_out : in  std_logic;                     -- OUTPUT OF SBIC/SBIS/SBRS/SBRC
147 
 
148 
                               sbi_st_out      : out std_logic;
149 
                               cbi_st_out      : out std_logic;
150 
 
151 
                               idc_bst_out     : out std_logic;
152 
                               idc_bset_out    : out std_logic;
153 
                               idc_bclr_out    : out std_logic;
154 
 
155 
                               idc_sbic_out    : out std_logic;
156 
                               idc_sbis_out    : out std_logic;
157 
 
158 
                               idc_sbrs_out    : out std_logic;
159 
                               idc_sbrc_out    : out std_logic;
160 
 
161 
                               idc_brbs_out    : out std_logic;
162 
                               idc_brbc_out    : out std_logic;
163 
 
164 
                               idc_reti_out    : out std_logic);
165 
end pm_fetch_dec_cm2;
166 
 
167 
architecture RTL of pm_fetch_dec_cm2 is
168 
 
169 
-- COPIES OF OUTPUTS
170 
signal ramadr_reg_in  : std_logic_vector(15 downto 0); -- INPUT OF THE ADDRESS REGISTER
171 
signal ramadr_reg_en  : std_logic;                     -- ADRESS REGISTER CLOCK ENABLE SIGNAL
172 
 
173 
signal irqack_int     : std_logic;
174 
signal irqackad_int   : std_logic_vector(irqackad'range);
175 
 
176 
-- ####################################################
177 
-- INTERNAL SIGNALS
178 
-- ####################################################
179 
 
180 
-- NEW SIGNALS
181 
signal   two_word_inst       : std_logic;                    -- CALL/JMP/STS/LDS INSTRUCTION INDICATOR
182 
 
183 
signal   ram_adr_int         : std_logic_vector (15 downto 0);
184 
constant const_ram_to_reg    : std_logic_vector := "00000000000";  -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19
185 
constant const_ram_to_io_a   : std_logic_vector := "00000000001";  -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
186 
constant const_ram_to_io_b   : std_logic_vector := "00000000010";  -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
187 
 
188 
-- LD/LDD/ST/STD SIGNALS
189 
signal adiw_sbiw_encoder_out : std_logic_vector (4 downto 0);
190 
signal adiw_sbiw_encoder_mux_out : std_logic_vector (4 downto 0);
191 
 
192 
 
193 
-- PROGRAM COUNTER SIGNALS
194 
signal program_counter_tmp : std_logic_vector (15 downto 0); -- TO STORE PC DURING LPM/ELPM INSTRUCTIONS
195 
signal program_counter     : std_logic_vector (15 downto 0);
196 
signal program_counter_in  : std_logic_vector (15 downto 0);
197 
signal program_counter_high_fr  : std_logic_vector (7 downto 0); -- TO STORE PC FOR CALL,IRQ,RCALL,ICALL
198 
 
199 
signal pc_low       : std_logic_vector (7 downto 0);
200 
signal pc_high      : std_logic_vector (7 downto 0);
201 
 
202 
 
203 
signal pc_low_en       : std_logic;
204 
signal pc_high_en      : std_logic;
205 
 
206 
signal offset_brbx     : std_logic_vector (15 downto 0);    -- OFFSET FOR BRCS/BRCC   INSTRUCTION  !!CHECKED
207 
signal offset_rxx      : std_logic_vector (15 downto 0);    -- OFFSET FOR RJMP/RCALL  INSTRUCTION  !!CHECKED
208 
 
209 
signal pa15_pm         : std_logic; -- ADDRESS LINE 15 FOR LPM/ELPM INSTRUCTIONS ('0' FOR LPM,RAMPZ(0) FOR ELPM)
210 
 
211 
signal alu_reg_wr      : std_logic; -- ALU INSTRUCTIONS PRODUCING WRITE TO THE GENERAL PURPOSE REGISTER FILE
212 
 
213 
-- DATA MEMORY,GENERAL PURPOSE REGISTERS AND I/O REGISTERS LOGIC
214 
 
215 
--! IMPORTANT NOTICE : OPERATIONS WHICH USE STACK POINTER (SPH:SPL) CAN NOT ACCCSESS GENERAL
216 
-- PURPOSE REGISTER FILE AND INPUT/OUTPUT REGISTER FILE !
217 
-- THESE OPERATIONS ARE : RCALL/ICALL/CALL/RET/RETI/PUSH/POP INSTRUCTIONS  AND INTERRUPT
218 
 
219 
signal reg_file_adr_space  : std_logic; -- ACCSESS TO THE REGISTER FILE
220 
signal io_file_adr_space   : std_logic; -- ACCSESS TO THE I/O FILE
221 
 
222 
-- STATE MACHINES SIGNALS
223 
signal irq_start      : std_logic;
224 
 
225 
signal nirq_st0       : std_logic;
226 
signal irq_st1        : std_logic;
227 
signal irq_st2        : std_logic;
228 
signal irq_st3        : std_logic;
229 
 
230 
signal ncall_st0      : std_logic;
231 
signal call_st1       : std_logic;
232 
signal call_st2       : std_logic;
233 
signal call_st3       : std_logic;
234 
 
235 
signal nrcall_st0     : std_logic;
236 
signal rcall_st1      : std_logic;
237 
signal rcall_st2      : std_logic;
238 
 
239 
signal nicall_st0     : std_logic;
240 
signal icall_st1      : std_logic;
241 
signal icall_st2      : std_logic;
242 
 
243 
signal njmp_st0       : std_logic;
244 
signal jmp_st1        : std_logic;
245 
signal jmp_st2        : std_logic;
246 
 
247 
signal ijmp_st        : std_logic;
248 
 
249 
signal rjmp_st        : std_logic;
250 
 
251 
signal nret_st0       : std_logic;
252 
signal ret_st1        : std_logic;
253 
signal ret_st2        : std_logic;
254 
signal ret_st3        : std_logic;
255 
 
256 
signal nreti_st0      : std_logic;
257 
signal reti_st1       : std_logic;
258 
signal reti_st2       : std_logic;
259 
signal reti_st3       : std_logic;
260 
 
261 
signal brxx_st        : std_logic;  -- BRANCHES
262 
 
263 
signal adiw_st        : std_logic;
264 
signal sbiw_st        : std_logic;
265 
 
266 
signal nskip_inst_st0 : std_logic;
267 
signal skip_inst_st1  : std_logic;
268 
signal skip_inst_st2  : std_logic;  -- ALL SKIP INSTRUCTIONS SBRS/SBRC/SBIS/SBIC/CPSE
269 
 
270 
signal skip_inst_start  : std_logic;
271 
 
272 
signal nlpm_st0       : std_logic;
273 
signal lpm_st1        : std_logic;
274 
signal lpm_st2        : std_logic;
275 
 
276 
signal nelpm_st0      : std_logic;
277 
signal elpm_st1       : std_logic;
278 
signal elpm_st2       : std_logic;
279 
 
280 
--signal nsts_st0       : std_logic;
281 
--signal sts_st1        : std_logic;
282 
--signal sts_st2        : std_logic;
283 
 
284 
signal sts_st         : std_logic;
285 
 
286 
--signal nlds_st0       : std_logic;
287 
--signal lds_st1        : std_logic;
288 
--signal lds_st2        : std_logic;
289 
 
290 
signal lds_st           : std_logic;
291 
 
292 
signal st_st          : std_logic;
293 
signal ld_st          : std_logic;
294 
 
295 
signal sbi_st         : std_logic;
296 
signal cbi_st         : std_logic;
297 
 
298 
signal push_st        : std_logic;
299 
signal pop_st         : std_logic;
300 
 
301 
-- INTERNAL STATE MACHINES
302 
signal nop_insert_st  : std_logic;
303 
signal cpu_busy       : std_logic;
304 
 
305 
-- INTERNAL COPIES OF OUTPUTS
306 
signal pc_int              : std_logic_vector (15 downto 0);
307 
signal adr_int             : std_logic_vector (5 downto 0);
308 
signal iore_int                    : std_logic;
309 
signal iowe_int            : std_logic;
310 
signal ramadr_int          : std_logic_vector (15 downto 0);
311 
signal ramre_int           : std_logic;
312 
signal ramwe_int           : std_logic;
313 
signal dbusout_int         : std_logic_vector (7 downto 0);
314 
 
315 
-- COMMAND REGISTER
316 
signal instruction_reg      : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER
317 
signal instruction_code_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER WITH NOP INSERTION
318 
signal instruction_reg_ena  : std_logic;                               -- CLOCK ENABLE
319 
 
320 
 
321 
-- IRQ INTERNAL LOGIC
322 
signal irq_int              : std_logic;
323 
signal irq_vector_adr       : std_logic_vector(15 downto 0);
324 
 
325 
-- INTERRUPT RELATING REGISTERS
326 
signal pc_for_interrupt : std_logic_vector(15 downto 0);
327 
 
328 
-- DATA EXTRACTOR SIGNALS
329 
signal dex_dat8_immed  : std_logic_vector (7 downto 0);  -- IMMEDIATE CONSTANT (DATA) -> ANDI,ORI,SUBI,SBCI,CPI,LDI
330 
signal dex_dat6_immed  : std_logic_vector (5 downto 0);  -- IMMEDIATE CONSTANT (DATA) -> ADIW,SBIW
331 
signal dex_adr12mem_s  : std_logic_vector (11 downto 0); -- RELATIVE ADDRESS (SIGNED) -> RCALL,RJMP
332 
signal dex_adr6port    : std_logic_vector (5 downto 0);  -- I/O PORT ADDRESS -> IN,OUT
333 
signal dex_adr5port    : std_logic_vector (4 downto 0);  -- I/O PORT ADDRESS -> CBI,SBI,SBIC,SBIS
334 
signal dex_adr_disp    : std_logic_vector (5 downto 0);  -- DISPLACEMENT FO ADDDRESS -> STD,LDD
335 
signal dex_condition   : std_logic_vector (2 downto 0);  -- CONDITION -> BRBC,BRBS
336 
signal dex_bitnum_sreg : std_logic_vector (2 downto 0);  -- NUMBER OF BIT IN SREG -> BCLR,BSET
337 
signal dex_adrreg_r    : std_logic_vector (4 downto 0);  -- SOURCE REGISTER ADDRESS -> .......
338 
signal dex_adrreg_d    : std_logic_vector (4 downto 0);  -- DESTINATION REGISTER ADDRESS -> ......
339 
signal dex_bitop_bitnum : std_logic_vector(2 downto 0);  -- NUMBER OF BIT FOR BIT ORIENTEDE OPERATION -> BST/BLD+SBI/CBI+SBIC/SBIS+SBRC/SBRS !! CHECKED
340 
signal dex_brxx_offset : std_logic_vector (6 downto 0);  -- RELATIVE ADDRESS (SIGNED) -> BRBC,BRBS !! CHECKED
341 
signal dex_adiw_sbiw_reg_adr  : std_logic_vector (1 downto 0);  -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS
342 
 
343 
signal dex_adrreg_d_latched : std_logic_vector (4 downto 0);   --  STORE ADDRESS OF DESTINATION REGISTER FOR LDS/STS/POP INSTRUCTIONS
344 
signal gp_reg_tmp           : std_logic_vector (7 downto 0);   --  STORE DATA FROM THE REGISTERS FOR STS,ST INSTRUCTIONS
345 
signal cbi_sbi_io_adr_tmp   : std_logic_vector (4 downto 0);   --  STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION
346 
signal cbi_sbi_bit_num_tmp  : std_logic_vector (2 downto 0);   --  STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION
347 
 
348 
-- INSTRUCTIONS DECODER SIGNALS
349 
 
350 
signal idc_adc     : std_logic; -- INSTRUCTION ADC
351 
signal idc_add     : std_logic; -- INSTRUCTION ADD
352 
signal idc_adiw    : std_logic; -- INSTRUCTION ADIW
353 
signal idc_and     : std_logic; -- INSTRUCTION AND
354 
signal idc_andi    : std_logic; -- INSTRUCTION ANDI
355 
signal idc_asr     : std_logic; -- INSTRUCTION ASR
356 
 
357 
signal idc_bclr    : std_logic; -- INSTRUCTION BCLR
358 
signal idc_bld     : std_logic; -- INSTRUCTION BLD
359 
signal idc_brbc    : std_logic; -- INSTRUCTION BRBC
360 
signal idc_brbs    : std_logic; -- INSTRUCTION BRBS
361 
signal idc_bset    : std_logic; -- INSTRUCTION BSET
362 
signal idc_bst     : std_logic; -- INSTRUCTION BST
363 
 
364 
signal idc_call    : std_logic; -- INSTRUCTION CALL
365 
signal idc_cbi     : std_logic; -- INSTRUCTION CBI
366 
signal idc_com     : std_logic; -- INSTRUCTION COM
367 
signal idc_cp      : std_logic; -- INSTRUCTION CP
368 
signal idc_cpc     : std_logic; -- INSTRUCTION CPC
369 
signal idc_cpi     : std_logic; -- INSTRUCTION CPI
370 
signal idc_cpse    : std_logic; -- INSTRUCTION CPSE
371 
 
372 
signal idc_dec     : std_logic; -- INSTRUCTION DEC
373 
 
374 
signal idc_elpm    : std_logic; -- INSTRUCTION ELPM
375 
signal idc_eor     : std_logic; -- INSTRUCTION EOR
376 
 
377 
signal idc_icall   : std_logic; -- INSTRUCTION ICALL
378 
signal idc_ijmp    : std_logic; -- INSTRUCTION IJMP
379 
 
380 
signal idc_in      : std_logic; -- INSTRUCTION IN
381 
signal idc_inc     : std_logic; -- INSTRUCTION INC
382 
 
383 
signal idc_jmp     : std_logic; -- INSTRUCTION JMP
384 
 
385 
signal idc_ld_x    : std_logic; -- INSTRUCTION LD Rx,X ; LD Rx,X+ ;LD Rx,-X
386 
signal idc_ld_y    : std_logic; -- INSTRUCTION LD Rx,Y ; LD Rx,Y+ ;LD Rx,-Y
387 
signal idc_ldd_y   : std_logic; -- INSTRUCTION LDD Rx,Y+q
388 
signal idc_ld_z    : std_logic; -- INSTRUCTION LD Rx,Z ; LD Rx,Z+ ;LD Rx,-Z
389 
signal idc_ldd_z   : std_logic; -- INSTRUCTION LDD Rx,Z+q
390 
 
391 
signal idc_ldi     : std_logic; -- INSTRUCTION LDI
392 
signal idc_lds     : std_logic; -- INSTRUCTION LDS
393 
signal idc_lpm     : std_logic; -- INSTRUCTION LPM
394 
signal idc_lsr     : std_logic; -- INSTRUCTION LSR
395 
 
396 
signal idc_mov     : std_logic; -- INSTRUCTION MOV
397 
signal idc_mul     : std_logic; -- INSTRUCTION MUL
398 
 
399 
signal idc_neg     : std_logic; -- INSTRUCTION NEG
400 
signal idc_nop     : std_logic; -- INSTRUCTION NOP
401 
 
402 
signal idc_or      : std_logic; -- INSTRUCTION OR
403 
signal idc_ori     : std_logic; -- INSTRUCTION ORI
404 
signal idc_out     : std_logic; -- INSTRUCTION OUT
405 
 
406 
signal idc_pop     : std_logic; -- INSTRUCTION POP
407 
signal idc_push    : std_logic; -- INSTRUCTION PUSH
408 
 
409 
signal idc_rcall   : std_logic; -- INSTRUCTION RCALL
410 
signal idc_ret     : std_logic; -- INSTRUCTION RET
411 
signal idc_reti    : std_logic; -- INSTRUCTION RETI
412 
signal idc_rjmp    : std_logic; -- INSTRUCTION RJMP
413 
signal idc_ror     : std_logic; -- INSTRUCTION ROR
414 
 
415 
signal idc_sbc     : std_logic; -- INSTRUCTION SBC
416 
signal idc_sbci    : std_logic; -- INSTRUCTION SBCI
417 
signal idc_sbi     : std_logic; -- INSTRUCTION SBI
418 
signal idc_sbic    : std_logic; -- INSTRUCTION SBIC
419 
signal idc_sbis    : std_logic; -- INSTRUCTION SBIS
420 
signal idc_sbiw    : std_logic; -- INSTRUCTION SBIW
421 
signal idc_sbrc    : std_logic; -- INSTRUCTION SBRC
422 
signal idc_sbrs    : std_logic; -- INSTRUCTION SBRS
423 
signal idc_sleep   : std_logic; -- INSTRUCTION SLEEP
424 
 
425 
signal idc_st_x    : std_logic; -- INSTRUCTION LD X,Rx ; LD X+,Rx ;LD -X,Rx
426 
signal idc_st_y    : std_logic; -- INSTRUCTION LD Y,Rx ; LD Y+,Rx ;LD -Y,Rx
427 
signal idc_std_y   : std_logic; -- INSTRUCTION LDD Y+q,Rx
428 
signal idc_st_z    : std_logic; -- INSTRUCTION LD Z,Rx ; LD Z+,Rx ;LD -Z,Rx
429 
signal idc_std_z   : std_logic; -- INSTRUCTION LDD Z+q,Rx
430 
 
431 
signal idc_sts     : std_logic; -- INSTRUCTION STS
432 
signal idc_sub     : std_logic; -- INSTRUCTION SUB
433 
signal idc_subi    : std_logic; -- INSTRUCTION SUBI
434 
signal idc_swap    : std_logic; -- INSTRUCTION SWAP
435 
 
436 
signal idc_wdr     : std_logic; -- INSTRUCTION WDR
437 
 
438 
-- ADDITIONAL SIGNALS
439 
signal idc_psinc   :  std_logic; -- POST INCREMENT FLAG FOR LD,ST INSTRUCTIONS
440 
signal idc_prdec   :  std_logic; -- PRE DECREMENT  FLAG FOR LD,ST INSTRUCTIONS
441 
 
442 
-- ##################################################
443 
 
444 
-- SREG FLAGS WRITE ENABLE SIGNALS
445 
 
446 
--alias sreg_c_wr_en  : std_logic is sreg_fl_wr_en(0);
447 
--alias sreg_z_wr_en  : std_logic is sreg_fl_wr_en(1);
448 
--alias sreg_n_wr_en  : std_logic is sreg_fl_wr_en(2);
449 
--alias sreg_v_wr_en  : std_logic is sreg_fl_wr_en(3);
450 
--alias sreg_s_wr_en  : std_logic is sreg_fl_wr_en(4);
451 
--alias sreg_h_wr_en  : std_logic is sreg_fl_wr_en(5);
452 
--alias sreg_t_wr_en  : std_logic is sreg_fl_wr_en(6);
453 
--alias sreg_i_wr_en  : std_logic is sreg_fl_wr_en(7);
454 
 
455 
signal sreg_c_wr_en  : std_logic; --  is sreg_fl_wr_en(0);
456 
signal sreg_z_wr_en  : std_logic; --  is sreg_fl_wr_en(1);
457 
signal sreg_n_wr_en  : std_logic; --  is sreg_fl_wr_en(2);
458 
signal sreg_v_wr_en  : std_logic; --  is sreg_fl_wr_en(3);
459 
signal sreg_s_wr_en  : std_logic; --  is sreg_fl_wr_en(4);
460 
signal sreg_h_wr_en  : std_logic; --  is sreg_fl_wr_en(5);
461 
signal sreg_t_wr_en  : std_logic; --  is sreg_fl_wr_en(6);
462 
signal sreg_i_wr_en  : std_logic; --  is sreg_fl_wr_en(7);
463 
 
464 
signal sreg_bop_wr_en : std_logic_vector (7 downto 0);
465 
 
466 
signal sreg_adr_eq  : std_logic;
467 
-- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
468 
 
469 
signal inst_cml_1 :  std_logic_vector ( 15 downto 0 );
470 
signal sp_ndown_up_cml_out :  std_logic;
471 
signal sp_en_cml_out :  std_logic;
472 
signal cpuwait_cml_1 :  std_logic;
473 
signal irqlines_cml_1 :  std_logic_vector ( 22 downto 0 );
474 
signal reg_rd_out_cml_1 :  std_logic_vector ( 7 downto 0 );
475 
signal reg_rd_in_cml_out :  std_logic_vector ( 7 downto 0 );
476 
signal reg_rr_out_cml_1 :  std_logic_vector ( 7 downto 0 );
477 
signal spl_out_cml_1 :  std_logic_vector ( 7 downto 0 );
478 
signal sph_out_cml_1 :  std_logic_vector ( 7 downto 0 );
479 
signal rampz_out_cml_1 :  std_logic_vector ( 7 downto 0 );
480 
signal bitpr_io_out_cml_1 :  std_logic_vector ( 7 downto 0 );
481 
signal irqack_cml_out :  std_logic;
482 
signal irqack_int_cml_1 :  std_logic;
483 
signal irqackad_cml_out :  std_logic_vector ( 4 downto 0 );
484 
signal irqackad_int_cml_1 :  std_logic_vector ( irqackad 'range);
485 
signal two_word_inst_cml_1 :  std_logic;
486 
signal adiw_sbiw_encoder_out_cml_1 :  std_logic_vector ( 4 downto 0 );
487 
signal adiw_sbiw_encoder_mux_out_cml_1 :  std_logic_vector ( 4 downto 0 );
488 
signal program_counter_tmp_cml_1 :  std_logic_vector ( 15 downto 0 );
489 
signal program_counter_cml_1 :  std_logic_vector ( 15 downto 0 );
490 
signal program_counter_high_fr_cml_1 :  std_logic_vector ( 7 downto 0 );
491 
signal pc_low_cml_1 :  std_logic_vector ( 7 downto 0 );
492 
signal pc_high_cml_1 :  std_logic_vector ( 7 downto 0 );
493 
signal reg_rd_wr_cml_out :  std_logic;
494 
signal reg_file_adr_space_cml_1 :  std_logic;
495 
signal io_file_adr_space_cml_1 :  std_logic;
496 
signal nirq_st0_cml_1 :  std_logic;
497 
signal irq_st1_cml_1 :  std_logic;
498 
signal irq_st2_cml_1 :  std_logic;
499 
signal irq_st3_cml_1 :  std_logic;
500 
signal ncall_st0_cml_1 :  std_logic;
501 
signal call_st1_cml_1 :  std_logic;
502 
signal call_st2_cml_1 :  std_logic;
503 
signal call_st3_cml_1 :  std_logic;
504 
signal nrcall_st0_cml_1 :  std_logic;
505 
signal rcall_st1_cml_1 :  std_logic;
506 
signal rcall_st2_cml_1 :  std_logic;
507 
signal nicall_st0_cml_1 :  std_logic;
508 
signal icall_st1_cml_1 :  std_logic;
509 
signal icall_st2_cml_1 :  std_logic;
510 
signal njmp_st0_cml_1 :  std_logic;
511 
signal jmp_st1_cml_1 :  std_logic;
512 
signal jmp_st2_cml_1 :  std_logic;
513 
signal ijmp_st_cml_1 :  std_logic;
514 
signal rjmp_st_cml_1 :  std_logic;
515 
signal nret_st0_cml_1 :  std_logic;
516 
signal ret_st1_cml_1 :  std_logic;
517 
signal ret_st2_cml_1 :  std_logic;
518 
signal ret_st3_cml_1 :  std_logic;
519 
signal nreti_st0_cml_1 :  std_logic;
520 
signal reti_st1_cml_1 :  std_logic;
521 
signal reti_st2_cml_1 :  std_logic;
522 
signal sreg_fl_in_cml_out :  std_logic_vector ( 7 downto 0 );
523 
signal reti_st3_cml_1 :  std_logic;
524 
signal brxx_st_cml_1 :  std_logic;
525 
signal adiw_st_cml_1 :  std_logic;
526 
signal sbiw_st_cml_1 :  std_logic;
527 
signal nskip_inst_st0_cml_1 :  std_logic;
528 
signal skip_inst_st1_cml_1 :  std_logic;
529 
signal skip_inst_st2_cml_1 :  std_logic;
530 
signal nlpm_st0_cml_1 :  std_logic;
531 
signal lpm_st1_cml_1 :  std_logic;
532 
signal lpm_st2_cml_1 :  std_logic;
533 
signal sts_st_cml_1 :  std_logic;
534 
signal lds_st_cml_1 :  std_logic;
535 
signal st_st_cml_1 :  std_logic;
536 
signal ld_st_cml_1 :  std_logic;
537 
signal sbi_st_cml_1 :  std_logic;
538 
signal cbi_st_cml_1 :  std_logic;
539 
signal push_st_cml_1 :  std_logic;
540 
signal pop_st_cml_1 :  std_logic;
541 
signal iowe_cml_out :  std_logic;
542 
signal iowe_int_cml_1 :  std_logic;
543 
signal ramadr_int_cml_1 :  std_logic_vector ( 15 downto 0 );
544 
signal ramre_int_cml_1 :  std_logic;
545 
signal ramwe_int_cml_1 :  std_logic;
546 
signal instruction_reg_cml_1 :  std_logic_vector ( 15 downto 0 );
547 
signal instruction_code_reg_cml_1 :  std_logic_vector ( 15 downto 0 );
548 
signal pc_for_interrupt_cml_1 :  std_logic_vector ( 15 downto 0 );
549 
signal dex_dat8_immed_cml_1 :  std_logic_vector ( 7 downto 0 );
550 
signal dex_adr5port_cml_1 :  std_logic_vector ( 4 downto 0 );
551 
signal dex_adrreg_d_cml_1 :  std_logic_vector ( 4 downto 0 );
552 
signal dex_bitop_bitnum_cml_1 :  std_logic_vector ( 2 downto 0 );
553 
signal dex_adrreg_d_latched_cml_1 :  std_logic_vector ( 4 downto 0 );
554 
signal gp_reg_tmp_cml_1 :  std_logic_vector ( 7 downto 0 );
555 
signal cbi_sbi_io_adr_tmp_cml_1 :  std_logic_vector ( 4 downto 0 );
556 
signal cbi_sbi_bit_num_tmp_cml_1 :  std_logic_vector ( 2 downto 0 );
557 
signal idc_adc_cml_1 :  std_logic;
558 
signal idc_add_cml_1 :  std_logic;
559 
signal idc_adiw_cml_1 :  std_logic;
560 
signal idc_and_cml_1 :  std_logic;
561 
signal idc_andi_cml_1 :  std_logic;
562 
signal idc_asr_cml_1 :  std_logic;
563 
signal idc_bclr_out_cml_out :  std_logic;
564 
signal idc_bclr_cml_1 :  std_logic;
565 
signal idc_brbc_cml_1 :  std_logic;
566 
signal idc_brbs_cml_1 :  std_logic;
567 
signal idc_bset_out_cml_out :  std_logic;
568 
signal idc_bset_cml_1 :  std_logic;
569 
signal idc_call_cml_1 :  std_logic;
570 
signal idc_cbi_cml_1 :  std_logic;
571 
signal idc_com_cml_1 :  std_logic;
572 
signal idc_cp_cml_1 :  std_logic;
573 
signal idc_cpc_cml_1 :  std_logic;
574 
signal idc_cpi_cml_1 :  std_logic;
575 
signal idc_cpse_cml_1 :  std_logic;
576 
signal idc_dec_cml_1 :  std_logic;
577 
signal idc_elpm_cml_1 :  std_logic;
578 
signal idc_eor_cml_1 :  std_logic;
579 
signal idc_icall_cml_1 :  std_logic;
580 
signal idc_ijmp_cml_1 :  std_logic;
581 
signal idc_in_cml_1 :  std_logic;
582 
signal idc_inc_cml_1 :  std_logic;
583 
signal idc_jmp_cml_1 :  std_logic;
584 
signal reg_h_wr_cml_out :  std_logic;
585 
signal reg_h_adr_cml_out :  std_logic_vector ( 2 downto 0 );
586 
signal idc_ld_x_cml_1 :  std_logic;
587 
signal idc_ld_y_cml_1 :  std_logic;
588 
signal idc_ldd_y_cml_1 :  std_logic;
589 
signal idc_ld_z_cml_1 :  std_logic;
590 
signal idc_ldd_z_cml_1 :  std_logic;
591 
signal idc_ldi_cml_1 :  std_logic;
592 
signal idc_lds_cml_1 :  std_logic;
593 
signal idc_lpm_cml_1 :  std_logic;
594 
signal idc_lsr_cml_1 :  std_logic;
595 
signal idc_neg_cml_1 :  std_logic;
596 
signal idc_or_cml_1 :  std_logic;
597 
signal idc_ori_cml_1 :  std_logic;
598 
signal idc_out_cml_1 :  std_logic;
599 
signal idc_pop_cml_1 :  std_logic;
600 
signal idc_push_cml_1 :  std_logic;
601 
signal idc_rcall_cml_1 :  std_logic;
602 
signal idc_ret_cml_1 :  std_logic;
603 
signal idc_reti_out_cml_out :  std_logic;
604 
signal idc_reti_cml_1 :  std_logic;
605 
signal idc_rjmp_cml_1 :  std_logic;
606 
signal idc_ror_cml_1 :  std_logic;
607 
signal idc_sbc_cml_1 :  std_logic;
608 
signal idc_sbci_cml_1 :  std_logic;
609 
signal idc_sbi_cml_1 :  std_logic;
610 
signal idc_sbic_cml_1 :  std_logic;
611 
signal idc_sbis_cml_1 :  std_logic;
612 
signal idc_sbiw_cml_1 :  std_logic;
613 
signal idc_sbrc_cml_1 :  std_logic;
614 
signal idc_sbrs_cml_1 :  std_logic;
615 
signal idc_st_x_cml_1 :  std_logic;
616 
signal idc_st_y_cml_1 :  std_logic;
617 
signal idc_std_y_cml_1 :  std_logic;
618 
signal idc_st_z_cml_1 :  std_logic;
619 
signal idc_std_z_cml_1 :  std_logic;
620 
signal idc_sts_cml_1 :  std_logic;
621 
signal idc_sub_cml_1 :  std_logic;
622 
signal idc_subi_cml_1 :  std_logic;
623 
signal idc_swap_cml_1 :  std_logic;
624 
signal sreg_bop_wr_en_cml_1 :  std_logic_vector ( 7 downto 0 );
625 
signal sreg_adr_eq_cml_1 :  std_logic;
626 
 
627 
begin
628 
 
629 
 
630 
 
631 
process(cp2_cml_1) begin
632 
if (cp2_cml_1 = '1' and cp2_cml_1'event) then
633 
        inst_cml_1 <= inst;
634 
        cpuwait_cml_1 <= cpuwait;
635 
        irqlines_cml_1 <= irqlines;
636 
        reg_rd_out_cml_1 <= reg_rd_out;
637 
        reg_rr_out_cml_1 <= reg_rr_out;
638 
        spl_out_cml_1 <= spl_out;
639 
        sph_out_cml_1 <= sph_out;
640 
        rampz_out_cml_1 <= rampz_out;
641 
        bitpr_io_out_cml_1 <= bitpr_io_out;
642 
        irqack_int_cml_1 <= irqack_int;
643 
        irqackad_int_cml_1 <= irqackad_int;
644 
        two_word_inst_cml_1 <= two_word_inst;
645 
        adiw_sbiw_encoder_out_cml_1 <= adiw_sbiw_encoder_out;
646 
        adiw_sbiw_encoder_mux_out_cml_1 <= adiw_sbiw_encoder_mux_out;
647 
        program_counter_tmp_cml_1 <= program_counter_tmp;
648 
        program_counter_cml_1 <= program_counter;
649 
        program_counter_high_fr_cml_1 <= program_counter_high_fr;
650 
        pc_low_cml_1 <= pc_low;
651 
        pc_high_cml_1 <= pc_high;
652 
        reg_file_adr_space_cml_1 <= reg_file_adr_space;
653 
        io_file_adr_space_cml_1 <= io_file_adr_space;
654 
        nirq_st0_cml_1 <= nirq_st0;
655 
        irq_st1_cml_1 <= irq_st1;
656 
        irq_st2_cml_1 <= irq_st2;
657 
        irq_st3_cml_1 <= irq_st3;
658 
        ncall_st0_cml_1 <= ncall_st0;
659 
        call_st1_cml_1 <= call_st1;
660 
        call_st2_cml_1 <= call_st2;
661 
        call_st3_cml_1 <= call_st3;
662 
        nrcall_st0_cml_1 <= nrcall_st0;
663 
        rcall_st1_cml_1 <= rcall_st1;
664 
        rcall_st2_cml_1 <= rcall_st2;
665 
        nicall_st0_cml_1 <= nicall_st0;
666 
        icall_st1_cml_1 <= icall_st1;
667 
        icall_st2_cml_1 <= icall_st2;
668 
        njmp_st0_cml_1 <= njmp_st0;
669 
        jmp_st1_cml_1 <= jmp_st1;
670 
        jmp_st2_cml_1 <= jmp_st2;
671 
        ijmp_st_cml_1 <= ijmp_st;
672 
        rjmp_st_cml_1 <= rjmp_st;
673 
        nret_st0_cml_1 <= nret_st0;
674 
        ret_st1_cml_1 <= ret_st1;
675 
        ret_st2_cml_1 <= ret_st2;
676 
        ret_st3_cml_1 <= ret_st3;
677 
        nreti_st0_cml_1 <= nreti_st0;
678 
        reti_st1_cml_1 <= reti_st1;
679 
        reti_st2_cml_1 <= reti_st2;
680 
        reti_st3_cml_1 <= reti_st3;
681 
        brxx_st_cml_1 <= brxx_st;
682 
        adiw_st_cml_1 <= adiw_st;
683 
        sbiw_st_cml_1 <= sbiw_st;
684 
        nskip_inst_st0_cml_1 <= nskip_inst_st0;
685 
        skip_inst_st1_cml_1 <= skip_inst_st1;
686 
        skip_inst_st2_cml_1 <= skip_inst_st2;
687 
        nlpm_st0_cml_1 <= nlpm_st0;
688 
        lpm_st1_cml_1 <= lpm_st1;
689 
        lpm_st2_cml_1 <= lpm_st2;
690 
        sts_st_cml_1 <= sts_st;
691 
        lds_st_cml_1 <= lds_st;
692 
        st_st_cml_1 <= st_st;
693 
        ld_st_cml_1 <= ld_st;
694 
        sbi_st_cml_1 <= sbi_st;
695 
        cbi_st_cml_1 <= cbi_st;
696 
        push_st_cml_1 <= push_st;
697 
        pop_st_cml_1 <= pop_st;
698 
        iowe_int_cml_1 <= iowe_int;
699 
        ramadr_int_cml_1 <= ramadr_int;
700 
        ramre_int_cml_1 <= ramre_int;
701 
        ramwe_int_cml_1 <= ramwe_int;
702 
        instruction_reg_cml_1 <= instruction_reg;
703 
        instruction_code_reg_cml_1 <= instruction_code_reg;
704 
        pc_for_interrupt_cml_1 <= pc_for_interrupt;
705 
        dex_dat8_immed_cml_1 <= dex_dat8_immed;
706 
        dex_adr5port_cml_1 <= dex_adr5port;
707 
        dex_adrreg_d_cml_1 <= dex_adrreg_d;
708 
        dex_bitop_bitnum_cml_1 <= dex_bitop_bitnum;
709 
        dex_adrreg_d_latched_cml_1 <= dex_adrreg_d_latched;
710 
        gp_reg_tmp_cml_1 <= gp_reg_tmp;
711 
        cbi_sbi_io_adr_tmp_cml_1 <= cbi_sbi_io_adr_tmp;
712 
        cbi_sbi_bit_num_tmp_cml_1 <= cbi_sbi_bit_num_tmp;
713 
        idc_adc_cml_1 <= idc_adc;
714 
        idc_add_cml_1 <= idc_add;
715 
        idc_adiw_cml_1 <= idc_adiw;
716 
        idc_and_cml_1 <= idc_and;
717 
        idc_andi_cml_1 <= idc_andi;
718 
        idc_asr_cml_1 <= idc_asr;
719 
        idc_bclr_cml_1 <= idc_bclr;
720 
        idc_brbc_cml_1 <= idc_brbc;
721 
        idc_brbs_cml_1 <= idc_brbs;
722 
        idc_bset_cml_1 <= idc_bset;
723 
        idc_call_cml_1 <= idc_call;
724 
        idc_cbi_cml_1 <= idc_cbi;
725 
        idc_com_cml_1 <= idc_com;
726 
        idc_cp_cml_1 <= idc_cp;
727 
        idc_cpc_cml_1 <= idc_cpc;
728 
        idc_cpi_cml_1 <= idc_cpi;
729 
        idc_cpse_cml_1 <= idc_cpse;
730 
        idc_dec_cml_1 <= idc_dec;
731 
        idc_elpm_cml_1 <= idc_elpm;
732 
        idc_eor_cml_1 <= idc_eor;
733 
        idc_icall_cml_1 <= idc_icall;
734 
        idc_ijmp_cml_1 <= idc_ijmp;
735 
        idc_in_cml_1 <= idc_in;
736 
        idc_inc_cml_1 <= idc_inc;
737 
        idc_jmp_cml_1 <= idc_jmp;
738 
        idc_ld_x_cml_1 <= idc_ld_x;
739 
        idc_ld_y_cml_1 <= idc_ld_y;
740 
        idc_ldd_y_cml_1 <= idc_ldd_y;
741 
        idc_ld_z_cml_1 <= idc_ld_z;
742 
        idc_ldd_z_cml_1 <= idc_ldd_z;
743 
        idc_ldi_cml_1 <= idc_ldi;
744 
        idc_lds_cml_1 <= idc_lds;
745 
        idc_lpm_cml_1 <= idc_lpm;
746 
        idc_lsr_cml_1 <= idc_lsr;
747 
        idc_neg_cml_1 <= idc_neg;
748 
        idc_or_cml_1 <= idc_or;
749 
        idc_ori_cml_1 <= idc_ori;
750 
        idc_out_cml_1 <= idc_out;
751 
        idc_pop_cml_1 <= idc_pop;
752 
        idc_push_cml_1 <= idc_push;
753 
        idc_rcall_cml_1 <= idc_rcall;
754 
        idc_ret_cml_1 <= idc_ret;
755 
        idc_reti_cml_1 <= idc_reti;
756 
        idc_rjmp_cml_1 <= idc_rjmp;
757 
        idc_ror_cml_1 <= idc_ror;
758 
        idc_sbc_cml_1 <= idc_sbc;
759 
        idc_sbci_cml_1 <= idc_sbci;
760 
        idc_sbi_cml_1 <= idc_sbi;
761 
        idc_sbic_cml_1 <= idc_sbic;
762 
        idc_sbis_cml_1 <= idc_sbis;
763 
        idc_sbiw_cml_1 <= idc_sbiw;
764 
        idc_sbrc_cml_1 <= idc_sbrc;
765 
        idc_sbrs_cml_1 <= idc_sbrs;
766 
        idc_st_x_cml_1 <= idc_st_x;
767 
        idc_st_y_cml_1 <= idc_st_y;
768 
        idc_std_y_cml_1 <= idc_std_y;
769 
        idc_st_z_cml_1 <= idc_st_z;
770 
        idc_std_z_cml_1 <= idc_std_z;
771 
        idc_sts_cml_1 <= idc_sts;
772 
        idc_sub_cml_1 <= idc_sub;
773 
        idc_subi_cml_1 <= idc_subi;
774 
        idc_swap_cml_1 <= idc_swap;
775 
        sreg_bop_wr_en_cml_1 <= sreg_bop_wr_en;
776 
        sreg_adr_eq_cml_1 <= sreg_adr_eq;
777 
end if;
778 
end process;
779 
sp_ndown_up <= sp_ndown_up_cml_out;
780 
sp_en <= sp_en_cml_out;
781 
reg_rd_in <= reg_rd_in_cml_out;
782 
irqack <= irqack_cml_out;
783 
irqackad <= irqackad_cml_out;
784 
reg_rd_wr <= reg_rd_wr_cml_out;
785 
sreg_fl_in <= sreg_fl_in_cml_out;
786 
iowe <= iowe_cml_out;
787 
idc_bclr_out <= idc_bclr_out_cml_out;
788 
idc_bset_out <= idc_bset_out_cml_out;
789 
reg_h_wr <= reg_h_wr_cml_out;
790 
reg_h_adr <= reg_h_adr_cml_out;
791 
idc_reti_out <= idc_reti_out_cml_out;
792 
 
793 
 
794 
sreg_fl_wr_en <= sreg_i_wr_en & sreg_t_wr_en & sreg_h_wr_en & sreg_s_wr_en & sreg_v_wr_en & sreg_n_wr_en & sreg_z_wr_en & sreg_c_wr_en;
795 
 
796 
 
797 
-- INSTRUCTION FETCH
798 
instruction_reg_ena <= '1'; -- FOR TEST
799 
 
800 
-- SynEDA CoreMultiplier
801 
-- assignment(s): instruction_reg
802 
-- replace(s): inst, instruction_reg
803 
 
804 
instruction_fetch:process(cp2,ireset)
805 
begin
806 
if ireset='0' then                              -- RESET
807 
instruction_reg <= (others => '0');
808 
elsif (cp2='1' and cp2'event) then instruction_reg <= instruction_reg_cml_1;            -- CLOCK
809 
 if (cp2en='1') then                                                      -- Clock enable
810 
  if instruction_reg_ena='1' then
811 
   instruction_reg <= inst_cml_1;
812 
  end if;
813 
 end if;
814 
end if;
815 
end process;
816 
 
817 
-- TWO WORDS INSTRUCTION DETECTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)
818 
two_word_inst <= '1' when
819 
((instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010111") or    -- CALL
820 
 (instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010110")) or   -- JMP
821 
 (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010000000") or -- LDS
822 
 (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010010000")    -- STS
823 
   else '0';  -- TO DETECT CALL/JMP/LDS/STS INSTRUCTIONS FOR SBRS/SBRC/SBIS/SBIC/CPSE
824 
 
825 
 
826 
 
827 
-- DATA EXTRACTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)
828 
dex_dat8_immed <= instruction_reg(11 downto 8) & instruction_reg(3 downto 0);
829 
dex_dat6_immed <= instruction_reg(7 downto 6) & instruction_reg(3 downto 0);
830 
-- SynEDA CoreMultiplier
831 
-- assignment(s): dex_adr12mem_s
832 
-- replace(s): instruction_reg
833 
 
834 
dex_adr12mem_s <= instruction_reg_cml_1(11 downto 0);
835 
dex_adr6port <= instruction_reg(10 downto 9) & instruction_reg(3 downto 0);
836 
dex_adr5port <= instruction_reg(7 downto 3);
837 
-- SynEDA CoreMultiplier
838 
-- assignment(s): dex_adr_disp
839 
-- replace(s): instruction_reg
840 
 
841 
dex_adr_disp <= instruction_reg_cml_1(13) & instruction_reg_cml_1(11 downto 10) & instruction_reg_cml_1(2 downto 0);
842 
dex_condition <= instruction_reg(2 downto 0);
843 
dex_bitop_bitnum <= instruction_reg(2 downto 0);      -- NUMBER(POSITION) OF TESTING BIT IN SBRC/SBRS/SBIC/SBIS INSTRUCTION
844 
dex_bitnum_sreg <= instruction_reg(6 downto 4);
845 
dex_adrreg_r  <=  instruction_reg(9) & instruction_reg(3 downto 0);
846 
dex_adrreg_d  <= instruction_reg(8 downto 4);
847 
-- SynEDA CoreMultiplier
848 
-- assignment(s): dex_brxx_offset
849 
-- replace(s): instruction_reg
850 
 
851 
dex_brxx_offset <= instruction_reg_cml_1(9 downto 3);       -- OFFSET FOR BRBC/BRBS
852 
dex_adiw_sbiw_reg_adr <= instruction_reg(5 downto 4); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS
853 
--dex_adrindreg <= instruction_reg(3 downto 2);
854 
 
855 
-- SynEDA CoreMultiplier
856 
-- assignment(s): dex_adrreg_d_latched
857 
-- replace(s): dex_adrreg_d, dex_adrreg_d_latched, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
858 
 
859 
-- LATCH Rd ADDDRESS FOR LDS/STS/POP INSTRUCTIONS
860 
latcht_rd_adr:process(cp2,ireset)
861 
begin
862 
if ireset ='0' then
863 
dex_adrreg_d_latched <= (others => '0');
864 
elsif (cp2='1' and cp2'event) then dex_adrreg_d_latched <= dex_adrreg_d_latched_cml_1;
865 
 if (cp2en='1') then                                                      -- Clock enable
866 
  if ((idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ldd_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_z_cml_1) or idc_sts_cml_1 or
867 
          (idc_st_x_cml_1  or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)or idc_lds_cml_1 or
868 
           idc_pop_cml_1)='1' then
869 
   dex_adrreg_d_latched <= dex_adrreg_d_cml_1;
870 
  end if;
871 
 end if;
872 
end if;
873 
end process;
874 
-- +++++++++++++++++++++++++++++++++++++++++++++++++
875 
 
876 
 
877 
-- R24:R25/R26:R27/R28:R29/R30:R31 ADIW/SBIW  ADDRESS CONTROL LOGIC
878 
adiw_sbiw_encoder_out <= "11"&dex_adiw_sbiw_reg_adr&'0';
879 
 
880 
-- SynEDA CoreMultiplier
881 
-- assignment(s): adiw_sbiw_encoder_mux_out
882 
-- replace(s): adiw_sbiw_encoder_out, adiw_sbiw_encoder_mux_out
883 
 
884 
adiw_sbiw_high_reg_adr:process(cp2,ireset)
885 
begin
886 
if ireset ='0' then
887 
adiw_sbiw_encoder_mux_out <= (others=>'0');
888 
elsif(cp2='1' and cp2'event) then adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_mux_out_cml_1;
889 
 if (cp2en='1') then                                                      -- Clock enable
890 
  adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_out_cml_1 +1;
891 
 end if;
892 
end if;
893 
end process;
894 
 
895 
-- ##########################
896 
 
897 
-- NOP INSERTION
898 
 
899 
--instruction_code_reg <= instruction_reg when nop_insert_st='0' else (others => '0');
900 
instruction_code_reg <= (others => '0') when (nop_insert_st='1') else -- NOP
901 
                        instruction_reg;                                                                                                -- Instruction
902 
 
903 
 
904 
nop_insert_st <= adiw_st or sbiw_st or cbi_st or sbi_st or rjmp_st or ijmp_st or pop_st or push_st or
905 
              brxx_st or ld_st or st_st or ncall_st0 or nirq_st0 or nret_st0 or nreti_st0 or nlpm_st0 or njmp_st0 or
906 
              nrcall_st0 or nicall_st0 or sts_st or lds_st or nskip_inst_st0;
907 
 
908 
 
909 
-- INSTRUCTION DECODER (CONNECTED AFTER NOP INSERTION LOGIC)
910 
 
911 
idc_adc  <= '1' when instruction_code_reg(15 downto 10) = "000111" else '0'; -- 000111XXXXXXXXXX
912 
idc_add  <= '1' when instruction_code_reg(15 downto 10) = "000011" else '0'; -- 000011XXXXXXXXXX
913 
 
914 
idc_adiw <= '1' when instruction_code_reg(15 downto 8) = "10010110" else '0'; -- 10010110XXXXXXXX
915 
 
916 
idc_and  <= '1' when instruction_code_reg(15 downto 10) = "001000" else '0'; -- 001000XXXXXXXXXX
917 
idc_andi <= '1' when instruction_code_reg(15 downto 12) = "0111" else '0'; -- 0111XXXXXXXXXXXX
918 
 
919 
idc_asr  <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100101" else '0'; -- 1001010XXXXX0101
920 
 
921 
idc_bclr <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010011000" else '0'; -- 100101001XXX1000
922 
 
923 
-- SynEDA CoreMultiplier
924 
-- assignment(s): idc_bld
925 
-- replace(s): instruction_code_reg
926 
 
927 
idc_bld  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3) = "11111000" else '0'; -- 1111100XXXXX0XXX
928 
 
929 
idc_brbc <= '1' when instruction_code_reg(15 downto 10) = "111101" else '0'; -- 111101XXXXXXXXXX
930 
idc_brbs <= '1' when instruction_code_reg(15 downto 10) = "111100" else '0'; -- 111100XXXXXXXXXX
931 
 
932 
idc_bset <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(3 downto 0) = "1001010001000" else '0'; -- 100101000XXX1000
933 
 
934 
-- SynEDA CoreMultiplier
935 
-- assignment(s): idc_bst
936 
-- replace(s): instruction_code_reg
937 
 
938 
idc_bst  <= '1' when instruction_code_reg_cml_1(15 downto 9) = "1111101" else '0'; -- 1111101XXXXXXXXX
939 
 
940 
idc_call <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010111" else '0'; -- 1001010XXXXX111X
941 
 
942 
idc_cbi  <= '1' when instruction_code_reg(15 downto 8) = "10011000" else '0'; -- 10011000XXXXXXXX
943 
 
944 
idc_com  <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100000" else '0'; -- 1001010XXXXX0000
945 
 
946 
idc_cp   <= '1' when instruction_code_reg(15 downto 10) = "000101" else '0'; -- 000101XXXXXXXXXX
947 
 
948 
idc_cpc  <= '1' when instruction_code_reg(15 downto 10) = "000001" else '0'; -- 000001XXXXXXXXXX
949 
 
950 
idc_cpi  <= '1' when instruction_code_reg(15 downto 12) = "0011" else '0'; -- 0011XXXXXXXXXXXX
951 
 
952 
idc_cpse <= '1' when instruction_code_reg(15 downto 10) = "000100" else '0'; -- 000100XXXXXXXXXX
953 
 
954 
idc_dec  <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010101010" else '0'; -- 1001010XXXXX1010
955 
 
956 
idc_elpm <= '1' when instruction_code_reg = "1001010111011000" else '0'; -- 1001010111011000
957 
 
958 
idc_eor  <= '1' when instruction_code_reg(15 downto 10) = "001001" else '0'; -- 001001XXXXXXXXXX
959 
 
960 
idc_icall<= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101011001" else '0'; -- 10010101XXXX1001
961 
 
962 
idc_ijmp <= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101001001" else '0'; -- 10010100XXXX1001
963 
 
964 
idc_in   <= '1' when instruction_code_reg(15 downto 11) = "10110" else '0'; -- 10110XXXXXXXXXXX
965 
 
966 
idc_inc  <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100011" else '0'; -- 1001010XXXXX0011
967 
 
968 
idc_jmp  <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 1) = "1001010110" else '0'; -- 1001010XXXXX110X
969 
 
970 
 
971 
-- LD,LDD
972 
idc_ld_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001100" or
973 
                     instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001101"  or
974 
                                         instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001110" else '0';
975 
 
976 
idc_ld_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001001" or
977 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001010") else '0';
978 
 
979 
idc_ldd_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10001" else '0'; -- 10X0XX0XXXXX1XXX
980 
 
981 
idc_ld_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000001" or
982 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000010") else '0';
983 
 
984 
idc_ldd_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10000" else '0'; -- 10X0XX0XXXXX0XXX
985 
-- ######
986 
 
987 
 
988 
idc_ldi <= '1' when instruction_code_reg(15 downto 12) = "1110" else '0'; -- 1110XXXXXXXXXXXX
989 
 
990 
idc_lds <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010000000" else '0'; -- 1001000XXXXX0000
991 
 
992 
idc_lpm <= '1' when instruction_code_reg = "1001010111001000" else '0'; -- 1001010111001000
993 
 
994 
idc_lsr <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100110" else '0'; -- 1001010XXXXX0110
995 
 
996 
-- SynEDA CoreMultiplier
997 
-- assignment(s): idc_mov
998 
-- replace(s): instruction_code_reg
999 
 
1000 
idc_mov <= '1' when instruction_code_reg_cml_1(15 downto 10) = "001011" else '0'; -- 001011XXXXXXXXXX
1001 
 
1002 
idc_mul <= '1' when instruction_code_reg(15 downto 10) = "100111" else '0'; -- 100111XXXXXXXXXX
1003 
 
1004 
idc_neg <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100001" else '0'; -- 1001010XXXXX0001
1005 
 
1006 
idc_nop <= '1' when instruction_code_reg = "0000000000000000" else '0'; -- 0000000000000000
1007 
 
1008 
idc_or  <= '1' when instruction_code_reg(15 downto 10) = "001010" else '0'; -- 001010XXXXXXXXXX
1009 
 
1010 
idc_ori <= '1' when instruction_code_reg(15 downto 12) = "0110" else '0'; -- 0110XXXXXXXXXXXX
1011 
 
1012 
idc_out <= '1' when instruction_code_reg(15 downto 11) = "10111" else '0'; -- 10111XXXXXXXXXXX
1013 
 
1014 
idc_pop <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001111" else '0'; -- 1001000XXXXX1111
1015 
 
1016 
idc_push<= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011111" else '0'; -- 1001001XXXXX1111
1017 
 
1018 
idc_rcall<= '1' when instruction_code_reg(15 downto 12) = "1101" else '0'; -- 1101XXXXXXXXXXXX
1019 
 
1020 
idc_ret  <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101001000" else '0'; -- 100101010XX01000
1021 
 
1022 
idc_reti <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101011000" else '0'; -- 100101010XX11000
1023 
 
1024 
idc_rjmp <= '1' when instruction_code_reg(15 downto 12) = "1100" else '0'; -- 1100XXXXXXXXXXXX
1025 
 
1026 
idc_ror  <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100111" else '0'; -- 1001010XXXXX0111
1027 
 
1028 
idc_sbc  <= '1' when instruction_code_reg(15 downto 10) = "000010" else '0'; -- 000010XXXXXXXXXX
1029 
 
1030 
idc_sbci <= '1' when instruction_code_reg(15 downto 12) = "0100" else '0'; -- 0100XXXXXXXXXXXX
1031 
 
1032 
idc_sbi  <= '1' when instruction_code_reg(15 downto 8) = "10011010" else '0'; -- 10011010XXXXXXXX
1033 
 
1034 
idc_sbic <= '1' when instruction_code_reg(15 downto 8) = "10011001" else '0'; -- 10011001XXXXXXXX
1035 
 
1036 
idc_sbis <= '1' when instruction_code_reg(15 downto 8) = "10011011" else '0'; -- 10011011XXXXXXXX
1037 
 
1038 
idc_sbiw <= '1' when instruction_code_reg(15 downto 8) = "10010111" else '0'; -- 10010111XXXXXXXX
1039 
 
1040 
idc_sbrc <= '1' when instruction_code_reg(15 downto 9) = "1111110" else '0'; -- 1111110XXXXXXXXX
1041 
 
1042 
idc_sbrs <= '1' when instruction_code_reg(15 downto 9) = "1111111" else '0'; -- 1111111XXXXXXXXX
1043 
 
1044 
-- SynEDA CoreMultiplier
1045 
-- assignment(s): idc_sleep
1046 
-- replace(s): instruction_code_reg
1047 
 
1048 
idc_sleep<= '1' when instruction_code_reg_cml_1(15 downto 5)&instruction_code_reg_cml_1(3 downto 0) = "100101011001000" else '0'; -- 10010101100X1000
1049 
 
1050 
 
1051 
-- ST,STD
1052 
idc_st_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011100" or
1053 
                     instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011101" or
1054 
                     instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011110" else '0';
1055 
 
1056 
idc_st_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011001" or
1057 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011010") else '0';
1058 
 
1059 
idc_std_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10011" else '0'; -- 10X0XX1XXXXX1XXX
1060 
 
1061 
idc_st_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010001" or
1062 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010010") else '0';
1063 
 
1064 
idc_std_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10010" else '0'; -- 10X0XX1XXXXX0XXX
1065 
-- ######
1066 
 
1067 
idc_sts  <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010010000" else '0'; -- 1001001XXXXX0000
1068 
 
1069 
idc_sub  <= '1' when instruction_code_reg(15 downto 10) = "000110" else '0'; -- 000110XXXXXXXXXX
1070 
 
1071 
idc_subi <= '1' when instruction_code_reg(15 downto 12) = "0101" else '0'; -- 0101XXXXXXXXXXXX
1072 
 
1073 
idc_swap <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100010" else '0'; -- 1001010XXXXX0010
1074 
 
1075 
-- SynEDA CoreMultiplier
1076 
-- assignment(s): idc_wdr
1077 
-- replace(s): instruction_code_reg
1078 
 
1079 
idc_wdr  <= '1' when instruction_code_reg_cml_1(15 downto 5)&instruction_code_reg_cml_1(3 downto 0) = "100101011011000" else '0'; -- 10010101101X1000
1080 
 
1081 
-- SynEDA CoreMultiplier
1082 
-- assignment(s): idc_psinc
1083 
-- replace(s): instruction_code_reg, idc_ld_x, idc_ld_y, idc_ld_z, idc_st_x, idc_st_y, idc_st_z
1084 
 
1085 
-- ADDITIONAL SIGNALS
1086 
idc_psinc <= '1' when (instruction_code_reg_cml_1(1 downto 0) = "01" and
1087 
 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_st_z_cml_1 or idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ld_z_cml_1)='1') else '0';  -- POST INCREMENT FOR LD/ST INSTRUCTIONS
1088 
 
1089 
-- SynEDA CoreMultiplier
1090 
-- assignment(s): idc_prdec
1091 
-- replace(s): instruction_code_reg, idc_ld_x, idc_ld_y, idc_ld_z, idc_st_x, idc_st_y, idc_st_z
1092 
 
1093 
idc_prdec <= '1' when (instruction_code_reg_cml_1(1 downto 0)    = "10" and
1094 
 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_st_z_cml_1 or idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ld_z_cml_1)='1') else '0';  -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
1095 
 
1096 
 
1097 
-- ##########################################################################################################
1098 
 
1099 
-- SynEDA CoreMultiplier
1100 
-- assignment(s): ramadr_reg_en
1101 
-- replace(s): cpuwait, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1102 
 
1103 
-- WRITE ENABLE SIGNALS FOR ramadr_reg
1104 
ramadr_reg_en <= idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ldd_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_z_cml_1 or idc_lds_cml_1 or    -- LD/LDD/LDS(two cycle execution)
1105 
                 idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1 or idc_sts_cml_1 or    -- ST/STS/STS(two cycle execution)
1106 
                                 idc_push_cml_1 or idc_pop_cml_1 or
1107 
                                 idc_rcall_cml_1 or (rcall_st1_cml_1 and not cpuwait_cml_1) or idc_icall_cml_1 or (icall_st1_cml_1 and not cpuwait_cml_1) or -- RCALL/ICALL
1108 
                                 call_st1_cml_1 or  (call_st2_cml_1 and not cpuwait_cml_1) or irq_st1_cml_1 or (irq_st2_cml_1 and not cpuwait_cml_1) or      -- CALL/IRQ
1109 
                                 idc_ret_cml_1 or (ret_st1_cml_1 and not cpuwait_cml_1 ) or idc_reti_cml_1 or (reti_st1_cml_1 and not cpuwait_cml_1);            -- RET/RETI  -- ??
1110 
 
1111 
 
1112 
-- SynEDA CoreMultiplier
1113 
-- assignment(s): ramadr_reg_in
1114 
-- replace(s): inst, cpuwait, spl_out, sph_out, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_ld_x, idc_ld_y, idc_ld_z, idc_lds, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_st_x, idc_st_y, idc_st_z, idc_sts
1115 
 
1116 
-- RAMADR MUX
1117 
ramadr_reg_in <= sph_out_cml_1&spl_out_cml_1 when
1118 
  (idc_rcall_cml_1 or (rcall_st1_cml_1 and not cpuwait_cml_1)or idc_icall_cml_1 or (icall_st1_cml_1 and not cpuwait_cml_1)or  -- RCALL/ICALL
1119 
   call_st1_cml_1  or (call_st2_cml_1 and not cpuwait_cml_1) or irq_st1_cml_1   or (irq_st2_cml_1 and not cpuwait_cml_1)  or  -- CALL/IRQ
1120 
   idc_push_cml_1 )='1' else                                                                      -- PUSH
1121 
   (sph_out_cml_1&spl_out_cml_1)+1 when (idc_ret_cml_1 or (ret_st1_cml_1 and not cpuwait_cml_1)  or idc_reti_cml_1  or (reti_st1_cml_1 and not cpuwait_cml_1) or idc_pop_cml_1)='1' else  -- RET/RETI/POP
1122 
   inst_cml_1 when (idc_lds_cml_1 or idc_sts_cml_1) ='1' else     -- LDS/STS (two cycle execution)
1123 
   reg_h_out when (idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ld_z_cml_1 or idc_st_x_cml_1 or idc_st_y_cml_1 or idc_st_z_cml_1)='1' else  -- LD/ST
1124 
   (reg_h_out + ("000000000"&dex_adr_disp));                                                       -- LDD/STD
1125 
 
1126 
 
1127 
-- SynEDA CoreMultiplier
1128 
-- assignment(s): ramadr_int
1129 
-- replace(s): ramadr_int
1130 
 
1131 
-- ADDRESS REGISTER
1132 
ramadr_reg:process(cp2,ireset)
1133 
begin
1134 
if ireset='0' then
1135 
ramadr_int <= (others => '0');
1136 
elsif(cp2='1' and cp2'event) then ramadr_int <= ramadr_int_cml_1;
1137 
 if (cp2en='1') then                                                      -- Clock enable
1138 
  if (ramadr_reg_en='1') then
1139 
   ramadr_int <= ramadr_reg_in;
1140 
  end if;
1141 
 end if;
1142 
end if;
1143 
end process;
1144 
 
1145 
ramadr <= ramadr_int;
1146 
 
1147 
-- SynEDA CoreMultiplier
1148 
-- assignment(s): reg_file_adr_space
1149 
-- replace(s): reg_file_adr_space
1150 
 
1151 
-- GENERAL PURPOSE REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS
1152 
gp_reg_adr:process(cp2,ireset)
1153 
begin
1154 
if ireset='0' then
1155 
reg_file_adr_space <='0';
1156 
elsif(cp2='1' and cp2'event) then reg_file_adr_space <= reg_file_adr_space_cml_1;
1157 
 if (cp2en='1') then                                                      -- Clock enable
1158 
  if (ramadr_reg_en='1') then
1159 
   if (ramadr_reg_in(15 downto 5)=const_ram_to_reg) then
1160 
    reg_file_adr_space <= '1';                             -- ADRESS RANGE 0x0000-0x001F -> REGISTERS (R0-R31)
1161 
   else
1162 
    reg_file_adr_space <= '0';
1163 
   end if;
1164 
  end if;
1165 
 end if;
1166 
end if;
1167 
end process;
1168 
 
1169 
-- SynEDA CoreMultiplier
1170 
-- assignment(s): io_file_adr_space
1171 
-- replace(s): io_file_adr_space
1172 
 
1173 
-- I/O REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS
1174 
io_reg_adr:process(cp2,ireset)
1175 
begin
1176 
if ireset='0' then io_file_adr_space<='0';
1177 
elsif(cp2='1' and cp2'event) then io_file_adr_space <= io_file_adr_space_cml_1;
1178 
 if (cp2en='1') then                                                      -- Clock enable
1179 
  if (ramadr_reg_en='1') then
1180 
   if (ramadr_reg_in(15 downto 5)=const_ram_to_io_a or ramadr_reg_in(15 downto 5)=const_ram_to_io_b) then
1181 
    io_file_adr_space <= '1';                             -- ADRESS RANGE 0x0020-0x005F -> I/O PORTS (0x00-0x3F)
1182 
   else
1183 
    io_file_adr_space <= '0';
1184 
   end if;
1185 
  end if;
1186 
 end if;
1187 
end if;
1188 
end process;
1189 
 
1190 
 
1191 
 
1192 
-- ##########################################################################################################
1193 
 
1194 
 
1195 
-- REGRE/REGWE LOGIC (5 BIT ADDSRESS BUS (INTERNAL ONLY) 32 LOCATIONS (R0-R31))
1196 
 
1197 
-- SynEDA CoreMultiplier
1198 
-- assignment(s): alu_reg_wr
1199 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_adiw, idc_and, idc_andi, idc_asr, idc_com, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi, idc_swap
1200 
 
1201 
-- WRITE ENABLE FOR Rd REGISTERS
1202 
alu_reg_wr <= idc_adc_cml_1 or idc_add_cml_1 or idc_adiw_cml_1 or adiw_st_cml_1 or idc_sub_cml_1 or idc_subi_cml_1 or idc_sbc_cml_1 or idc_sbci_cml_1 or
1203 
              idc_sbiw_cml_1 or  sbiw_st_cml_1 or idc_and_cml_1 or idc_andi_cml_1 or idc_or_cml_1 or idc_ori_cml_1 or idc_eor_cml_1 or idc_com_cml_1 or
1204 
                          idc_neg_cml_1 or idc_inc_cml_1 or idc_dec_cml_1 or idc_lsr_cml_1 or idc_ror_cml_1 or idc_asr_cml_1 or idc_swap_cml_1;
1205 
 
1206 
 
1207 
-- SynEDA CoreMultiplier
1208 
-- assignment(s): reg_rd_wr
1209 
-- replace(s): reg_file_adr_space, lpm_st2, sts_st, lds_st, st_st, ld_st, pop_st, idc_in, idc_ldi
1210 
 
1211 
reg_rd_wr_cml_out <= idc_in_cml_1 or alu_reg_wr or idc_bld or             -- ALU INSTRUCTIONS + IN/BLD INSRTRUCTION
1212 
 (pop_st_cml_1 or ld_st_cml_1 or lds_st_cml_1)or                                            -- POP/LD/LDD/LDS INSTRUCTIONS
1213 
 ((st_st_cml_1 or sts_st_cml_1) and reg_file_adr_space_cml_1)or              -- ST/STD/STS INSTRUCTION
1214 
  lpm_st2_cml_1 or idc_ldi_cml_1 or idc_mov;                            -- LPM/LDI/MOV INSTRUCTION
1215 
 
1216 
 
1217 
  reg_rd_adr <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else
1218 
                           "00000" when lpm_st2='1' else
1219 
               adiw_sbiw_encoder_out     when (idc_adiw or idc_sbiw)='1' else
1220 
               adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else
1221 
                           dex_adrreg_d_latched      when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else
1222 
               ramadr_int(4 downto 0)    when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
1223 
                           dex_adrreg_d;
1224 
 
1225 
  reg_rd_adr_int <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else
1226 
                           "00000" when lpm_st2='1' else
1227 
               adiw_sbiw_encoder_out     when (idc_adiw or idc_sbiw)='1' else
1228 
               adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else
1229 
                           dex_adrreg_d_latched      when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else
1230 
               ramadr_int(4 downto 0)    when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
1231 
                           dex_adrreg_d;
1232 
 
1233 
reg_rr_adr <= ramadr_int(4 downto 0) when ((ld_st or lds_st) and reg_file_adr_space)='1'else --!!??
1234 
                  dex_adrreg_d_latched   when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
1235 
                  dex_adrreg_r;
1236 
 
1237 
-- SynEDA CoreMultiplier
1238 
-- assignment(s): reg_rd_in
1239 
-- replace(s): reg_rr_out, reg_file_adr_space, lpm_st2, sts_st, lds_st, st_st, ld_st, pop_st, instruction_reg, dex_dat8_immed, gp_reg_tmp, idc_in, idc_ldi
1240 
 
1241 
-- MULTIPLEXER FOR REGISTER FILE Rd INPUT
1242 
reg_rd_in_cml_out <= dbusin when (idc_in_cml_1 or ((lds_st_cml_1 or ld_st_cml_1)and not reg_file_adr_space_cml_1) or pop_st_cml_1)='1' else -- FROM INPUT DATA BUS
1243 
                         reg_rr_out_cml_1 when ((lds_st_cml_1 or ld_st_cml_1)  and reg_file_adr_space_cml_1)='1' else
1244 
             gp_reg_tmp_cml_1 when ((st_st_cml_1 or sts_st_cml_1)  and reg_file_adr_space_cml_1)='1' else -- ST/STD/STS &  ADDRESS FROM 0 TO 31 (REGISTER FILE)
1245 
                         bld_op_out when (idc_bld='1')else                                     -- FROM BIT PROCESSOR BLD COMMAND
1246 
             reg_rr_out_cml_1 when (idc_mov='1')else                                     -- FOR MOV INSTRUCTION
1247 
                         instruction_reg_cml_1(15 downto 8) when (lpm_st2_cml_1='1' and reg_z_out(0)='1') else -- LPM/ELPM
1248 
                         instruction_reg_cml_1(7 downto 0) when  (lpm_st2_cml_1='1' and reg_z_out(0)='0') else -- LPM/ELPM
1249 
             dex_dat8_immed_cml_1 when idc_ldi_cml_1='1' else
1250 
                         alu_data_out;                                               -- FROM ALU DATA OUT
1251 
 
1252 
-- IORE/IOWE LOGIC (6 BIT ADDRESS adr[5..0] FOR I/O PORTS(64 LOCATIONS))
1253 
iore_int <= idc_in or idc_sbi or idc_cbi or idc_sbic or idc_sbis or ((ld_st or lds_st) and io_file_adr_space);   -- IN/SBI/CBI
1254 
iowe_int <= '1' when ((idc_out or sbi_st or cbi_st) or
1255 
                     ((st_st or sts_st) and io_file_adr_space))='1' else '0'; -- OUT/SBI/CBI + !! ST/STS/STD
1256 
 
1257 
 
1258 
-- adr[5..0] BUS MULTIPLEXER
1259 
adr_int <= dex_adr6port when (idc_in or idc_out) = '1' else                          -- IN/OUT INSTRUCTIONS
1260 
           '0'&dex_adr5port when (idc_cbi or idc_sbi or idc_sbic or idc_sbis) ='1'    else  -- CBI/SBI (READ PHASE) + SBIS/SBIC
1261 
                   '0'&cbi_sbi_io_adr_tmp when (cbi_st or sbi_st)='1' else       -- CBI/SBI (WRITE PHASE)
1262 
                    ramadr_int(6)&ramadr_int(4 downto 0);                                                   -- LD/LDS/LDD/ST/STS/STD
1263 
 
1264 
-- ramre LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS))
1265 
--ramre_int <= not(reg_file_adr_space or io_file_adr_space) and
1266 
--            (ld_st or lds_st2 or pop_st or                    -- LD/LDD/LDS/POP/
1267 
--             ret_st1 or ret_st2 or reti_st1 or reti_st2);     -- RET/RETI
1268 
 
1269 
-- SynEDA CoreMultiplier
1270 
-- assignment(s): ramre_int
1271 
-- replace(s): cpuwait, ret_st2, reti_st2, lds_st, ld_st, pop_st, ramre_int, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_ret, idc_reti
1272 
 
1273 
DataMemoryRead:process(cp2,ireset)
1274 
begin
1275 
if ireset='0' then -- Reset
1276 
 ramre_int <= '0';
1277 
elsif (cp2='1' and cp2'event) then ramre_int <= ramre_int_cml_1; -- Clock
1278 
 if (cp2en='1') then                                                      -- Clock enable
1279 
  case ramre_int_cml_1 is
1280 
   when '0' =>
1281 
    if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and
1282 
           ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and
1283 
       ramadr_reg_in(15 downto 5)/=const_ram_to_reg  and
1284 
      (idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ldd_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_z_cml_1 or  -- LD/LDD instruction
1285 
           idc_lds_cml_1 or                                                     -- LDS instruction(two cycle execution)
1286 
           idc_pop_cml_1 or                                                     -- POP instruction
1287 
       idc_ret_cml_1 or                                                         -- RET instruction
1288 
           idc_reti_cml_1)='1')                                                                                                     -- RETI instruction
1289 
           then ramre_int <='1';
1290 
    end if;
1291 
   when '1' =>
1292 
    if ((ld_st_cml_1 or lds_st_cml_1 or pop_st_cml_1 or ret_st2_cml_1 or reti_st2_cml_1)and not cpuwait_cml_1)='1' then
1293 
     ramre_int <='0';
1294 
    end if;
1295 
   when others  =>      null;
1296 
  end case;
1297 
 end if;
1298 
end if;
1299 
end process;
1300 
 
1301 
-- ramwe LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS))
1302 
--ramwe_int <= not(reg_file_adr_space or io_file_adr_space) and
1303 
--            (st_st or sts_st2 or push_st or rcall_st1 or rcall_st2 or -- ST/STD/STS/PUSH/RCALL
1304 
--                                                      icall_st1 or icall_st2 or -- ICALL
1305 
--                                                      call_st2 or call_st3 or   -- CALL
1306 
--                                                                                      irq_st2 or irq_st3);      -- INTERRUPT
1307 
 
1308 
-- SynEDA CoreMultiplier
1309 
-- assignment(s): ramwe_int
1310 
-- replace(s): cpuwait, irq_st1, irq_st3, call_st1, call_st3, rcall_st2, icall_st2, sts_st, st_st, push_st, ramwe_int, idc_icall, idc_push, idc_rcall, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1311 
 
1312 
DataMemoryWrite:process(cp2,ireset)
1313 
begin
1314 
if ireset='0' then -- Reset
1315 
 ramwe_int <= '0';
1316 
elsif (cp2='1' and cp2'event) then ramwe_int <= ramwe_int_cml_1; -- Clock
1317 
 if (cp2en='1') then                                                      -- Clock enable
1318 
  case ramwe_int_cml_1 is
1319 
   when '0' =>
1320 
    if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and
1321 
           ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and
1322 
       ramadr_reg_in(15 downto 5)/=const_ram_to_reg  and
1323 
      (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1 or  -- ST/STD instruction
1324 
           idc_sts_cml_1 or                                                     -- STS instruction (two cycle execution)
1325 
           idc_push_cml_1 or                                                    -- PUSH instruction
1326 
           idc_rcall_cml_1 or                                                                                                     -- RCALL instruction
1327 
           idc_icall_cml_1 or                                                                                                     -- ICALL instruction
1328 
           call_st1_cml_1 or                                                    -- CALL instruction
1329 
           irq_st1_cml_1)='1')                                                  -- Interrupt
1330 
          then ramwe_int <='1';
1331 
    end if;
1332 
   when '1' =>
1333 
    if ((st_st_cml_1 or sts_st_cml_1 or push_st_cml_1 or rcall_st2_cml_1 or
1334 
             icall_st2_cml_1 or call_st3_cml_1 or irq_st3_cml_1)and not cpuwait_cml_1)='1' then ramwe_int <='0';
1335 
    end if;
1336 
   when others  =>      null;
1337 
  end case;
1338 
end if;
1339 
end if;
1340 
end process;
1341 
 
1342 
-- DBUSOUT MULTIPLEXER
1343 
--dbusout_mux_logic: for i in dbusout_int'range generate
1344 
--dbusout_int(i)<= (reg_rd_out(i) and (idc_push or idc_sts or
1345 
--                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1346 
--                               (gp_reg_tmp(i) and (st_st or sts_st))or                            -- NEW
1347 
--                               (bitpr_io_out(i) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1348 
--                 (program_counter(i)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC                 (program_counter_high_fr(i) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1349 
--                 (pc_for_interrupt(i) and irq_st1) or
1350 
--                               (pc_for_interrupt(8) and irq_st2) or
1351 
--                               (reg_rd_out(i) and  idc_out); -- OUT
1352 
--end generate;
1353 
 
1354 
dbusout_int(0)<= (reg_rd_out_cml_1(0) and (idc_push_cml_1 or idc_sts_cml_1 or
1355 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1356 
                                 (gp_reg_tmp_cml_1(0) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1357 
                                 (bitpr_io_out_cml_1(0) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1358 
                 (program_counter_cml_1(0)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1359 
                 (program_counter_high_fr_cml_1(0) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1360 
                 (pc_for_interrupt_cml_1(0) and irq_st1_cml_1) or
1361 
                                 (pc_for_interrupt_cml_1(8) and irq_st2_cml_1) or
1362 
                                 (reg_rd_out_cml_1(0) and  idc_out_cml_1); -- OUT
1363 
 
1364 
dbusout_int(1)<= (reg_rd_out_cml_1(1) and (idc_push_cml_1 or idc_sts_cml_1 or
1365 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1366 
                                 (gp_reg_tmp_cml_1(1) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1367 
                                 (bitpr_io_out_cml_1(1) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1368 
                 (program_counter_cml_1(1)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1369 
                 (program_counter_high_fr_cml_1(1) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1370 
                 (pc_for_interrupt_cml_1(1) and irq_st1_cml_1) or
1371 
                                 (pc_for_interrupt_cml_1(9) and irq_st2_cml_1) or
1372 
                                 (reg_rd_out_cml_1(1) and  idc_out_cml_1); -- OUT
1373 
 
1374 
dbusout_int(2)<= (reg_rd_out_cml_1(2) and (idc_push_cml_1 or idc_sts_cml_1 or
1375 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1376 
                                 (gp_reg_tmp_cml_1(2) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1377 
                                 (bitpr_io_out_cml_1(2) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1378 
                 (program_counter_cml_1(2)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1379 
                 (program_counter_high_fr_cml_1(2) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1380 
                 (pc_for_interrupt_cml_1(2) and irq_st1_cml_1) or
1381 
                                 (pc_for_interrupt_cml_1(10) and irq_st2_cml_1) or
1382 
                                 (reg_rd_out_cml_1(2) and  idc_out_cml_1); -- OUT
1383 
 
1384 
dbusout_int(3)<= (reg_rd_out_cml_1(3) and (idc_push_cml_1 or idc_sts_cml_1 or
1385 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1386 
                                 (gp_reg_tmp_cml_1(3) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1387 
                                 (bitpr_io_out_cml_1(3) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1388 
                 (program_counter_cml_1(3)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1389 
                 (program_counter_high_fr_cml_1(3) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1390 
                 (pc_for_interrupt_cml_1(3) and irq_st1_cml_1) or
1391 
                                 (pc_for_interrupt_cml_1(11) and irq_st2_cml_1) or
1392 
                                 (reg_rd_out_cml_1(3) and  idc_out_cml_1); -- OUT
1393 
 
1394 
dbusout_int(4)<= (reg_rd_out_cml_1(4) and (idc_push_cml_1 or idc_sts_cml_1 or
1395 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1396 
                                 (gp_reg_tmp_cml_1(4) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1397 
                                 (bitpr_io_out_cml_1(4) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1398 
                 (program_counter_cml_1(4)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1399 
                 (program_counter_high_fr_cml_1(4) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1400 
                 (pc_for_interrupt_cml_1(4) and irq_st1_cml_1) or
1401 
                                 (pc_for_interrupt_cml_1(12) and irq_st2_cml_1) or
1402 
                                 (reg_rd_out_cml_1(4) and  idc_out_cml_1); -- OUT
1403 
 
1404 
dbusout_int(5)<= (reg_rd_out_cml_1(5) and (idc_push_cml_1 or idc_sts_cml_1 or
1405 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1406 
                                 (gp_reg_tmp_cml_1(5) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1407 
                                 (bitpr_io_out_cml_1(5) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1408 
                 (program_counter_cml_1(5)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1409 
                 (program_counter_high_fr_cml_1(5) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1410 
                 (pc_for_interrupt_cml_1(5) and irq_st1_cml_1) or
1411 
                                 (pc_for_interrupt_cml_1(13) and irq_st2_cml_1) or
1412 
                                 (reg_rd_out_cml_1(5) and  idc_out_cml_1); -- OUT
1413 
 
1414 
dbusout_int(6)<= (reg_rd_out_cml_1(6) and (idc_push_cml_1 or idc_sts_cml_1 or
1415 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1416 
                                 (gp_reg_tmp_cml_1(6) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1417 
                                 (bitpr_io_out_cml_1(6) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1418 
                 (program_counter_cml_1(6)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1419 
                 (program_counter_high_fr_cml_1(6) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1420 
                 (pc_for_interrupt_cml_1(6) and irq_st1_cml_1) or
1421 
                                 (pc_for_interrupt_cml_1(14) and irq_st2_cml_1) or
1422 
                                 (reg_rd_out_cml_1(6) and  idc_out_cml_1); -- OUT
1423 
 
1424 
-- SynEDA CoreMultiplier
1425 
-- assignment(s): dbusout_int
1426 
-- replace(s): reg_rd_out, bitpr_io_out, program_counter, program_counter_high_fr, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, sts_st, st_st, sbi_st, cbi_st, pc_for_interrupt, gp_reg_tmp, idc_icall, idc_out, idc_push, idc_rcall, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1427 
 
1428 
dbusout_int(7)<= (reg_rd_out_cml_1(7) and (idc_push_cml_1 or idc_sts_cml_1 or
1429 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1430 
                                 (gp_reg_tmp_cml_1(7) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1431 
                                 (bitpr_io_out_cml_1(7) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1432 
                 (program_counter_cml_1(7)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1433 
                 (program_counter_high_fr_cml_1(7) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1434 
                 (pc_for_interrupt_cml_1(7) and irq_st1_cml_1) or
1435 
                                 (pc_for_interrupt_cml_1(15) and irq_st2_cml_1) or
1436 
                                 (reg_rd_out_cml_1(7) and  idc_out_cml_1); -- OUT
1437 
 
1438 
dbusout_int_route <= dbusout_int;
1439 
 
1440 
dbusout(0)<= (reg_rd_out_int(0) and (idc_push or idc_sts or
1441 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1442 
                                 (gp_reg_tmp(0) and (st_st or sts_st))or                            -- NEW
1443 
                                 (bitpr_io_out(0) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1444 
                 (program_counter(0)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1445 
                 (program_counter_high_fr(0) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1446 
                 (pc_for_interrupt(0) and irq_st1) or
1447 
                                 (pc_for_interrupt(8) and irq_st2) or
1448 
                                 (reg_rd_out_int(0) and  idc_out); -- OUT
1449 
 
1450 
dbusout(1)<= (reg_rd_out_int(1) and (idc_push or idc_sts or
1451 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1452 
                                 (gp_reg_tmp(1) and (st_st or sts_st))or                            -- NEW
1453 
                                 (bitpr_io_out(1) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1454 
                 (program_counter(1)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1455 
                 (program_counter_high_fr(1) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1456 
                 (pc_for_interrupt(1) and irq_st1) or
1457 
                                 (pc_for_interrupt(9) and irq_st2) or
1458 
                                 (reg_rd_out_int(1) and  idc_out); -- OUT
1459 
 
1460 
dbusout(2)<= (reg_rd_out_int(2) and (idc_push or idc_sts or
1461 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1462 
                                 (gp_reg_tmp(2) and (st_st or sts_st))or                            -- NEW
1463 
                                 (bitpr_io_out(2) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1464 
                 (program_counter(2)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1465 
                 (program_counter_high_fr(2) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1466 
                 (pc_for_interrupt(2) and irq_st1) or
1467 
                                 (pc_for_interrupt(10) and irq_st2) or
1468 
                                 (reg_rd_out_int(2) and  idc_out); -- OUT
1469 
 
1470 
dbusout(3)<= (reg_rd_out_int(3) and (idc_push or idc_sts or
1471 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1472 
                                 (gp_reg_tmp(3) and (st_st or sts_st))or                            -- NEW
1473 
                                 (bitpr_io_out(3) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1474 
                 (program_counter(3)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1475 
                 (program_counter_high_fr(3) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1476 
                 (pc_for_interrupt(3) and irq_st1) or
1477 
                                 (pc_for_interrupt(11) and irq_st2) or
1478 
                                 (reg_rd_out_int(3) and  idc_out); -- OUT
1479 
 
1480 
dbusout(4)<= (reg_rd_out_int(4) and (idc_push or idc_sts or
1481 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1482 
                                 (gp_reg_tmp(4) and (st_st or sts_st))or                            -- NEW
1483 
                                 (bitpr_io_out(4) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1484 
                 (program_counter(4)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1485 
                 (program_counter_high_fr(4) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1486 
                 (pc_for_interrupt(4) and irq_st1) or
1487 
                                 (pc_for_interrupt(12) and irq_st2) or
1488 
                                 (reg_rd_out_int(4) and  idc_out); -- OUT
1489 
 
1490 
dbusout(5)<= (reg_rd_out_int(5) and (idc_push or idc_sts or
1491 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1492 
                                 (gp_reg_tmp(5) and (st_st or sts_st))or                            -- NEW
1493 
                                 (bitpr_io_out(5) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1494 
                 (program_counter(5)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1495 
                 (program_counter_high_fr(5) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1496 
                 (pc_for_interrupt(5) and irq_st1) or
1497 
                                 (pc_for_interrupt(13) and irq_st2) or
1498 
                                 (reg_rd_out_int(5) and  idc_out); -- OUT
1499 
 
1500 
dbusout(6)<= (reg_rd_out_int(6) and (idc_push or idc_sts or
1501 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1502 
                                 (gp_reg_tmp(6) and (st_st or sts_st))or                            -- NEW
1503 
                                 (bitpr_io_out(6) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1504 
                 (program_counter(6)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1505 
                 (program_counter_high_fr(6) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1506 
                 (pc_for_interrupt(6) and irq_st1) or
1507 
                                 (pc_for_interrupt(14) and irq_st2) or
1508 
                                 (reg_rd_out_int(6) and  idc_out); -- OUT
1509 
 
1510 
dbusout(7)<= (reg_rd_out_int(7) and (idc_push or idc_sts or
1511 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1512 
                                 (gp_reg_tmp(7) and (st_st or sts_st))or                            -- NEW
1513 
                                 (bitpr_io_out(7) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1514 
                 (program_counter(7)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1515 
                 (program_counter_high_fr(7) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1516 
                 (pc_for_interrupt(7) and irq_st1) or
1517 
                                 (pc_for_interrupt(15) and irq_st2) or
1518 
                                 (reg_rd_out_int(7) and  idc_out); -- OUT
1519 
 
1520 
 
1521 
-- ALU CONNECTION
1522 
 
1523 
-- ALU Rr INPUT MUX
1524 
alu_data_r_in <= dex_dat8_immed       when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi)='1' else
1525 
                 "00"&dex_dat6_immed  when (idc_adiw or idc_sbiw) ='1' else
1526 
                 "00000000"           when (adiw_st or sbiw_st) ='1' else
1527 
                 reg_rr_out;
1528 
 
1529 
 
1530 
-- SynEDA CoreMultiplier
1531 
-- assignment(s): gp_reg_tmp
1532 
-- replace(s): reg_rd_out, gp_reg_tmp, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1533 
 
1534 
-- gp_reg_tmp STORES TEMPREOARY THE VALUE OF SOURCE REGISTER DURING ST/STD/STS INSTRUCTION
1535 
gp_registers_trig:process(cp2,ireset)
1536 
begin
1537 
if (ireset='0') then
1538 
gp_reg_tmp <= (others=>'0');
1539 
elsif (cp2='1' and cp2'event) then gp_reg_tmp <= gp_reg_tmp_cml_1;
1540 
 if (cp2en='1') then                                                      -- Clock enable
1541 
  -- if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or sts_st1)='1' then  -- CLOCK ENABLE
1542 
  if ((idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1) or idc_sts_cml_1)='1' then  -- CLOCK ENABLE
1543 
     gp_reg_tmp <= reg_rd_out_cml_1;
1544 
  end if;
1545 
 end if;
1546 
end if;
1547 
end process;
1548 
 
1549 
-- **********************************************************************************************************
1550 
 
1551 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1552 
-- +++++++++++++++++++++++++++++++++++++++ PROGRAM COUNTER ++++++++++++++++++++++++++++++++++++++++++++++++++
1553 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1554 
 
1555 
-- SynEDA CoreMultiplier
1556 
-- assignment(s): program_counter_high_fr
1557 
-- replace(s): program_counter, program_counter_high_fr, irq_st1, call_st1, idc_icall, idc_rcall
1558 
 
1559 
program_counter_high_store:process(cp2,ireset)
1560 
begin
1561 
if ireset='0' then                         -- RESET
1562 
program_counter_high_fr <=(others => '0');
1563 
elsif (cp2='1' and cp2'event) then program_counter_high_fr <= program_counter_high_fr_cml_1;       -- CLOCK
1564 
 if (cp2en='1') then                                                      -- Clock enable
1565 
  if (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1 or irq_st1_cml_1) ='1' then
1566 
   program_counter_high_fr <= program_counter_cml_1(15 downto 8);       -- STORE HIGH BYTE OF THE PROGRAMM COUNTER FOR RCALL/ICALL/CALL INSTRUCTIONS AND INTERRUPTS
1567 
  end if;
1568 
 end if;
1569 
end if;
1570 
end process;
1571 
 
1572 
 
1573 
-- SynEDA CoreMultiplier
1574 
-- assignment(s): program_counter_tmp
1575 
-- replace(s): program_counter_tmp, program_counter, idc_elpm, idc_lpm
1576 
 
1577 
program_counter_for_lpm_elpm:process(cp2,ireset)
1578 
begin
1579 
if ireset='0' then                         -- RESET
1580 
program_counter_tmp<=(others => '0');
1581 
elsif (cp2='1' and cp2'event) then program_counter_tmp <= program_counter_tmp_cml_1;       -- CLOCK
1582 
 if (cp2en='1') then                                                      -- Clock enable
1583 
  if (idc_lpm_cml_1 or idc_elpm_cml_1) ='1' then
1584 
   program_counter_tmp <= program_counter_cml_1;
1585 
  end if;
1586 
 end if;
1587 
end if;
1588 
end process;
1589 
 
1590 
-- SynEDA CoreMultiplier
1591 
-- assignment(s): pa15_pm
1592 
-- replace(s): rampz_out, idc_elpm
1593 
 
1594 
pa15_pm <= rampz_out_cml_1(0) and idc_elpm_cml_1; -- '0' WHEN LPM INSTRUCTIONS  RAMPZ(0) WHEN ELPM INSTRUCTION
1595 
 
1596 
-- OFFSET FOR BRBC/BRBS INSTRUCTIONS +63/-64
1597 
offset_brbx <= "0000000000"&dex_brxx_offset(5 downto 0) when (dex_brxx_offset(6)='0') else -- +
1598 
               "1111111111"&dex_brxx_offset(5 downto 0);                                   -- -
1599 
 
1600 
-- OFFSET FOR RJMP/RCALL INSTRUCTIONS +2047/-2048
1601 
offset_rxx <= "00000"&dex_adr12mem_s(10 downto 0) when (dex_adr12mem_s(11)='0') else       -- +
1602 
              "11111"&dex_adr12mem_s(10 downto 0);                                          -- -
1603 
 
1604 
program_counter <= pc_high&pc_low;
1605 
 
1606 
-- SynEDA CoreMultiplier
1607 
-- assignment(s): program_counter_in
1608 
-- replace(s): irqackad_int, program_counter_tmp, program_counter, irq_st1, call_st1, jmp_st1, ret_st1, ret_st2, reti_st1, reti_st2, lpm_st1, instruction_reg, idc_brbc, idc_brbs, idc_elpm, idc_icall, idc_ijmp, idc_lpm, idc_rcall, idc_rjmp
1609 
 
1610 
program_counter_in <= program_counter_cml_1 + offset_brbx when ((idc_brbc_cml_1 or idc_brbs_cml_1) and  bit_test_op_out) ='1'else  -- BRBC/BRBS
1611 
                      program_counter_cml_1 + offset_rxx when (idc_rjmp_cml_1 or idc_rcall_cml_1)='1'else     -- RJMP/RCALL
1612 
                      reg_z_out when (idc_ijmp_cml_1 or idc_icall_cml_1)='1'else                        -- IJMP/ICALL
1613 
                      pa15_pm&reg_z_out(15 downto 1) when (idc_lpm_cml_1 or idc_elpm_cml_1) ='1'else    -- LPM/ELPM
1614 
                      instruction_reg_cml_1  when (jmp_st1_cml_1 or call_st1_cml_1)='1'else                    -- JMP/CALL
1615 
                      "0000000000"&irqackad_int_cml_1&'0' when irq_st1_cml_1 ='1' else                 -- INTERRUPT
1616 
                      dbusin&"00000000"  when (ret_st1_cml_1 or reti_st1_cml_1)='1' else                 -- RET/RETI -> PC HIGH BYTE
1617 
                      "00000000"&dbusin  when (ret_st2_cml_1 or reti_st2_cml_1)='1' else                 -- RET/RETI -> PC LOW BYTE
1618 
                      program_counter_tmp_cml_1 when (lpm_st1_cml_1)='1'                                 -- AFTER LPM/ELPM INSTRUCTION
1619 
                      else program_counter_cml_1+1;      -- THE MOST USUAL CASE
1620 
 
1621 
 
1622 
 
1623 
-- SynEDA CoreMultiplier
1624 
-- assignment(s): pc_low_en
1625 
-- replace(s): cpuwait, irq_st2, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, sts_st, lds_st, idc_adiw, idc_cbi, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_pop, idc_push, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
1626 
 
1627 
pc_low_en  <= not (idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_y_cml_1 or idc_ldd_z_cml_1 or
1628 
                       idc_st_x_cml_1 or idc_st_y_cml_1 or idc_st_z_cml_1 or idc_std_y_cml_1 or idc_std_z_cml_1 or
1629 
                                   ((sts_st_cml_1 or lds_st_cml_1) and cpuwait_cml_1)or
1630 
                                   idc_adiw_cml_1 or idc_sbiw_cml_1 or
1631 
                                   idc_push_cml_1 or idc_pop_cml_1 or
1632 
                                   idc_cbi_cml_1 or idc_sbi_cml_1 or
1633 
                                   rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1 or irq_st2_cml_1 or cpuwait_cml_1 or
1634 
                                   ret_st1_cml_1 or reti_st1_cml_1);
1635 
 
1636 
 
1637 
-- SynEDA CoreMultiplier
1638 
-- assignment(s): pc_high_en
1639 
-- replace(s): cpuwait, irq_st2, call_st2, rcall_st1, icall_st1, ret_st2, reti_st2, sts_st, lds_st, idc_adiw, idc_cbi, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_pop, idc_push, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
1640 
 
1641 
pc_high_en <= not (idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_y_cml_1 or idc_ldd_z_cml_1 or
1642 
                       idc_st_x_cml_1 or idc_st_y_cml_1 or idc_st_z_cml_1 or idc_std_y_cml_1 or idc_std_z_cml_1 or
1643 
                                   ((sts_st_cml_1 or lds_st_cml_1) and cpuwait_cml_1) or
1644 
                                   idc_adiw_cml_1 or idc_sbiw_cml_1 or
1645 
                                   idc_push_cml_1 or idc_pop_cml_1 or
1646 
                                   idc_cbi_cml_1 or idc_sbi_cml_1 or
1647 
                                   rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1 or irq_st2_cml_1 or cpuwait_cml_1 or
1648 
                                   ret_st2_cml_1 or reti_st2_cml_1);
1649 
 
1650 
-- SynEDA CoreMultiplier
1651 
-- assignment(s): pc_low
1652 
-- replace(s): pc_low
1653 
 
1654 
program_counter_low:process(cp2,ireset)
1655 
begin
1656 
if ireset='0' then                              -- RESET
1657 
pc_low<=(others => '0');
1658 
elsif (cp2='1' and cp2'event) then pc_low <= pc_low_cml_1;              -- CLOCK
1659 
 if (cp2en='1') then                                                    -- Clock enable
1660 
  if pc_low_en ='1' then
1661 
   pc_low <= program_counter_in(7 downto 0);
1662 
  end if;
1663 
 end if;
1664 
end if;
1665 
end process;
1666 
 
1667 
-- SynEDA CoreMultiplier
1668 
-- assignment(s): pc_high
1669 
-- replace(s): pc_high
1670 
 
1671 
program_counter_high:process(cp2,ireset)
1672 
begin
1673 
if ireset='0' then                               -- RESET
1674 
pc_high<=(others => '0');
1675 
elsif (cp2='1' and cp2'event) then pc_high <= pc_high_cml_1;               -- CLOCK
1676 
 if (cp2en='1') then                                                     -- Clock enable
1677 
  if pc_high_en ='1' then
1678 
   pc_high <= program_counter_in(15 downto 8);
1679 
  end if;
1680 
 end if;
1681 
end if;
1682 
end process;
1683 
 
1684 
pc <= program_counter;
1685 
 
1686 
 
1687 
-- SynEDA CoreMultiplier
1688 
-- assignment(s): pc_for_interrupt
1689 
-- replace(s): program_counter, pc_for_interrupt
1690 
 
1691 
program_counter_for_interrupt:process(cp2,ireset)
1692 
begin
1693 
if ireset='0' then                                 -- RESET
1694 
pc_for_interrupt <=(others => '0');
1695 
elsif (cp2='1' and cp2'event) then pc_for_interrupt <= pc_for_interrupt_cml_1;               -- CLOCK
1696 
 if (cp2en='1') then                                                     -- Clock enable
1697 
  if irq_start ='1' then
1698 
   pc_for_interrupt <= program_counter_cml_1;
1699 
  end if;
1700 
 end if;
1701 
end if;
1702 
end process;
1703 
 
1704 
-- END OF PROGRAM COUNTER
1705 
 
1706 
-- STATE MACHINES
1707 
 
1708 
-- SynEDA CoreMultiplier
1709 
-- assignment(s): skip_inst_start
1710 
-- replace(s): idc_cpse, idc_sbic, idc_sbis, idc_sbrc, idc_sbrs
1711 
 
1712 
skip_inst_start <= ((idc_sbrc_cml_1 or idc_sbrs_cml_1 or idc_sbic_cml_1 or idc_sbis_cml_1) and bit_test_op_out)or
1713 
                   (idc_cpse_cml_1 and alu_z_flag_out);
1714 
 
1715 
-- SynEDA CoreMultiplier
1716 
-- assignment(s): nskip_inst_st0, skip_inst_st1, skip_inst_st2
1717 
-- replace(s): two_word_inst, nskip_inst_st0, skip_inst_st1, skip_inst_st2
1718 
 
1719 
skip_instruction_sm:process(cp2,ireset)
1720 
begin
1721 
if ireset='0' then                       -- RESET
1722 
nskip_inst_st0 <= '0';
1723 
skip_inst_st1  <= '0';
1724 
skip_inst_st2  <= '0';
1725 
elsif (cp2='1' and cp2'event) then skip_inst_st2 <= skip_inst_st2_cml_1; skip_inst_st1 <= skip_inst_st1_cml_1; nskip_inst_st0 <= nskip_inst_st0_cml_1;       -- CLOCK
1726 
 if (cp2en='1') then                                 -- Clock enable
1727 
  nskip_inst_st0 <= (not nskip_inst_st0_cml_1 and skip_inst_start) or
1728 
                    (nskip_inst_st0_cml_1 and not((skip_inst_st1_cml_1 and not two_word_inst_cml_1) or skip_inst_st2_cml_1));
1729 
  skip_inst_st1  <= (not skip_inst_st1_cml_1 and not nskip_inst_st0_cml_1 and skip_inst_start);
1730 
  skip_inst_st2  <=  not skip_inst_st2_cml_1 and skip_inst_st1_cml_1 and two_word_inst_cml_1;
1731 
 end if;
1732 
end if;
1733 
end process;
1734 
 
1735 
 
1736 
 
1737 
-- SynEDA CoreMultiplier
1738 
-- assignment(s): adiw_st, sbiw_st
1739 
-- replace(s): adiw_st, idc_adiw, sbiw_st, idc_sbiw
1740 
 
1741 
alu_state_machines:process(cp2,ireset)
1742 
begin
1743 
if ireset='0' then                       -- RESET
1744 
adiw_st <= '0';
1745 
sbiw_st <= '0';
1746 
elsif (cp2='1' and cp2'event) then sbiw_st <= sbiw_st_cml_1; adiw_st <= adiw_st_cml_1;       -- CLOCK
1747 
 if (cp2en='1') then                                     -- Clock enable
1748 
  adiw_st <= not adiw_st_cml_1 and idc_adiw_cml_1;
1749 
  sbiw_st <= not sbiw_st_cml_1 and idc_sbiw_cml_1;
1750 
 end if;
1751 
end if;
1752 
end process;
1753 
 
1754 
 
1755 
-- SynEDA CoreMultiplier
1756 
-- assignment(s): nlpm_st0, lpm_st1, lpm_st2
1757 
-- replace(s): nlpm_st0, lpm_st2, idc_elpm, idc_lpm, lpm_st1
1758 
 
1759 
lpm_state_machine:process(cp2,ireset)
1760 
begin
1761 
if ireset='0' then                       -- RESET
1762 
nlpm_st0 <= '0';
1763 
lpm_st1 <= '0';
1764 
lpm_st2 <= '0';
1765 
elsif (cp2='1' and cp2'event) then lpm_st2 <= lpm_st2_cml_1; lpm_st1 <= lpm_st1_cml_1; nlpm_st0 <= nlpm_st0_cml_1;       -- CLOCK
1766 
 if (cp2en='1') then                                                      -- Clock enable
1767 
  nlpm_st0 <= (not nlpm_st0_cml_1 and (idc_lpm_cml_1 or idc_elpm_cml_1)) or (nlpm_st0_cml_1 and not lpm_st2_cml_1);
1768 
  lpm_st1  <= (not lpm_st1_cml_1 and not nlpm_st0_cml_1 and (idc_lpm_cml_1 or idc_elpm_cml_1)); -- ??
1769 
  lpm_st2  <=  not lpm_st2_cml_1 and lpm_st1_cml_1;
1770 
 end if;
1771 
end if;
1772 
end process;
1773 
 
1774 
 
1775 
-- SynEDA CoreMultiplier
1776 
-- assignment(s): lds_st
1777 
-- replace(s): cpuwait, lds_st, idc_lds
1778 
 
1779 
lds_state_machine:process(cp2,ireset)
1780 
begin
1781 
if ireset='0' then                       -- RESET
1782 
 lds_st <= '0';
1783 
elsif (cp2='1' and cp2'event) then lds_st <= lds_st_cml_1;       -- CLOCK
1784 
 if (cp2en='1') then                                                      -- Clock enable
1785 
  lds_st  <= (not lds_st_cml_1 and idc_lds_cml_1) or (lds_st_cml_1 and cpuwait_cml_1);
1786 
 end if;
1787 
end if;
1788 
end process;
1789 
 
1790 
 
1791 
-- SynEDA CoreMultiplier
1792 
-- assignment(s): sts_st
1793 
-- replace(s): cpuwait, sts_st, idc_sts
1794 
 
1795 
sts_state_machine:process(cp2,ireset)
1796 
begin
1797 
if ireset='0' then                       -- RESET
1798 
 sts_st <= '0';
1799 
elsif (cp2='1' and cp2'event) then sts_st <= sts_st_cml_1;       -- CLOCK
1800 
 if (cp2en='1') then                                                      -- Clock enable
1801 
  sts_st  <= (not sts_st_cml_1 and idc_sts_cml_1) or (sts_st_cml_1 and cpuwait_cml_1);
1802 
 end if;
1803 
end if;
1804 
end process;
1805 
 
1806 
-- SynEDA CoreMultiplier
1807 
-- assignment(s): njmp_st0, jmp_st1, jmp_st2
1808 
-- replace(s): njmp_st0, jmp_st2, idc_jmp, jmp_st1
1809 
 
1810 
jmp_state_machine:process(cp2,ireset)
1811 
begin
1812 
if ireset='0' then                       -- RESET
1813 
njmp_st0 <= '0';
1814 
jmp_st1 <= '0';
1815 
jmp_st2 <= '0';
1816 
elsif (cp2='1' and cp2'event) then jmp_st2 <= jmp_st2_cml_1; jmp_st1 <= jmp_st1_cml_1; njmp_st0 <= njmp_st0_cml_1;       -- CLOCK
1817 
 if (cp2en='1') then                                                      -- Clock enable
1818 
  njmp_st0 <= (not njmp_st0_cml_1 and idc_jmp_cml_1) or (njmp_st0_cml_1 and not jmp_st2_cml_1);
1819 
  jmp_st1  <= not jmp_st1_cml_1 and not njmp_st0_cml_1 and idc_jmp_cml_1; -- ??
1820 
  jmp_st2  <= not jmp_st2_cml_1 and jmp_st1_cml_1;
1821 
 end if;
1822 
end if;
1823 
end process;
1824 
 
1825 
-- SynEDA CoreMultiplier
1826 
-- assignment(s): nrcall_st0, rcall_st1, rcall_st2
1827 
-- replace(s): cpuwait, nrcall_st0, rcall_st2, idc_rcall, rcall_st1
1828 
 
1829 
rcall_state_machine:process(cp2,ireset)
1830 
begin
1831 
if ireset='0' then                       -- RESET
1832 
nrcall_st0 <= '0';
1833 
rcall_st1 <= '0';
1834 
rcall_st2 <= '0';
1835 
elsif (cp2='1' and cp2'event) then rcall_st2 <= rcall_st2_cml_1; rcall_st1 <= rcall_st1_cml_1; nrcall_st0 <= nrcall_st0_cml_1;       -- CLOCK
1836 
 if (cp2en='1') then                                                      -- Clock enable
1837 
  nrcall_st0 <= (not nrcall_st0_cml_1 and idc_rcall_cml_1) or (nrcall_st0_cml_1 and not (rcall_st2_cml_1 and not cpuwait_cml_1));
1838 
  rcall_st1  <= (not rcall_st1_cml_1 and not nrcall_st0_cml_1 and idc_rcall_cml_1) or (rcall_st1_cml_1 and cpuwait_cml_1);
1839 
  rcall_st2  <= (not rcall_st2_cml_1 and rcall_st1_cml_1 and not cpuwait_cml_1) or (rcall_st2_cml_1 and cpuwait_cml_1);
1840 
 end if;
1841 
end if;
1842 
end process;
1843 
 
1844 
-- SynEDA CoreMultiplier
1845 
-- assignment(s): nicall_st0, icall_st1, icall_st2
1846 
-- replace(s): cpuwait, nicall_st0, icall_st2, idc_icall, icall_st1
1847 
 
1848 
icall_state_machine:process(cp2,ireset)
1849 
begin
1850 
if ireset='0' then                       -- RESET
1851 
nicall_st0 <= '0';
1852 
icall_st1 <= '0';
1853 
icall_st2 <= '0';
1854 
elsif (cp2='1' and cp2'event) then icall_st2 <= icall_st2_cml_1; icall_st1 <= icall_st1_cml_1; nicall_st0 <= nicall_st0_cml_1;       -- CLOCK
1855 
 if (cp2en='1') then                                                      -- Clock enable
1856 
  nicall_st0 <= (not nicall_st0_cml_1 and idc_icall_cml_1) or (nicall_st0_cml_1 and not (icall_st2_cml_1 and not cpuwait_cml_1));
1857 
  icall_st1  <= (not icall_st1_cml_1 and not nicall_st0_cml_1 and idc_icall_cml_1) or (icall_st1_cml_1 and cpuwait_cml_1);
1858 
  icall_st2  <= (not icall_st2_cml_1 and icall_st1_cml_1 and not cpuwait_cml_1) or (icall_st2_cml_1 and cpuwait_cml_1);
1859 
 end if;
1860 
end if;
1861 
end process;
1862 
 
1863 
-- SynEDA CoreMultiplier
1864 
-- assignment(s): ncall_st0, call_st1, call_st2, call_st3
1865 
-- replace(s): cpuwait, ncall_st0, call_st3, idc_call, call_st1, call_st2
1866 
 
1867 
call_state_machine:process(cp2,ireset)
1868 
begin
1869 
if ireset='0' then                       -- RESET
1870 
ncall_st0 <= '0';
1871 
call_st1 <= '0';
1872 
call_st2 <= '0';
1873 
call_st3  <= '0';
1874 
elsif (cp2='1' and cp2'event) then call_st3 <= call_st3_cml_1; call_st2 <= call_st2_cml_1; call_st1 <= call_st1_cml_1; ncall_st0 <= ncall_st0_cml_1;       -- CLOCK
1875 
 if (cp2en='1') then                                                      -- Clock enable
1876 
  ncall_st0 <= (not ncall_st0_cml_1 and idc_call_cml_1) or (ncall_st0_cml_1 and not( call_st3_cml_1 and not cpuwait_cml_1));
1877 
  call_st1  <= not call_st1_cml_1 and not ncall_st0_cml_1 and idc_call_cml_1;
1878 
  call_st2  <= (not call_st2_cml_1 and call_st1_cml_1) or (call_st2_cml_1 and cpuwait_cml_1);
1879 
  call_st3  <= (not call_st3_cml_1 and call_st2_cml_1 and not cpuwait_cml_1) or (call_st3_cml_1 and cpuwait_cml_1);
1880 
 end if;
1881 
end if;
1882 
end process;
1883 
 
1884 
-- SynEDA CoreMultiplier
1885 
-- assignment(s): nret_st0, ret_st1, ret_st2, ret_st3
1886 
-- replace(s): nret_st0, ret_st3, idc_ret, cpuwait, ret_st1, ret_st2
1887 
 
1888 
ret_state_machine:process(cp2,ireset)
1889 
begin
1890 
if ireset='0' then                       -- RESET
1891 
nret_st0 <= '0';
1892 
ret_st1 <= '0';
1893 
ret_st2 <= '0';
1894 
ret_st3  <= '0';
1895 
elsif (cp2='1' and cp2'event) then ret_st3 <= ret_st3_cml_1; ret_st2 <= ret_st2_cml_1; ret_st1 <= ret_st1_cml_1; nret_st0 <= nret_st0_cml_1;       -- CLOCK
1896 
 if (cp2en='1') then                                                      -- Clock enable
1897 
  nret_st0 <= (not nret_st0_cml_1 and idc_ret_cml_1) or (nret_st0_cml_1 and not ret_st3_cml_1);
1898 
  ret_st1  <= (not ret_st1_cml_1 and not nret_st0_cml_1 and idc_ret_cml_1) or (ret_st1_cml_1 and cpuwait_cml_1);
1899 
  ret_st2  <= (not ret_st2_cml_1 and ret_st1_cml_1 and not cpuwait_cml_1) or (ret_st2_cml_1 and cpuwait_cml_1) ;
1900 
  ret_st3  <= not ret_st3_cml_1 and ret_st2_cml_1 and not cpuwait_cml_1;
1901 
 end if;
1902 
end if;
1903 
end process;
1904 
 
1905 
-- SynEDA CoreMultiplier
1906 
-- assignment(s): nreti_st0, reti_st1, reti_st2, reti_st3
1907 
-- replace(s): nreti_st0, reti_st3, idc_reti, cpuwait, reti_st1, reti_st2
1908 
 
1909 
reti_state_machine:process(cp2,ireset)
1910 
begin
1911 
if ireset='0' then                       -- RESET
1912 
nreti_st0 <= '0';
1913 
reti_st1 <= '0';
1914 
reti_st2 <= '0';
1915 
reti_st3  <= '0';
1916 
elsif (cp2='1' and cp2'event) then reti_st3 <= reti_st3_cml_1; reti_st2 <= reti_st2_cml_1; reti_st1 <= reti_st1_cml_1; nreti_st0 <= nreti_st0_cml_1;       -- CLOCK
1917 
 if (cp2en='1') then                                                      -- Clock enable
1918 
  nreti_st0 <= (not nreti_st0_cml_1 and idc_reti_cml_1) or (nreti_st0_cml_1 and not reti_st3_cml_1);
1919 
  reti_st1  <= (not reti_st1_cml_1 and not nreti_st0_cml_1 and idc_reti_cml_1) or (reti_st1_cml_1 and cpuwait_cml_1);
1920 
  reti_st2  <= (not reti_st2_cml_1 and reti_st1_cml_1 and not cpuwait_cml_1) or (reti_st2_cml_1 and cpuwait_cml_1) ;
1921 
  reti_st3  <= not reti_st3_cml_1 and reti_st2_cml_1 and not cpuwait_cml_1;
1922 
 end if;
1923 
end if;
1924 
end process;
1925 
 
1926 
 
1927 
-- INTERRUPT LOGIC AND STATE MACHINE
1928 
 
1929 
-- SynEDA CoreMultiplier
1930 
-- assignment(s): irq_int
1931 
-- replace(s): irqlines
1932 
 
1933 
irq_int <= '0' when      irqlines_cml_1="00000000000000000000000" else '1';
1934 
 
1935 
irq_vector_adr(15 downto 6)<=(others => '0');
1936 
irq_vector_adr(0) <= '0';
1937 
-- SynEDA CoreMultiplier
1938 
-- assignment(s): irq_vector_adr
1939 
-- replace(s): irqlines
1940 
 
1941 
-- PRIORITY ENCODER
1942 
irq_vector_adr(5 downto 1) <= "00001" when irqlines_cml_1(0)='1'  else -- 0x0002
1943 
                              "00010" when irqlines_cml_1(1)='1'  else -- 0x0004
1944 
                              "00011" when irqlines_cml_1(2)='1'  else -- 0x0006
1945 
                              "00100" when irqlines_cml_1(3)='1'  else -- 0x0008
1946 
                              "00101" when irqlines_cml_1(4)='1'  else -- 0x000A
1947 
                              "00110" when irqlines_cml_1(5)='1'  else -- 0x000C
1948 
                              "00111" when irqlines_cml_1(6)='1'  else -- 0x000E
1949 
                              "01000" when irqlines_cml_1(7)='1'  else -- 0x0010
1950 
                              "01001" when irqlines_cml_1(8)='1'  else -- 0x0012
1951 
                              "01010" when irqlines_cml_1(9)='1'  else -- 0x0014
1952 
                              "01011" when irqlines_cml_1(10)='1' else -- 0x0016
1953 
                              "01100" when irqlines_cml_1(11)='1' else -- 0x0018
1954 
                              "01101" when irqlines_cml_1(12)='1' else -- 0x001A
1955 
                              "01110" when irqlines_cml_1(13)='1' else -- 0x001C
1956 
                              "01111" when irqlines_cml_1(14)='1' else -- 0x001E
1957 
                              "10000" when irqlines_cml_1(15)='1' else -- 0x0020
1958 
                              "10001" when irqlines_cml_1(16)='1' else -- 0x0022
1959 
                              "10010" when irqlines_cml_1(17)='1' else -- 0x0024
1960 
                              "10011" when irqlines_cml_1(18)='1' else -- 0x0026
1961 
                              "10100" when irqlines_cml_1(19)='1' else -- 0x0028
1962 
                              "10101" when irqlines_cml_1(20)='1' else -- 0x002A
1963 
                              "10110" when irqlines_cml_1(21)='1' else -- 0x002C
1964 
                              "10111" when irqlines_cml_1(22)='1' else -- 0x002E
1965 
                                                          "00000";
1966 
 
1967 
-- SynEDA CoreMultiplier
1968 
-- assignment(s): cpu_busy
1969 
-- replace(s): cpuwait, two_word_inst, nirq_st0, call_st1, call_st2, call_st3, rcall_st1, rcall_st2, icall_st1, icall_st2, jmp_st1, ret_st1, ret_st2, reti_st1, reti_st2, skip_inst_st1, lpm_st1, sts_st, lds_st, st_st, ld_st, push_st, pop_st, iowe_int, idc_adiw, idc_bclr, idc_brbc, idc_brbs, idc_call, idc_cbi, idc_icall, idc_ijmp, idc_jmp, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_lpm, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_rjmp, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts, sreg_bop_wr_en, sreg_adr_eq
1970 
 
1971 
-- MULTI CYCLE INSTRUCTION FLAG FOR IRQ
1972 
cpu_busy <= idc_adiw_cml_1 or idc_sbiw_cml_1 or idc_cbi_cml_1 or idc_sbi_cml_1 or
1973 
            idc_rjmp_cml_1 or idc_ijmp_cml_1 or
1974 
                        idc_jmp_cml_1 or jmp_st1_cml_1 or
1975 
--                      idc_brbs or idc_brbc or -- Old variant
1976 
            ((idc_brbc_cml_1 or idc_brbs_cml_1) and  bit_test_op_out) or
1977 
                        idc_lpm_cml_1 or lpm_st1_cml_1 or
1978 
                        skip_inst_start or (skip_inst_st1_cml_1 and two_word_inst_cml_1) or
1979 
                        idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ldd_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_z_cml_1 or (ld_st_cml_1 and cpuwait_cml_1) or
1980 
                        idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1 or (st_st_cml_1 and cpuwait_cml_1) or
1981 
                        idc_lds_cml_1 or (lds_st_cml_1 and cpuwait_cml_1) or
1982 
                        idc_sts_cml_1 or (sts_st_cml_1 and cpuwait_cml_1) or
1983 
                        idc_rcall_cml_1 or rcall_st1_cml_1 or (rcall_st2_cml_1 and cpuwait_cml_1) or           -- RCALL
1984 
                        idc_icall_cml_1 or icall_st1_cml_1 or (icall_st2_cml_1 and cpuwait_cml_1) or               -- ICALL
1985 
                        idc_call_cml_1 or call_st1_cml_1 or call_st2_cml_1 or (call_st3_cml_1 and cpuwait_cml_1) or  -- CALL
1986 
                        idc_push_cml_1 or (push_st_cml_1 and cpuwait_cml_1) or                           -- PUSH (added 14.07.05)
1987 
                        idc_pop_cml_1 or (pop_st_cml_1 and cpuwait_cml_1) or                             -- POP  (added 14.07.05)
1988 
                    (idc_bclr_cml_1 and sreg_bop_wr_en_cml_1(7)) or                 -- ??? CLI
1989 
                    (iowe_int_cml_1 and sreg_adr_eq_cml_1 and not dbusout_int(7))or -- ??? Writing '0' to I flag (OUT/STD/ST/STD)
1990 
                        nirq_st0_cml_1 or
1991 
--                      idc_ret  or nret_st0 or                             -- Old variant
1992 
                        idc_ret_cml_1 or ret_st1_cml_1 or ret_st2_cml_1 or
1993 
--                      idc_reti or nreti_st0;                              -- At least one instruction must be executed after RETI and before the new interrupt.
1994 
                        idc_reti_cml_1 or reti_st1_cml_1 or reti_st2_cml_1;
1995 
 
1996 
sreg_adr_eq <= '1' when adr_int=SREG_Address else '0';
1997 
 
1998 
--irq_start <= irq_int and not cpu_busy and globint;
1999 
irq_start <= irq_int and not cpu_busy and globint;
2000 
 
2001 
-- SynEDA CoreMultiplier
2002 
-- assignment(s): nirq_st0, irq_st1, irq_st2, irq_st3
2003 
-- replace(s): cpuwait, nirq_st0, irq_st3, irq_st1, irq_st2
2004 
 
2005 
irq_state_machine:process(cp2,ireset)
2006 
begin
2007 
if ireset='0' then                       -- RESET
2008 
nirq_st0 <= '0';
2009 
irq_st1 <= '0';
2010 
irq_st2 <= '0';
2011 
irq_st3 <= '0';
2012 
elsif (cp2='1' and cp2'event) then irq_st3 <= irq_st3_cml_1; irq_st2 <= irq_st2_cml_1; irq_st1 <= irq_st1_cml_1; nirq_st0 <= nirq_st0_cml_1;       -- CLOCK
2013 
 if (cp2en='1') then                                                      -- Clock enable
2014 
  nirq_st0 <= (not nirq_st0_cml_1 and irq_start) or (nirq_st0_cml_1 and not (irq_st3_cml_1 and not cpuwait_cml_1));
2015 
  irq_st1  <= (not irq_st1_cml_1 and not nirq_st0_cml_1 and irq_start);
2016 
  irq_st2  <= (not irq_st2_cml_1 and irq_st1_cml_1) or (irq_st2_cml_1 and cpuwait_cml_1);
2017 
  irq_st3  <= (not irq_st3_cml_1 and irq_st2_cml_1 and not cpuwait_cml_1) or (irq_st3_cml_1 and cpuwait_cml_1);
2018 
 end if;
2019 
end if;
2020 
end process;
2021 
 
2022 
-- SynEDA CoreMultiplier
2023 
-- assignment(s): irqack_int
2024 
-- replace(s): irqack_int
2025 
 
2026 
irqack_reg:process(cp2,ireset)
2027 
begin
2028 
if ireset='0' then                       -- RESET
2029 
irqack_int<='0';
2030 
elsif (cp2='1' and cp2'event) then irqack_int <= irqack_int_cml_1;       -- CLOCK
2031 
 if (cp2en='1') then                                                      -- Clock enable
2032 
  irqack_int<= not irqack_int_cml_1 and irq_start;
2033 
 end if;
2034 
end if;
2035 
end process;
2036 
-- SynEDA CoreMultiplier
2037 
-- assignment(s): irqack
2038 
-- replace(s): irqack_int
2039 
 
2040 
irqack_cml_out <= irqack_int_cml_1;
2041 
 
2042 
-- SynEDA CoreMultiplier
2043 
-- assignment(s): irqackad_int
2044 
-- replace(s): irqackad_int
2045 
 
2046 
irqackad_reg:process(cp2,ireset)
2047 
begin
2048 
if ireset='0' then                                -- RESET
2049 
irqackad_int<=(others=>'0');
2050 
elsif (cp2='1' and cp2'event) then irqackad_int <= irqackad_int_cml_1;              -- CLOCK
2051 
 if (cp2en='1') then                                                      -- Clock enable
2052 
  irqackad_int <= irq_vector_adr(5 downto 1);
2053 
 end if;
2054 
end if;
2055 
end process;
2056 
-- SynEDA CoreMultiplier
2057 
-- assignment(s): irqackad
2058 
-- replace(s): irqackad_int
2059 
 
2060 
irqackad_cml_out <= irqackad_int_cml_1;
2061 
 
2062 
-- *******************************************************************************************
2063 
 
2064 
-- SynEDA CoreMultiplier
2065 
-- assignment(s): ijmp_st, rjmp_st, brxx_st, push_st, pop_st
2066 
-- replace(s): ijmp_st, idc_ijmp, rjmp_st, idc_rjmp, brxx_st, idc_brbc, idc_brbs, cpuwait, push_st, idc_push, pop_st, idc_pop
2067 
 
2068 
rjmp_push_pop_ijmp_state_brxx_machine:process(cp2,ireset)
2069 
begin
2070 
if ireset='0' then                       -- RESET
2071 
rjmp_st <= '0';
2072 
ijmp_st <= '0';
2073 
push_st <= '0';
2074 
pop_st <= '0';
2075 
brxx_st <= '0';
2076 
elsif (cp2='1' and cp2'event) then pop_st <= pop_st_cml_1; push_st <= push_st_cml_1; brxx_st <= brxx_st_cml_1; rjmp_st <= rjmp_st_cml_1; ijmp_st <= ijmp_st_cml_1;       -- CLOCK
2077 
 if (cp2en='1') then                                                      -- Clock enable
2078 
  rjmp_st <= idc_rjmp_cml_1;    -- ??
2079 
  ijmp_st <= idc_ijmp_cml_1;
2080 
  push_st <= (not push_st_cml_1 and idc_push_cml_1) or (push_st_cml_1 and cpuwait_cml_1);
2081 
  pop_st  <= (not pop_st_cml_1  and idc_pop_cml_1) or (pop_st_cml_1 and cpuwait_cml_1);
2082 
  brxx_st <= not brxx_st_cml_1 and (idc_brbc_cml_1 or idc_brbs_cml_1) and bit_test_op_out;
2083 
 end if;
2084 
end if;
2085 
end process;
2086 
 
2087 
-- SynEDA CoreMultiplier
2088 
-- assignment(s): st_st, ld_st
2089 
-- replace(s): cpuwait, st_st, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, ld_st, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z
2090 
 
2091 
-- LD/LDD/ST/STD
2092 
ld_st_state_machine:process(cp2,ireset)
2093 
begin
2094 
if ireset='0' then                       -- RESET
2095 
ld_st <= '0';
2096 
st_st <= '0';
2097 
elsif (cp2='1' and cp2'event) then ld_st <= ld_st_cml_1; st_st <= st_st_cml_1;       -- CLOCK
2098 
 if (cp2en='1') then                                                      -- Clock enable
2099 
  ld_st <= (not ld_st_cml_1 and (idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ldd_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_z_cml_1)) or (ld_st_cml_1 and cpuwait_cml_1);
2100 
  st_st <= (not st_st_cml_1 and (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)) or (st_st_cml_1 and cpuwait_cml_1);
2101 
 end if;
2102 
end if;
2103 
end process;
2104 
 
2105 
-- SynEDA CoreMultiplier
2106 
-- assignment(s): sbi_st, cbi_st, cbi_sbi_io_adr_tmp, cbi_sbi_bit_num_tmp
2107 
-- replace(s): sbi_st, idc_sbi, cbi_st, idc_cbi, dex_adr5port, cbi_sbi_io_adr_tmp, dex_bitop_bitnum, cbi_sbi_bit_num_tmp
2108 
 
2109 
-- SBI/CBI
2110 
sbi_cbi_machine:process(cp2,ireset)
2111 
begin
2112 
if ireset='0' then                       -- RESET
2113 
sbi_st <= '0';
2114 
cbi_st <= '0';
2115 
cbi_sbi_io_adr_tmp  <= (others => '0');
2116 
cbi_sbi_bit_num_tmp     <= (others => '0');
2117 
elsif (cp2='1' and cp2'event) then cbi_sbi_bit_num_tmp <= cbi_sbi_bit_num_tmp_cml_1; cbi_sbi_io_adr_tmp <= cbi_sbi_io_adr_tmp_cml_1; cbi_st <= cbi_st_cml_1; sbi_st <= sbi_st_cml_1;       -- CLOCK
2118 
 if (cp2en='1') then                                                      -- Clock enable
2119 
  sbi_st <= not sbi_st_cml_1 and idc_sbi_cml_1;
2120 
  cbi_st <= not cbi_st_cml_1 and idc_cbi_cml_1;
2121 
  cbi_sbi_io_adr_tmp <= dex_adr5port_cml_1;
2122 
  cbi_sbi_bit_num_tmp <= dex_bitop_bitnum_cml_1;
2123 
 end if;
2124 
end if;
2125 
end process;
2126 
 
2127 
-- ########################################################################################
2128 
 
2129 
-- SREG FLAGS WRITE ENABLE LOGIC
2130 
 
2131 
--bclr_bset_op_en_logic:for i in sreg_bop_wr_en'range generate
2132 
--sreg_bop_wr_en(i) <= '1' when (dex_bitnum_sreg=i and (idc_bclr or idc_bset)='1') else '0';
2133 
--end generate;
2134 
 
2135 
sreg_bop_wr_en(0) <= '1' when (dex_bitnum_sreg=0 and (idc_bclr or idc_bset)='1') else '0';
2136 
sreg_bop_wr_en(1) <= '1' when (dex_bitnum_sreg=1 and (idc_bclr or idc_bset)='1') else '0';
2137 
sreg_bop_wr_en(2) <= '1' when (dex_bitnum_sreg=2 and (idc_bclr or idc_bset)='1') else '0';
2138 
sreg_bop_wr_en(3) <= '1' when (dex_bitnum_sreg=3 and (idc_bclr or idc_bset)='1') else '0';
2139 
sreg_bop_wr_en(4) <= '1' when (dex_bitnum_sreg=4 and (idc_bclr or idc_bset)='1') else '0';
2140 
sreg_bop_wr_en(5) <= '1' when (dex_bitnum_sreg=5 and (idc_bclr or idc_bset)='1') else '0';
2141 
sreg_bop_wr_en(6) <= '1' when (dex_bitnum_sreg=6 and (idc_bclr or idc_bset)='1') else '0';
2142 
sreg_bop_wr_en(7) <= '1' when (dex_bitnum_sreg=7 and (idc_bclr or idc_bset)='1') else '0';
2143 
 
2144 
-- SynEDA CoreMultiplier
2145 
-- assignment(s): sreg_c_wr_en
2146 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_adiw, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_lsr, idc_neg, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi, sreg_bop_wr_en
2147 
 
2148 
sreg_c_wr_en <= idc_add_cml_1 or idc_adc_cml_1 or (idc_adiw_cml_1 or adiw_st_cml_1) or idc_sub_cml_1  or idc_subi_cml_1 or
2149 
                idc_sbc_cml_1 or idc_sbci_cml_1 or (idc_sbiw_cml_1 or sbiw_st_cml_1) or idc_com_cml_1 or idc_neg_cml_1 or
2150 
                                idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1 or
2151 
                idc_lsr_cml_1 or idc_ror_cml_1 or idc_asr_cml_1 or sreg_bop_wr_en_cml_1(0);
2152 
 
2153 
-- SynEDA CoreMultiplier
2154 
-- assignment(s): sreg_z_wr_en
2155 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_adiw, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi, sreg_bop_wr_en
2156 
 
2157 
sreg_z_wr_en <= idc_add_cml_1 or idc_adc_cml_1 or (idc_adiw_cml_1 or adiw_st_cml_1) or idc_sub_cml_1  or idc_subi_cml_1 or
2158 
                idc_sbc_cml_1 or idc_sbci_cml_1 or (idc_sbiw_cml_1 or sbiw_st_cml_1) or
2159 
                                idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1 or
2160 
                idc_and_cml_1 or idc_andi_cml_1 or idc_or_cml_1 or idc_ori_cml_1 or idc_eor_cml_1 or idc_com_cml_1 or idc_neg_cml_1 or
2161 
                idc_inc_cml_1 or idc_dec_cml_1 or idc_lsr_cml_1 or idc_ror_cml_1 or idc_asr_cml_1 or sreg_bop_wr_en_cml_1(1);
2162 
 
2163 
 
2164 
-- SynEDA CoreMultiplier
2165 
-- assignment(s): sreg_n_wr_en
2166 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi, sreg_bop_wr_en
2167 
 
2168 
sreg_n_wr_en <= idc_add_cml_1 or idc_adc_cml_1 or adiw_st_cml_1 or idc_sub_cml_1  or idc_subi_cml_1 or
2169 
                idc_sbc_cml_1 or idc_sbci_cml_1 or sbiw_st_cml_1 or
2170 
                                idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1 or
2171 
                idc_and_cml_1 or idc_andi_cml_1 or idc_or_cml_1 or idc_ori_cml_1 or idc_eor_cml_1 or idc_com_cml_1 or idc_neg_cml_1 or
2172 
                idc_inc_cml_1 or idc_dec_cml_1 or idc_lsr_cml_1 or idc_ror_cml_1 or idc_asr_cml_1 or sreg_bop_wr_en_cml_1(2);
2173 
 
2174 
-- SynEDA CoreMultiplier
2175 
-- assignment(s): sreg_v_wr_en
2176 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi, sreg_bop_wr_en
2177 
 
2178 
sreg_v_wr_en <= idc_add_cml_1 or idc_adc_cml_1 or adiw_st_cml_1 or idc_sub_cml_1  or idc_subi_cml_1 or -- idc_adiw
2179 
                idc_sbc_cml_1 or idc_sbci_cml_1 or sbiw_st_cml_1 or idc_neg_cml_1 or idc_com_cml_1 or  -- idc_sbiw
2180 
                idc_inc_cml_1 or idc_dec_cml_1 or
2181 
                                idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1 or
2182 
                idc_lsr_cml_1 or idc_ror_cml_1 or idc_asr_cml_1 or sreg_bop_wr_en_cml_1(3) or
2183 
                                idc_and_cml_1 or idc_andi_cml_1 or idc_or_cml_1 or idc_ori_cml_1 or idc_eor_cml_1; -- V-flag bug fixing
2184 
 
2185 
-- SynEDA CoreMultiplier
2186 
-- assignment(s): sreg_s_wr_en
2187 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi, sreg_bop_wr_en
2188 
 
2189 
sreg_s_wr_en <= idc_add_cml_1 or idc_adc_cml_1 or adiw_st_cml_1 or idc_sub_cml_1 or idc_subi_cml_1 or
2190 
                idc_sbc_cml_1 or idc_sbci_cml_1 or sbiw_st_cml_1 or
2191 
                                idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1 or
2192 
                                idc_and_cml_1 or idc_andi_cml_1 or idc_or_cml_1 or idc_ori_cml_1 or idc_eor_cml_1 or idc_com_cml_1 or idc_neg_cml_1 or
2193 
                                idc_inc_cml_1 or idc_dec_cml_1 or idc_lsr_cml_1 or idc_ror_cml_1 or idc_asr_cml_1 or sreg_bop_wr_en_cml_1(4);
2194 
 
2195 
-- SynEDA CoreMultiplier
2196 
-- assignment(s): sreg_h_wr_en
2197 
-- replace(s): idc_adc, idc_add, idc_cp, idc_cpc, idc_cpi, idc_neg, idc_sbc, idc_sbci, idc_sub, idc_subi, sreg_bop_wr_en
2198 
 
2199 
sreg_h_wr_en <= idc_add_cml_1 or idc_adc_cml_1 or idc_sub_cml_1  or idc_subi_cml_1 or
2200 
                                idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1 or
2201 
                idc_sbc_cml_1 or idc_sbci_cml_1 or idc_neg_cml_1 or sreg_bop_wr_en_cml_1(5);
2202 
 
2203 
-- SynEDA CoreMultiplier
2204 
-- assignment(s): sreg_t_wr_en
2205 
-- replace(s): sreg_bop_wr_en
2206 
 
2207 
sreg_t_wr_en <=  idc_bst or sreg_bop_wr_en_cml_1(6);
2208 
 
2209 
-- SynEDA CoreMultiplier
2210 
-- assignment(s): sreg_i_wr_en
2211 
-- replace(s): irq_st1, reti_st3, sreg_bop_wr_en
2212 
 
2213 
sreg_i_wr_en <= irq_st1_cml_1 or reti_st3_cml_1 or sreg_bop_wr_en_cml_1(7); -- WAS "irq_start"
2214 
 
2215 
-- SynEDA CoreMultiplier
2216 
-- assignment(s): sreg_fl_in
2217 
-- replace(s): reti_st3, idc_bclr, idc_bset
2218 
 
2219 
sreg_fl_in_cml_out <=  bit_pr_sreg_out when (idc_bst or idc_bclr_cml_1 or idc_bset_cml_1)='1' else                         -- TO THE SREG
2220 
reti_st3_cml_1&'0'&alu_h_flag_out&alu_s_flag_out&alu_v_flag_out&alu_n_flag_out&alu_z_flag_out&alu_c_flag_out;
2221 
 
2222 
-- #################################################################################################################
2223 
 
2224 
-- *********************************************************************************************
2225 
-- ************** INSTRUCTION DECODER OUTPUTS FOR THE OTHER BLOCKS  ****************************
2226 
-- *********************************************************************************************
2227 
 
2228 
-- FOR ALU
2229 
 
2230 
idc_add_out   <= idc_add;
2231 
idc_adc_out   <= idc_adc;
2232 
idc_adiw_out  <= idc_adiw;
2233 
idc_sub_out   <= idc_sub;
2234 
idc_subi_out  <= idc_subi;
2235 
idc_sbc_out   <= idc_sbc;
2236 
idc_sbci_out  <= idc_sbci;
2237 
idc_sbiw_out  <= idc_sbiw;
2238 
adiw_st_out   <= adiw_st;
2239 
sbiw_st_out   <= sbiw_st;
2240 
idc_and_out   <= idc_and;
2241 
idc_andi_out  <= idc_andi;
2242 
idc_or_out    <= idc_or;
2243 
idc_ori_out   <= idc_ori;
2244 
idc_eor_out   <= idc_eor;
2245 
idc_com_out   <= idc_com;
2246 
idc_neg_out   <= idc_neg;
2247 
idc_inc_out   <= idc_inc;
2248 
idc_dec_out   <= idc_dec;
2249 
idc_cp_out    <= idc_cp;
2250 
idc_cpc_out   <= idc_cpc;
2251 
idc_cpi_out   <= idc_cpi;
2252 
idc_cpse_out  <= idc_cpse;
2253 
idc_lsr_out   <= idc_lsr;
2254 
idc_ror_out   <= idc_ror;
2255 
idc_asr_out   <= idc_asr;
2256 
idc_swap_out  <= idc_swap;
2257 
 
2258 
-- FOR THE BIT PROCESSOR
2259 
sbi_st_out   <= sbi_st;
2260 
cbi_st_out   <= cbi_st;
2261 
idc_bst_out  <= idc_bst;
2262 
-- SynEDA CoreMultiplier
2263 
-- assignment(s): idc_bset_out
2264 
-- replace(s): idc_bset
2265 
 
2266 
idc_bset_out_cml_out <= idc_bset_cml_1;
2267 
-- SynEDA CoreMultiplier
2268 
-- assignment(s): idc_bclr_out
2269 
-- replace(s): idc_bclr
2270 
 
2271 
idc_bclr_out_cml_out <= idc_bclr_cml_1;
2272 
idc_sbic_out <= idc_sbic;
2273 
idc_sbis_out <= idc_sbis;
2274 
idc_sbrs_out <= idc_sbrs;
2275 
idc_sbrc_out <= idc_sbrc;
2276 
idc_brbs_out <= idc_brbs;
2277 
idc_brbc_out <= idc_brbc;
2278 
-- SynEDA CoreMultiplier
2279 
-- assignment(s): idc_reti_out
2280 
-- replace(s): idc_reti
2281 
 
2282 
idc_reti_out_cml_out <= idc_reti_cml_1;
2283 
 
2284 
-- POST INCREMENT/PRE DECREMENT FOR THE X,Y,Z REGISTERS
2285 
post_inc <= idc_psinc;
2286 
pre_dec  <= idc_prdec;
2287 
-- SynEDA CoreMultiplier
2288 
-- assignment(s): reg_h_wr
2289 
-- replace(s): idc_ld_x, idc_ld_y, idc_ld_z, idc_st_x, idc_st_y, idc_st_z
2290 
 
2291 
reg_h_wr_cml_out <= (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_st_z_cml_1 or idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ld_z_cml_1) and (idc_psinc or idc_prdec);
2292 
 
2293 
reg_h_adr_cml_out(0)<= idc_st_x_cml_1 or idc_ld_x_cml_1;
2294 
reg_h_adr_cml_out(1)<= idc_st_y_cml_1 or idc_std_y_cml_1 or idc_ld_y_cml_1 or idc_ldd_y_cml_1;
2295 
-- SynEDA CoreMultiplier
2296 
-- assignment(s): reg_h_adr
2297 
-- replace(s): idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
2298 
 
2299 
reg_h_adr_cml_out(2)<= idc_st_z_cml_1 or idc_std_z_cml_1 or idc_ld_z_cml_1 or idc_ldd_z_cml_1;
2300 
 
2301 
-- SynEDA CoreMultiplier
2302 
-- assignment(s): sp_en
2303 
-- replace(s): cpuwait, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti
2304 
 
2305 
-- SynEDA CoreMultiplier
2306 
-- assignment(s): sp_ndown_up
2307 
-- replace(s): cpuwait, ret_st1, reti_st1, idc_pop, idc_ret, idc_reti
2308 
 
2309 
-- STACK POINTER CONTROL
2310 
sp_ndown_up_cml_out <= idc_pop_cml_1 or idc_ret_cml_1 or (ret_st1_cml_1 and not cpuwait_cml_1) or idc_reti_cml_1 or (reti_st1_cml_1 and not cpuwait_cml_1); -- ?????????
2311 
sp_en_cml_out <= idc_push_cml_1 or idc_pop_cml_1 or idc_rcall_cml_1 or (rcall_st1_cml_1 and not cpuwait_cml_1) or idc_icall_cml_1 or (icall_st1_cml_1 and not cpuwait_cml_1) or
2312 
idc_ret_cml_1 or (ret_st1_cml_1 and not cpuwait_cml_1) or idc_reti_cml_1 or (reti_st1_cml_1 and not cpuwait_cml_1) or
2313 
call_st1_cml_1 or (call_st2_cml_1 and not cpuwait_cml_1) or irq_st1_cml_1 or (irq_st2_cml_1 and not cpuwait_cml_1); --????????
2314 
 
2315 
 
2316 
branch  <= dex_condition;
2317 
bit_num_r_io <= cbi_sbi_bit_num_tmp when (cbi_st or sbi_st)='1' else dex_bitop_bitnum;
2318 
 
2319 
adr <= adr_int;
2320 
 
2321 
ramre <= ramre_int;
2322 
ramwe <= ramwe_int;
2323 
 
2324 
iore <= iore_int;
2325 
-- SynEDA CoreMultiplier
2326 
-- assignment(s): iowe
2327 
-- replace(s): iowe_int
2328 
 
2329 
iowe_cml_out <= iowe_int_cml_1;
2330 
 
2331 
--dbusout <= dbusout_int;
2332 
 
2333 
-- Sleep Control
2334 
sleepi <= idc_sleep;
2335 
irqok  <= irq_int;
2336 
 
2337 
-- Watchdog
2338 
wdri <= idc_wdr;
2339 
 
2340 
-- ************************** JTAG OCD support ************************************
2341 
 
2342 
-- Change of flow
2343 
change_flow <= '0';
2344 
valid_instr <= '0';
2345 
 
2346 
 
2347 
end RTL;

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