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tobil |
--**********************************************************************************************
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-- General purpose register file for the AVR Core
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-- Version 1.4 (Special version for the JTAG OCD)
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-- Modified 22.04.2004
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-- Designed by Ruslan Lepetenok
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--**********************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use WORK.SynthCtrlPack.all; -- Synthesis control
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entity reg_file_cm2 is port (
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cp2_cml_1 : in std_logic;
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--Clock and reset
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cp2 : in std_logic;
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cp2en : in std_logic;
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ireset : in std_logic;
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reg_rd_in : in std_logic_vector(7 downto 0);
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reg_rd_out : out std_logic_vector(7 downto 0);
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reg_rd_out_int : out std_logic_vector(7 downto 0);
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reg_rd_adr : in std_logic_vector(4 downto 0);
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reg_rd_adr_int : in std_logic_vector (4 downto 0);
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reg_rr_out : out std_logic_vector(7 downto 0);
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reg_rr_adr : in std_logic_vector(4 downto 0);
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reg_rd_wr : in std_logic;
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post_inc : in std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS
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pre_dec : in std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
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reg_h_wr : in std_logic;
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reg_h_out : out std_logic_vector(15 downto 0);
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reg_h_adr : in std_logic_vector(2 downto 0); -- x,y,z
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reg_z_out : out std_logic_vector(15 downto 0) -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
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);
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end reg_file_cm2;
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architecture RTL of reg_file_cm2 is
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type register_file_type is array(0 to 25) of std_logic_vector(7 downto 0);
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type register_mux_type is array(0 to 31) of std_logic_vector(7 downto 0);
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signal register_file : register_file_type;
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signal r26h : std_logic_vector(7 downto 0);
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signal r27h : std_logic_vector(7 downto 0);
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signal r28h : std_logic_vector(7 downto 0);
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signal r29h : std_logic_vector(7 downto 0);
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signal r30h : std_logic_vector(7 downto 0);
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signal r31h : std_logic_vector(7 downto 0);
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signal register_wr_en : std_logic_vector(31 downto 0);
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signal sg_rd_decode : std_logic_vector (31 downto 0);
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signal sg_rd_decode_int : std_logic_vector (31 downto 0);
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signal sg_rr_decode : std_logic_vector (31 downto 0);
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--signal sg_tmp_rd_data : register_mux_type;
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signal sg_tmp_rd_data_0 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_1 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_2 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_3 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_4 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_5 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_6 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_7 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_8 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_9 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_10 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_11 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_12 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_13 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_14 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_15 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_16 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_17 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_18 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_19 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_20 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_21 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_22 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_23 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_24 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_25 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_26 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_27 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_28 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_29 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_30 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_31 : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_0_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_1_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_2_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_3_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_4_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_5_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_6_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_7_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_8_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_9_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_10_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_11_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_12_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_13_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_14_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_15_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_16_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_17_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_18_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_19_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_20_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_21_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_22_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_23_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_24_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_25_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_26_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_27_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_28_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_29_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_30_int : std_logic_vector(7 downto 0);
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signal sg_tmp_rd_data_31_int : std_logic_vector(7 downto 0);
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--signal sg_tmp_rr_data : register_mux_type;
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signal sg_tmp_rr_data_0 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_1 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_2 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_3 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_4 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_5 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_6 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_7 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_8 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_9 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_10 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_11 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_12 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_13 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_14 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_15 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_16 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_17 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_18 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_19 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_20 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_21 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_22 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_23 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_24 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_25 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_26 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_27 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_28 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_29 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_30 : std_logic_vector(7 downto 0);
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signal sg_tmp_rr_data_31 : std_logic_vector(7 downto 0);
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signal sg_adr16_postinc : std_logic_vector (15 downto 0);
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signal sg_adr16_predec : std_logic_vector (15 downto 0);
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signal reg_h_in : std_logic_vector (15 downto 0);
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signal sg_tmp_h_data : std_logic_vector (15 downto 0);
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signal reg_rd_adr_cml_1 : std_logic_vector ( 4 downto 0 );
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signal register_file_cml_1 : register_file_type;
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signal r26h_cml_1 : std_logic_vector ( 7 downto 0 );
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signal r27h_cml_1 : std_logic_vector ( 7 downto 0 );
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signal r28h_cml_1 : std_logic_vector ( 7 downto 0 );
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signal r29h_cml_1 : std_logic_vector ( 7 downto 0 );
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signal reg_z_out_cml_out : std_logic_vector ( 15 downto 0 );
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signal r30h_cml_1 : std_logic_vector ( 7 downto 0 );
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signal r31h_cml_1 : std_logic_vector ( 7 downto 0 );
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begin
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process(cp2_cml_1) begin
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if (cp2_cml_1 = '1' and cp2_cml_1'event) then
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reg_rd_adr_cml_1 <= reg_rd_adr;
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register_file_cml_1 <= register_file;
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r26h_cml_1 <= r26h;
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r27h_cml_1 <= r27h;
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r28h_cml_1 <= r28h;
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r29h_cml_1 <= r29h;
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r30h_cml_1 <= r30h;
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r31h_cml_1 <= r31h;
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end if;
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end process;
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reg_z_out <= reg_z_out_cml_out;
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write_decode: for i in 0 to 31 generate
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-- SynEDA CoreMultiplier
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-- assignment(s): register_wr_en
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-- replace(s): reg_rd_adr
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register_wr_en(i) <= '1' when (i=reg_rd_adr_cml_1 and reg_rd_wr='1') else '0';
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end generate;
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rd_mux_decode: for i in 0 to 31 generate
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sg_rd_decode(i) <= '1' when (reg_rd_adr=i) else '0';
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end generate;
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rd_mux_decode_int: for i in 0 to 31 generate
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sg_rd_decode_int(i) <= '1' when (reg_rd_adr_int=i) else '0';
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end generate;
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rr_mux_decode: for i in 0 to 31 generate
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sg_rr_decode(i) <= '1' when (reg_rr_adr=i) else '0';
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end generate;
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-- SynEDA CoreMultiplier
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-- assignment(s): reg_z_out
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-- replace(s): r30h, r31h
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reg_z_out_cml_out <= r31h_cml_1&r30h_cml_1; -- R31:R30 OUTPUT FOR LPM/ELPM INSTRUCTIONS
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--sg_tmp_rd_data(0) <= register_file(0) when sg_rd_decode(0)='1' else (others=>'0');
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--read_rd_mux: for i in 1 to 25 generate
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--sg_tmp_rd_data(i) <= register_file(i) when sg_rd_decode(i)='1' else sg_tmp_rd_data(i-1);
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--end generate;
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--sg_tmp_rd_data(26) <= r26h when sg_rd_decode(26)='1' else sg_tmp_rd_data(25);
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--sg_tmp_rd_data(27) <= r27h when sg_rd_decode(27)='1' else sg_tmp_rd_data(26);
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--sg_tmp_rd_data(28) <= r28h when sg_rd_decode(28)='1' else sg_tmp_rd_data(27);
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--sg_tmp_rd_data(29) <= r29h when sg_rd_decode(29)='1' else sg_tmp_rd_data(28);
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--sg_tmp_rd_data(30) <= r30h when sg_rd_decode(30)='1' else sg_tmp_rd_data(29);
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--sg_tmp_rd_data(31) <= r31h when sg_rd_decode(31)='1' else sg_tmp_rd_data(30);
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--reg_rd_out <= sg_tmp_rd_data(31);
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sg_tmp_rd_data_0 <= register_file(0) when sg_rd_decode(0)='1' else (others=>'0');
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sg_tmp_rd_data_1 <= register_file(1) when sg_rd_decode(1)='1' else sg_tmp_rd_data_0;
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sg_tmp_rd_data_2 <= register_file(2) when sg_rd_decode(2)='1' else sg_tmp_rd_data_1;
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sg_tmp_rd_data_3 <= register_file(3) when sg_rd_decode(3)='1' else sg_tmp_rd_data_2;
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sg_tmp_rd_data_4 <= register_file(4) when sg_rd_decode(4)='1' else sg_tmp_rd_data_3;
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sg_tmp_rd_data_5 <= register_file(5) when sg_rd_decode(5)='1' else sg_tmp_rd_data_4;
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sg_tmp_rd_data_6 <= register_file(6) when sg_rd_decode(6)='1' else sg_tmp_rd_data_5;
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sg_tmp_rd_data_7 <= register_file(7) when sg_rd_decode(7)='1' else sg_tmp_rd_data_6;
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sg_tmp_rd_data_8 <= register_file(8) when sg_rd_decode(8)='1' else sg_tmp_rd_data_7;
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sg_tmp_rd_data_9 <= register_file(9) when sg_rd_decode(9)='1' else sg_tmp_rd_data_8;
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sg_tmp_rd_data_10 <= register_file(10) when sg_rd_decode(10)='1' else sg_tmp_rd_data_9;
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sg_tmp_rd_data_11 <= register_file(11) when sg_rd_decode(11)='1' else sg_tmp_rd_data_10;
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sg_tmp_rd_data_12 <= register_file(12) when sg_rd_decode(12)='1' else sg_tmp_rd_data_11;
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sg_tmp_rd_data_13 <= register_file(13) when sg_rd_decode(13)='1' else sg_tmp_rd_data_12;
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sg_tmp_rd_data_14 <= register_file(14) when sg_rd_decode(14)='1' else sg_tmp_rd_data_13;
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sg_tmp_rd_data_15 <= register_file(15) when sg_rd_decode(15)='1' else sg_tmp_rd_data_14;
|
246 |
|
|
sg_tmp_rd_data_16 <= register_file(16) when sg_rd_decode(16)='1' else sg_tmp_rd_data_15;
|
247 |
|
|
sg_tmp_rd_data_17 <= register_file(17) when sg_rd_decode(17)='1' else sg_tmp_rd_data_16;
|
248 |
|
|
sg_tmp_rd_data_18 <= register_file(18) when sg_rd_decode(18)='1' else sg_tmp_rd_data_17;
|
249 |
|
|
sg_tmp_rd_data_19 <= register_file(19) when sg_rd_decode(19)='1' else sg_tmp_rd_data_18;
|
250 |
|
|
sg_tmp_rd_data_20 <= register_file(20) when sg_rd_decode(20)='1' else sg_tmp_rd_data_19;
|
251 |
|
|
sg_tmp_rd_data_21 <= register_file(21) when sg_rd_decode(21)='1' else sg_tmp_rd_data_20;
|
252 |
|
|
sg_tmp_rd_data_22 <= register_file(22) when sg_rd_decode(22)='1' else sg_tmp_rd_data_21;
|
253 |
|
|
sg_tmp_rd_data_23 <= register_file(23) when sg_rd_decode(23)='1' else sg_tmp_rd_data_22;
|
254 |
|
|
sg_tmp_rd_data_24 <= register_file(24) when sg_rd_decode(24)='1' else sg_tmp_rd_data_23;
|
255 |
|
|
sg_tmp_rd_data_25 <= register_file(25) when sg_rd_decode(25)='1' else sg_tmp_rd_data_24;
|
256 |
|
|
sg_tmp_rd_data_26 <= r26h when sg_rd_decode(26)='1' else sg_tmp_rd_data_25;
|
257 |
|
|
sg_tmp_rd_data_27 <= r27h when sg_rd_decode(27)='1' else sg_tmp_rd_data_26;
|
258 |
|
|
sg_tmp_rd_data_28 <= r28h when sg_rd_decode(28)='1' else sg_tmp_rd_data_27;
|
259 |
|
|
sg_tmp_rd_data_29 <= r29h when sg_rd_decode(29)='1' else sg_tmp_rd_data_28;
|
260 |
|
|
sg_tmp_rd_data_30 <= r30h when sg_rd_decode(30)='1' else sg_tmp_rd_data_29;
|
261 |
|
|
sg_tmp_rd_data_31 <= r31h when sg_rd_decode(31)='1' else sg_tmp_rd_data_30;
|
262 |
|
|
reg_rd_out <= sg_tmp_rd_data_31;
|
263 |
|
|
|
264 |
|
|
sg_tmp_rd_data_0_int <= register_file(0) when sg_rd_decode_int(0)='1' else (others=>'0');
|
265 |
|
|
sg_tmp_rd_data_1_int <= register_file(1) when sg_rd_decode_int(1)='1' else sg_tmp_rd_data_0_int;
|
266 |
|
|
sg_tmp_rd_data_2_int <= register_file(2) when sg_rd_decode_int(2)='1' else sg_tmp_rd_data_1_int;
|
267 |
|
|
sg_tmp_rd_data_3_int <= register_file(3) when sg_rd_decode_int(3)='1' else sg_tmp_rd_data_2_int;
|
268 |
|
|
sg_tmp_rd_data_4_int <= register_file(4) when sg_rd_decode_int(4)='1' else sg_tmp_rd_data_3_int;
|
269 |
|
|
sg_tmp_rd_data_5_int <= register_file(5) when sg_rd_decode_int(5)='1' else sg_tmp_rd_data_4_int;
|
270 |
|
|
sg_tmp_rd_data_6_int <= register_file(6) when sg_rd_decode_int(6)='1' else sg_tmp_rd_data_5_int;
|
271 |
|
|
sg_tmp_rd_data_7_int <= register_file(7) when sg_rd_decode_int(7)='1' else sg_tmp_rd_data_6_int;
|
272 |
|
|
sg_tmp_rd_data_8_int <= register_file(8) when sg_rd_decode_int(8)='1' else sg_tmp_rd_data_7_int;
|
273 |
|
|
sg_tmp_rd_data_9_int <= register_file(9) when sg_rd_decode_int(9)='1' else sg_tmp_rd_data_8_int;
|
274 |
|
|
sg_tmp_rd_data_10_int <= register_file(10) when sg_rd_decode_int(10)='1' else sg_tmp_rd_data_9_int;
|
275 |
|
|
sg_tmp_rd_data_11_int <= register_file(11) when sg_rd_decode_int(11)='1' else sg_tmp_rd_data_10_int;
|
276 |
|
|
sg_tmp_rd_data_12_int <= register_file(12) when sg_rd_decode_int(12)='1' else sg_tmp_rd_data_11_int;
|
277 |
|
|
sg_tmp_rd_data_13_int <= register_file(13) when sg_rd_decode_int(13)='1' else sg_tmp_rd_data_12_int;
|
278 |
|
|
sg_tmp_rd_data_14_int <= register_file(14) when sg_rd_decode_int(14)='1' else sg_tmp_rd_data_13_int;
|
279 |
|
|
sg_tmp_rd_data_15_int <= register_file(15) when sg_rd_decode_int(15)='1' else sg_tmp_rd_data_14_int;
|
280 |
|
|
sg_tmp_rd_data_16_int <= register_file(16) when sg_rd_decode_int(16)='1' else sg_tmp_rd_data_15_int;
|
281 |
|
|
sg_tmp_rd_data_17_int <= register_file(17) when sg_rd_decode_int(17)='1' else sg_tmp_rd_data_16_int;
|
282 |
|
|
sg_tmp_rd_data_18_int <= register_file(18) when sg_rd_decode_int(18)='1' else sg_tmp_rd_data_17_int;
|
283 |
|
|
sg_tmp_rd_data_19_int <= register_file(19) when sg_rd_decode_int(19)='1' else sg_tmp_rd_data_18_int;
|
284 |
|
|
sg_tmp_rd_data_20_int <= register_file(20) when sg_rd_decode_int(20)='1' else sg_tmp_rd_data_19_int;
|
285 |
|
|
sg_tmp_rd_data_21_int <= register_file(21) when sg_rd_decode_int(21)='1' else sg_tmp_rd_data_20_int;
|
286 |
|
|
sg_tmp_rd_data_22_int <= register_file(22) when sg_rd_decode_int(22)='1' else sg_tmp_rd_data_21_int;
|
287 |
|
|
sg_tmp_rd_data_23_int <= register_file(23) when sg_rd_decode_int(23)='1' else sg_tmp_rd_data_22_int;
|
288 |
|
|
sg_tmp_rd_data_24_int <= register_file(24) when sg_rd_decode_int(24)='1' else sg_tmp_rd_data_23_int;
|
289 |
|
|
sg_tmp_rd_data_25_int <= register_file(25) when sg_rd_decode_int(25)='1' else sg_tmp_rd_data_24_int;
|
290 |
|
|
sg_tmp_rd_data_26_int <= r26h when sg_rd_decode_int(26)='1' else sg_tmp_rd_data_25_int;
|
291 |
|
|
sg_tmp_rd_data_27_int <= r27h when sg_rd_decode_int(27)='1' else sg_tmp_rd_data_26_int;
|
292 |
|
|
sg_tmp_rd_data_28_int <= r28h when sg_rd_decode_int(28)='1' else sg_tmp_rd_data_27_int;
|
293 |
|
|
sg_tmp_rd_data_29_int <= r29h when sg_rd_decode_int(29)='1' else sg_tmp_rd_data_28_int;
|
294 |
|
|
sg_tmp_rd_data_30_int <= r30h when sg_rd_decode_int(30)='1' else sg_tmp_rd_data_29_int;
|
295 |
|
|
sg_tmp_rd_data_31_int <= r31h when sg_rd_decode_int(31)='1' else sg_tmp_rd_data_30_int;
|
296 |
|
|
reg_rd_out_int <= sg_tmp_rd_data_31_int;
|
297 |
|
|
|
298 |
|
|
--sg_tmp_rr_data(0) <= register_file(0) when sg_rr_decode(0)='1' else (others=>'0');
|
299 |
|
|
--read_rr_mux: for i in 1 to 25 generate
|
300 |
|
|
--sg_tmp_rr_data(i) <= register_file(i) when sg_rr_decode(i)='1' else sg_tmp_rr_data(i-1);
|
301 |
|
|
--end generate;
|
302 |
|
|
--sg_tmp_rr_data() <= register_file() when sg_rr_decode()='1' else sg_tmp_rr_data();
|
303 |
|
|
--sg_tmp_rr_data(26) <= r26h when sg_rr_decode(26)='1' else sg_tmp_rr_data(25);
|
304 |
|
|
--sg_tmp_rr_data(27) <= r27h when sg_rr_decode(27)='1' else sg_tmp_rr_data(26);
|
305 |
|
|
--sg_tmp_rr_data(28) <= r28h when sg_rr_decode(28)='1' else sg_tmp_rr_data(27);
|
306 |
|
|
--sg_tmp_rr_data(29) <= r29h when sg_rr_decode(29)='1' else sg_tmp_rr_data(28);
|
307 |
|
|
--sg_tmp_rr_data(30) <= r30h when sg_rr_decode(30)='1' else sg_tmp_rr_data(29);
|
308 |
|
|
--sg_tmp_rr_data(31) <= r31h when sg_rr_decode(31)='1' else sg_tmp_rr_data(30);
|
309 |
|
|
--reg_rr_out <= sg_tmp_rr_data(31);
|
310 |
|
|
|
311 |
|
|
|
312 |
|
|
sg_tmp_rr_data_0 <= register_file(0) when sg_rr_decode(0)='1' else (others=>'0');
|
313 |
|
|
sg_tmp_rr_data_1 <= register_file(1) when sg_rr_decode(1)='1' else sg_tmp_rr_data_0;
|
314 |
|
|
sg_tmp_rr_data_2 <= register_file(2) when sg_rr_decode(2)='1' else sg_tmp_rr_data_1;
|
315 |
|
|
sg_tmp_rr_data_3 <= register_file(3) when sg_rr_decode(3)='1' else sg_tmp_rr_data_2;
|
316 |
|
|
sg_tmp_rr_data_4 <= register_file(4) when sg_rr_decode(4)='1' else sg_tmp_rr_data_3;
|
317 |
|
|
sg_tmp_rr_data_5 <= register_file(5) when sg_rr_decode(5)='1' else sg_tmp_rr_data_4;
|
318 |
|
|
sg_tmp_rr_data_6 <= register_file(6) when sg_rr_decode(6)='1' else sg_tmp_rr_data_5;
|
319 |
|
|
sg_tmp_rr_data_7 <= register_file(7) when sg_rr_decode(7)='1' else sg_tmp_rr_data_6;
|
320 |
|
|
sg_tmp_rr_data_8 <= register_file(8) when sg_rr_decode(8)='1' else sg_tmp_rr_data_7;
|
321 |
|
|
sg_tmp_rr_data_9 <= register_file(9) when sg_rr_decode(9)='1' else sg_tmp_rr_data_8;
|
322 |
|
|
sg_tmp_rr_data_10 <= register_file(10) when sg_rr_decode(10)='1' else sg_tmp_rr_data_9;
|
323 |
|
|
sg_tmp_rr_data_11 <= register_file(11) when sg_rr_decode(11)='1' else sg_tmp_rr_data_10;
|
324 |
|
|
sg_tmp_rr_data_12 <= register_file(12) when sg_rr_decode(12)='1' else sg_tmp_rr_data_11;
|
325 |
|
|
sg_tmp_rr_data_13 <= register_file(13) when sg_rr_decode(13)='1' else sg_tmp_rr_data_12;
|
326 |
|
|
sg_tmp_rr_data_14 <= register_file(14) when sg_rr_decode(14)='1' else sg_tmp_rr_data_13;
|
327 |
|
|
sg_tmp_rr_data_15 <= register_file(15) when sg_rr_decode(15)='1' else sg_tmp_rr_data_14;
|
328 |
|
|
sg_tmp_rr_data_16 <= register_file(16) when sg_rr_decode(16)='1' else sg_tmp_rr_data_15;
|
329 |
|
|
sg_tmp_rr_data_17 <= register_file(17) when sg_rr_decode(17)='1' else sg_tmp_rr_data_16;
|
330 |
|
|
sg_tmp_rr_data_18 <= register_file(18) when sg_rr_decode(18)='1' else sg_tmp_rr_data_17;
|
331 |
|
|
sg_tmp_rr_data_19 <= register_file(19) when sg_rr_decode(19)='1' else sg_tmp_rr_data_18;
|
332 |
|
|
sg_tmp_rr_data_20 <= register_file(20) when sg_rr_decode(20)='1' else sg_tmp_rr_data_19;
|
333 |
|
|
sg_tmp_rr_data_21 <= register_file(21) when sg_rr_decode(21)='1' else sg_tmp_rr_data_20;
|
334 |
|
|
sg_tmp_rr_data_22 <= register_file(22) when sg_rr_decode(22)='1' else sg_tmp_rr_data_21;
|
335 |
|
|
sg_tmp_rr_data_23 <= register_file(23) when sg_rr_decode(23)='1' else sg_tmp_rr_data_22;
|
336 |
|
|
sg_tmp_rr_data_24 <= register_file(24) when sg_rr_decode(24)='1' else sg_tmp_rr_data_23;
|
337 |
|
|
sg_tmp_rr_data_25 <= register_file(25) when sg_rr_decode(25)='1' else sg_tmp_rr_data_24;
|
338 |
|
|
sg_tmp_rr_data_26 <= r26h when sg_rr_decode(26)='1' else sg_tmp_rr_data_25;
|
339 |
|
|
sg_tmp_rr_data_27 <= r27h when sg_rr_decode(27)='1' else sg_tmp_rr_data_26;
|
340 |
|
|
sg_tmp_rr_data_28 <= r28h when sg_rr_decode(28)='1' else sg_tmp_rr_data_27;
|
341 |
|
|
sg_tmp_rr_data_29 <= r29h when sg_rr_decode(29)='1' else sg_tmp_rr_data_28;
|
342 |
|
|
sg_tmp_rr_data_30 <= r30h when sg_rr_decode(30)='1' else sg_tmp_rr_data_29;
|
343 |
|
|
sg_tmp_rr_data_31 <= r31h when sg_rr_decode(31)='1' else sg_tmp_rr_data_30;
|
344 |
|
|
reg_rr_out <= sg_tmp_rr_data_31;
|
345 |
|
|
|
346 |
|
|
|
347 |
|
|
h_dat_mux_l:for i in 0 to 7 generate
|
348 |
|
|
sg_tmp_h_data(i) <= (r26h_cml_1(i) and reg_h_adr(0)) or (r28h_cml_1(i) and reg_h_adr(1)) or (r30h_cml_1(i) and reg_h_adr(2));
|
349 |
|
|
end generate;
|
350 |
|
|
h_dat_mux_h:for i in 8 to 15 generate
|
351 |
|
|
-- SynEDA CoreMultiplier
|
352 |
|
|
-- assignment(s): sg_tmp_h_data
|
353 |
|
|
-- replace(s): r26h, r27h, r28h, r29h, r30h, r31h
|
354 |
|
|
|
355 |
|
|
sg_tmp_h_data(i) <= (r27h_cml_1(i-8) and reg_h_adr(0)) or (r29h_cml_1(i-8) and reg_h_adr(1)) or (r31h_cml_1(i-8) and reg_h_adr(2));
|
356 |
|
|
end generate;
|
357 |
|
|
|
358 |
|
|
|
359 |
|
|
sg_adr16_postinc <= sg_tmp_h_data +1;
|
360 |
|
|
sg_adr16_predec <= sg_tmp_h_data -1;
|
361 |
|
|
-- OUTPUT TO THE ADDRESS BUS
|
362 |
|
|
reg_h_out <= sg_adr16_predec when (pre_dec='1') else -- PREDECREMENT
|
363 |
|
|
sg_tmp_h_data; -- NO PREDECREMENT
|
364 |
|
|
|
365 |
|
|
-- TO REGISTERS
|
366 |
|
|
reg_h_in <= sg_adr16_postinc when (post_inc='1') else -- POST INC
|
367 |
|
|
sg_adr16_predec; -- PRE DEC
|
368 |
|
|
|
369 |
|
|
-- Register file with global reset (for simulation)
|
370 |
|
|
|
371 |
|
|
RegFileWithRst:if CResetRegFile generate
|
372 |
|
|
|
373 |
|
|
-- SynEDA CoreMultiplier
|
374 |
|
|
-- assignment(s): register_file
|
375 |
|
|
-- replace(s): register_file
|
376 |
|
|
|
377 |
|
|
R0_R25:process(cp2,ireset)
|
378 |
|
|
begin
|
379 |
|
|
if ireset='0' then
|
380 |
|
|
for i in 0 to 25 loop
|
381 |
|
|
register_file(i) <= (others =>'0');
|
382 |
|
|
end loop;
|
383 |
|
|
elsif (cp2='1' and cp2'event) then register_file <= register_file_cml_1;
|
384 |
|
|
if (cp2en='1') then -- Clock enable
|
385 |
|
|
for i in 0 to 25 loop
|
386 |
|
|
if register_wr_en(i)='1' then
|
387 |
|
|
register_file(i) <= reg_rd_in;
|
388 |
|
|
end if;
|
389 |
|
|
end loop;
|
390 |
|
|
end if;
|
391 |
|
|
end if;
|
392 |
|
|
end process;
|
393 |
|
|
|
394 |
|
|
|
395 |
|
|
-- SynEDA CoreMultiplier
|
396 |
|
|
-- assignment(s): r26h
|
397 |
|
|
-- replace(s): r26h
|
398 |
|
|
|
399 |
|
|
-- R26 (LOW)
|
400 |
|
|
R26:process(cp2,ireset)
|
401 |
|
|
begin
|
402 |
|
|
if ireset='0' then
|
403 |
|
|
r26h <= (others =>'0');
|
404 |
|
|
elsif (cp2='1' and cp2'event) then r26h <= r26h_cml_1;
|
405 |
|
|
if (cp2en='1') then -- Clock enable
|
406 |
|
|
if register_wr_en(26)='1' then
|
407 |
|
|
r26h <= reg_rd_in;
|
408 |
|
|
elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
|
409 |
|
|
r26h <= reg_h_in(7 downto 0);
|
410 |
|
|
end if;
|
411 |
|
|
end if;
|
412 |
|
|
end if;
|
413 |
|
|
end process;
|
414 |
|
|
|
415 |
|
|
-- SynEDA CoreMultiplier
|
416 |
|
|
-- assignment(s): r27h
|
417 |
|
|
-- replace(s): r27h
|
418 |
|
|
|
419 |
|
|
-- R27 (HIGH)
|
420 |
|
|
R27:process(cp2,ireset)
|
421 |
|
|
begin
|
422 |
|
|
if ireset='0' then
|
423 |
|
|
r27h <= (others =>'0');
|
424 |
|
|
elsif (cp2='1' and cp2'event) then r27h <= r27h_cml_1;
|
425 |
|
|
if (cp2en='1') then -- Clock enable
|
426 |
|
|
if register_wr_en(27)='1' then
|
427 |
|
|
r27h <= reg_rd_in;
|
428 |
|
|
elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
|
429 |
|
|
r27h <= reg_h_in(15 downto 8);
|
430 |
|
|
end if;
|
431 |
|
|
end if;
|
432 |
|
|
end if;
|
433 |
|
|
end process;
|
434 |
|
|
|
435 |
|
|
-- SynEDA CoreMultiplier
|
436 |
|
|
-- assignment(s): r28h
|
437 |
|
|
-- replace(s): r28h
|
438 |
|
|
|
439 |
|
|
-- R28 (LOW)
|
440 |
|
|
R28:process(cp2,ireset)
|
441 |
|
|
begin
|
442 |
|
|
if ireset='0' then
|
443 |
|
|
r28h <= (others =>'0');
|
444 |
|
|
elsif (cp2='1' and cp2'event) then r28h <= r28h_cml_1;
|
445 |
|
|
if (cp2en='1') then -- Clock enable
|
446 |
|
|
if register_wr_en(28)='1' then
|
447 |
|
|
r28h <= reg_rd_in;
|
448 |
|
|
elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
|
449 |
|
|
r28h <= reg_h_in(7 downto 0);
|
450 |
|
|
end if;
|
451 |
|
|
end if;
|
452 |
|
|
end if;
|
453 |
|
|
end process;
|
454 |
|
|
|
455 |
|
|
-- SynEDA CoreMultiplier
|
456 |
|
|
-- assignment(s): r29h
|
457 |
|
|
-- replace(s): r29h
|
458 |
|
|
|
459 |
|
|
-- R29 (HIGH)
|
460 |
|
|
R29:process(cp2,ireset)
|
461 |
|
|
begin
|
462 |
|
|
if ireset='0' then
|
463 |
|
|
r29h <= (others =>'0');
|
464 |
|
|
elsif (cp2='1' and cp2'event) then r29h <= r29h_cml_1;
|
465 |
|
|
if (cp2en='1') then -- Clock enable
|
466 |
|
|
if register_wr_en(29)='1' then
|
467 |
|
|
r29h <= reg_rd_in;
|
468 |
|
|
elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
|
469 |
|
|
r29h <= reg_h_in(15 downto 8);
|
470 |
|
|
end if;
|
471 |
|
|
end if;
|
472 |
|
|
end if;
|
473 |
|
|
end process;
|
474 |
|
|
|
475 |
|
|
-- SynEDA CoreMultiplier
|
476 |
|
|
-- assignment(s): r30h
|
477 |
|
|
-- replace(s): r30h
|
478 |
|
|
|
479 |
|
|
-- R30 (LOW)
|
480 |
|
|
R30:process(cp2,ireset)
|
481 |
|
|
begin
|
482 |
|
|
if ireset='0' then
|
483 |
|
|
r30h <= (others =>'0');
|
484 |
|
|
elsif (cp2='1' and cp2'event) then r30h <= r30h_cml_1;
|
485 |
|
|
if (cp2en='1') then -- Clock enable
|
486 |
|
|
if register_wr_en(30)='1' then
|
487 |
|
|
r30h <= reg_rd_in;
|
488 |
|
|
elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
|
489 |
|
|
r30h <= reg_h_in(7 downto 0);
|
490 |
|
|
end if;
|
491 |
|
|
end if;
|
492 |
|
|
end if;
|
493 |
|
|
end process;
|
494 |
|
|
|
495 |
|
|
-- SynEDA CoreMultiplier
|
496 |
|
|
-- assignment(s): r31h
|
497 |
|
|
-- replace(s): r31h
|
498 |
|
|
|
499 |
|
|
-- R31 (HIGH)
|
500 |
|
|
R31:process(cp2,ireset)
|
501 |
|
|
begin
|
502 |
|
|
if ireset='0' then
|
503 |
|
|
r31h <= (others =>'0');
|
504 |
|
|
elsif (cp2='1' and cp2'event) then r31h <= r31h_cml_1;
|
505 |
|
|
if (cp2en='1') then -- Clock enable
|
506 |
|
|
if register_wr_en(31)='1' then
|
507 |
|
|
r31h <= reg_rd_in;
|
508 |
|
|
elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
|
509 |
|
|
r31h <= reg_h_in(15 downto 8);
|
510 |
|
|
end if;
|
511 |
|
|
end if;
|
512 |
|
|
end if;
|
513 |
|
|
end process;
|
514 |
|
|
|
515 |
|
|
end generate;
|
516 |
|
|
|
517 |
|
|
|
518 |
|
|
-- Register file without global reset (for synthesis)
|
519 |
|
|
|
520 |
|
|
RegFileWithoutRst:if not CResetRegFile generate
|
521 |
|
|
|
522 |
|
|
R0_R25:process(cp2)
|
523 |
|
|
begin
|
524 |
|
|
if (cp2='1' and cp2'event) then
|
525 |
|
|
if (cp2en='1') then -- Clock enable
|
526 |
|
|
for i in 0 to 25 loop
|
527 |
|
|
if register_wr_en(i)='1' then
|
528 |
|
|
register_file(i) <= reg_rd_in;
|
529 |
|
|
end if;
|
530 |
|
|
end loop;
|
531 |
|
|
end if;
|
532 |
|
|
end if;
|
533 |
|
|
end process;
|
534 |
|
|
|
535 |
|
|
|
536 |
|
|
-- R26 (LOW)
|
537 |
|
|
R26:process(cp2)
|
538 |
|
|
begin
|
539 |
|
|
if (cp2='1' and cp2'event) then
|
540 |
|
|
if (cp2en='1') then -- Clock enable
|
541 |
|
|
if register_wr_en(26)='1' then
|
542 |
|
|
r26h <= reg_rd_in;
|
543 |
|
|
elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
|
544 |
|
|
r26h <= reg_h_in(7 downto 0);
|
545 |
|
|
end if;
|
546 |
|
|
end if;
|
547 |
|
|
end if;
|
548 |
|
|
end process;
|
549 |
|
|
|
550 |
|
|
-- R27 (HIGH)
|
551 |
|
|
R27:process(cp2)
|
552 |
|
|
begin
|
553 |
|
|
if (cp2='1' and cp2'event) then
|
554 |
|
|
if (cp2en='1') then -- Clock enable
|
555 |
|
|
if register_wr_en(27)='1' then
|
556 |
|
|
r27h <= reg_rd_in;
|
557 |
|
|
elsif (reg_h_adr(0)='1'and reg_h_wr='1') then
|
558 |
|
|
r27h <= reg_h_in(15 downto 8);
|
559 |
|
|
end if;
|
560 |
|
|
end if;
|
561 |
|
|
end if;
|
562 |
|
|
end process;
|
563 |
|
|
|
564 |
|
|
-- R28 (LOW)
|
565 |
|
|
R28:process(cp2)
|
566 |
|
|
begin
|
567 |
|
|
if (cp2='1' and cp2'event) then
|
568 |
|
|
if (cp2en='1') then -- Clock enable
|
569 |
|
|
if register_wr_en(28)='1' then
|
570 |
|
|
r28h <= reg_rd_in;
|
571 |
|
|
elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
|
572 |
|
|
r28h <= reg_h_in(7 downto 0);
|
573 |
|
|
end if;
|
574 |
|
|
end if;
|
575 |
|
|
end if;
|
576 |
|
|
end process;
|
577 |
|
|
|
578 |
|
|
-- R29 (HIGH)
|
579 |
|
|
R29:process(cp2)
|
580 |
|
|
begin
|
581 |
|
|
if (cp2='1' and cp2'event) then
|
582 |
|
|
if (cp2en='1') then -- Clock enable
|
583 |
|
|
if register_wr_en(29)='1' then
|
584 |
|
|
r29h <= reg_rd_in;
|
585 |
|
|
elsif (reg_h_adr(1)='1'and reg_h_wr='1') then
|
586 |
|
|
r29h <= reg_h_in(15 downto 8);
|
587 |
|
|
end if;
|
588 |
|
|
end if;
|
589 |
|
|
end if;
|
590 |
|
|
end process;
|
591 |
|
|
|
592 |
|
|
-- R30 (LOW)
|
593 |
|
|
R30:process(cp2)
|
594 |
|
|
begin
|
595 |
|
|
if (cp2='1' and cp2'event) then
|
596 |
|
|
if (cp2en='1') then -- Clock enable
|
597 |
|
|
if register_wr_en(30)='1' then
|
598 |
|
|
r30h <= reg_rd_in;
|
599 |
|
|
elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
|
600 |
|
|
r30h <= reg_h_in(7 downto 0);
|
601 |
|
|
end if;
|
602 |
|
|
end if;
|
603 |
|
|
end if;
|
604 |
|
|
end process;
|
605 |
|
|
|
606 |
|
|
-- R31 (HIGH)
|
607 |
|
|
R31:process(cp2)
|
608 |
|
|
begin
|
609 |
|
|
if (cp2='1' and cp2'event) then
|
610 |
|
|
if (cp2en='1') then -- Clock enable
|
611 |
|
|
if register_wr_en(31)='1' then
|
612 |
|
|
r31h <= reg_rd_in;
|
613 |
|
|
elsif (reg_h_adr(2)='1'and reg_h_wr='1') then
|
614 |
|
|
r31h <= reg_h_in(15 downto 8);
|
615 |
|
|
end if;
|
616 |
|
|
end if;
|
617 |
|
|
end if;
|
618 |
|
|
end process;
|
619 |
|
|
|
620 |
|
|
end generate;
|
621 |
|
|
|
622 |
|
|
end RTL;
|