1 |
2 |
tobil |
--************************************************************************************************
|
2 |
|
|
-- PM_FETCH_DEC(internal module) for AVR core
|
3 |
|
|
-- Version 2.6! (Special version for the JTAG OCD)
|
4 |
|
|
-- Designed by Ruslan Lepetenok 14.11.2001
|
5 |
|
|
-- Modified 31.05.06
|
6 |
|
|
-- Modification:
|
7 |
|
|
-- Registered ramre/ramwe outputs
|
8 |
|
|
-- cpu_busy logic modified(affects RCALL/ICALL/CALL instruction interract with interrupt)
|
9 |
|
|
-- SLEEP and CLRWDT instructions support was added
|
10 |
|
|
-- V-flag bug fixed (AND/ANDI/OR/ORI/EOR)
|
11 |
|
|
-- V-flag bug fixed (ADIW/SBIW)
|
12 |
|
|
-- Unused outputs(sreg_bit_num[2..0],idc_sbi_out,idc_cbi_out,idc_bld_out) were removed.
|
13 |
|
|
-- Output alu_data_d_in[7..0] was removed.
|
14 |
|
|
-- Gloabal clock enable(cp2en) was added
|
15 |
|
|
-- cpu_busy(push/pop) + irq bug was fixed 14.07.05
|
16 |
|
|
-- BRXX+IRQ interaction was modified -> cpu_busy
|
17 |
|
|
-- LDS/STS now requires only two cycles for execution (13.01.06 -> last modificatioon)
|
18 |
|
|
--************************************************************************************************
|
19 |
|
|
|
20 |
|
|
library IEEE;
|
21 |
|
|
use IEEE.std_logic_1164.all;
|
22 |
|
|
use IEEE.std_logic_unsigned.all;
|
23 |
|
|
|
24 |
|
|
use WORK.AVRuCPackage.all;
|
25 |
|
|
|
26 |
|
|
entity pm_fetch_dec_cm4 is port(
|
27 |
|
|
cp2_cml_1 : in std_logic;
|
28 |
|
|
cp2_cml_2 : in std_logic;
|
29 |
|
|
cp2_cml_3 : in std_logic;
|
30 |
|
|
|
31 |
|
|
-- Clock and reset
|
32 |
|
|
cp2 : in std_logic;
|
33 |
|
|
cp2en : in std_logic;
|
34 |
|
|
ireset : in std_logic;
|
35 |
|
|
-- JTAG OCD support
|
36 |
|
|
valid_instr : out std_logic;
|
37 |
|
|
insert_nop : in std_logic;
|
38 |
|
|
block_irq : in std_logic;
|
39 |
|
|
change_flow : out std_logic;
|
40 |
|
|
-- Program memory
|
41 |
|
|
pc : out std_logic_vector (15 downto 0);
|
42 |
|
|
inst : in std_logic_vector (15 downto 0);
|
43 |
|
|
-- I/O control
|
44 |
|
|
adr : out std_logic_vector (5 downto 0);
|
45 |
|
|
iore : out std_logic;
|
46 |
|
|
iowe : out std_logic;
|
47 |
|
|
-- Data memory control
|
48 |
|
|
ramadr : out std_logic_vector (15 downto 0);
|
49 |
|
|
ramre : out std_logic;
|
50 |
|
|
ramwe : out std_logic;
|
51 |
|
|
cpuwait : in std_logic;
|
52 |
|
|
-- Data paths
|
53 |
|
|
dbusin : in std_logic_vector (7 downto 0);
|
54 |
|
|
dbusout : out std_logic_vector (7 downto 0);
|
55 |
|
|
dbusout_int_route : out std_logic_vector (7 downto 0);
|
56 |
|
|
-- Interrupt
|
57 |
|
|
irqlines : in std_logic_vector (22 downto 0);
|
58 |
|
|
irqack : out std_logic;
|
59 |
|
|
irqackad : out std_logic_vector(4 downto 0);
|
60 |
|
|
--Sleep
|
61 |
|
|
sleepi : out std_logic;
|
62 |
|
|
irqok : out std_logic;
|
63 |
|
|
--Watchdog
|
64 |
|
|
wdri : out std_logic;
|
65 |
|
|
-- ALU interface(Data inputs)
|
66 |
|
|
alu_data_r_in : out std_logic_vector(7 downto 0);
|
67 |
|
|
-- ALU interface(Instruction inputs)
|
68 |
|
|
idc_add_out : out std_logic;
|
69 |
|
|
idc_adc_out : out std_logic;
|
70 |
|
|
idc_adiw_out : out std_logic;
|
71 |
|
|
idc_sub_out : out std_logic;
|
72 |
|
|
idc_subi_out : out std_logic;
|
73 |
|
|
idc_sbc_out : out std_logic;
|
74 |
|
|
idc_sbci_out : out std_logic;
|
75 |
|
|
idc_sbiw_out : out std_logic;
|
76 |
|
|
|
77 |
|
|
adiw_st_out : out std_logic;
|
78 |
|
|
sbiw_st_out : out std_logic;
|
79 |
|
|
|
80 |
|
|
idc_and_out : out std_logic;
|
81 |
|
|
idc_andi_out : out std_logic;
|
82 |
|
|
idc_or_out : out std_logic;
|
83 |
|
|
idc_ori_out : out std_logic;
|
84 |
|
|
idc_eor_out : out std_logic;
|
85 |
|
|
idc_com_out : out std_logic;
|
86 |
|
|
idc_neg_out : out std_logic;
|
87 |
|
|
|
88 |
|
|
idc_inc_out : out std_logic;
|
89 |
|
|
idc_dec_out : out std_logic;
|
90 |
|
|
|
91 |
|
|
idc_cp_out : out std_logic;
|
92 |
|
|
idc_cpc_out : out std_logic;
|
93 |
|
|
idc_cpi_out : out std_logic;
|
94 |
|
|
idc_cpse_out : out std_logic;
|
95 |
|
|
|
96 |
|
|
idc_lsr_out : out std_logic;
|
97 |
|
|
idc_ror_out : out std_logic;
|
98 |
|
|
idc_asr_out : out std_logic;
|
99 |
|
|
idc_swap_out : out std_logic;
|
100 |
|
|
|
101 |
|
|
-- ALU interface(Data output)
|
102 |
|
|
alu_data_out : in std_logic_vector(7 downto 0);
|
103 |
|
|
|
104 |
|
|
-- ALU interface(Flag outputs)
|
105 |
|
|
alu_c_flag_out : in std_logic;
|
106 |
|
|
alu_z_flag_out : in std_logic;
|
107 |
|
|
alu_n_flag_out : in std_logic;
|
108 |
|
|
alu_v_flag_out : in std_logic;
|
109 |
|
|
alu_s_flag_out : in std_logic;
|
110 |
|
|
alu_h_flag_out : in std_logic;
|
111 |
|
|
|
112 |
|
|
-- General purpose register file interface
|
113 |
|
|
reg_rd_in : out std_logic_vector (7 downto 0);
|
114 |
|
|
reg_rd_out : in std_logic_vector (7 downto 0);
|
115 |
|
|
reg_rd_out_int : in std_logic_vector(7 downto 0);
|
116 |
|
|
reg_rd_adr : out std_logic_vector (4 downto 0);
|
117 |
|
|
reg_rd_adr_int : out std_logic_vector (4 downto 0);
|
118 |
|
|
reg_rr_out : in std_logic_vector (7 downto 0);
|
119 |
|
|
reg_rr_adr : out std_logic_vector (4 downto 0);
|
120 |
|
|
reg_rd_wr : out std_logic;
|
121 |
|
|
|
122 |
|
|
post_inc : out std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS
|
123 |
|
|
pre_dec : out std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
|
124 |
|
|
reg_h_wr : out std_logic;
|
125 |
|
|
reg_h_out : in std_logic_vector (15 downto 0);
|
126 |
|
|
reg_h_adr : out std_logic_vector (2 downto 0); -- x,y,z
|
127 |
|
|
reg_z_out : in std_logic_vector (15 downto 0); -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
|
128 |
|
|
|
129 |
|
|
-- I/O register file interface
|
130 |
|
|
sreg_fl_in : out std_logic_vector(7 downto 0);
|
131 |
|
|
globint : in std_logic; -- SREG I flag
|
132 |
|
|
|
133 |
|
|
sreg_fl_wr_en : out std_logic_vector(7 downto 0); --FLAGS WRITE ENABLE SIGNALS
|
134 |
|
|
|
135 |
|
|
spl_out : in std_logic_vector(7 downto 0);
|
136 |
|
|
sph_out : in std_logic_vector(7 downto 0);
|
137 |
|
|
sp_ndown_up : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
|
138 |
|
|
sp_en : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
|
139 |
|
|
|
140 |
|
|
rampz_out : in std_logic_vector(7 downto 0);
|
141 |
|
|
|
142 |
|
|
-- Bit processor interface
|
143 |
|
|
bit_num_r_io : out std_logic_vector (2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS
|
144 |
|
|
bitpr_io_out : in std_logic_vector(7 downto 0); -- SBI/CBI OUT
|
145 |
|
|
branch : out std_logic_vector (2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION
|
146 |
|
|
bit_pr_sreg_out : in std_logic_vector(7 downto 0); -- BCLR/BSET/BST(T-FLAG ONLY)
|
147 |
|
|
bld_op_out : in std_logic_vector(7 downto 0); -- BLD OUT (T FLAG)
|
148 |
|
|
bit_test_op_out : in std_logic; -- OUTPUT OF SBIC/SBIS/SBRS/SBRC
|
149 |
|
|
|
150 |
|
|
sbi_st_out : out std_logic;
|
151 |
|
|
cbi_st_out : out std_logic;
|
152 |
|
|
|
153 |
|
|
idc_bst_out : out std_logic;
|
154 |
|
|
idc_bset_out : out std_logic;
|
155 |
|
|
idc_bclr_out : out std_logic;
|
156 |
|
|
|
157 |
|
|
idc_sbic_out : out std_logic;
|
158 |
|
|
idc_sbis_out : out std_logic;
|
159 |
|
|
|
160 |
|
|
idc_sbrs_out : out std_logic;
|
161 |
|
|
idc_sbrc_out : out std_logic;
|
162 |
|
|
|
163 |
|
|
idc_brbs_out : out std_logic;
|
164 |
|
|
idc_brbc_out : out std_logic;
|
165 |
|
|
|
166 |
|
|
idc_reti_out : out std_logic);
|
167 |
|
|
end pm_fetch_dec_cm4;
|
168 |
|
|
|
169 |
|
|
architecture RTL of pm_fetch_dec_cm4 is
|
170 |
|
|
|
171 |
|
|
-- COPIES OF OUTPUTS
|
172 |
|
|
signal ramadr_reg_in : std_logic_vector(15 downto 0); -- INPUT OF THE ADDRESS REGISTER
|
173 |
|
|
signal ramadr_reg_en : std_logic; -- ADRESS REGISTER CLOCK ENABLE SIGNAL
|
174 |
|
|
|
175 |
|
|
signal irqack_int : std_logic;
|
176 |
|
|
signal irqackad_int : std_logic_vector(irqackad'range);
|
177 |
|
|
|
178 |
|
|
-- ####################################################
|
179 |
|
|
-- INTERNAL SIGNALS
|
180 |
|
|
-- ####################################################
|
181 |
|
|
|
182 |
|
|
-- NEW SIGNALS
|
183 |
|
|
signal two_word_inst : std_logic; -- CALL/JMP/STS/LDS INSTRUCTION INDICATOR
|
184 |
|
|
|
185 |
|
|
signal ram_adr_int : std_logic_vector (15 downto 0);
|
186 |
|
|
constant const_ram_to_reg : std_logic_vector := "00000000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19
|
187 |
|
|
constant const_ram_to_io_a : std_logic_vector := "00000000001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
|
188 |
|
|
constant const_ram_to_io_b : std_logic_vector := "00000000010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
|
189 |
|
|
|
190 |
|
|
-- LD/LDD/ST/STD SIGNALS
|
191 |
|
|
signal adiw_sbiw_encoder_out : std_logic_vector (4 downto 0);
|
192 |
|
|
signal adiw_sbiw_encoder_mux_out : std_logic_vector (4 downto 0);
|
193 |
|
|
|
194 |
|
|
|
195 |
|
|
-- PROGRAM COUNTER SIGNALS
|
196 |
|
|
signal program_counter_tmp : std_logic_vector (15 downto 0); -- TO STORE PC DURING LPM/ELPM INSTRUCTIONS
|
197 |
|
|
signal program_counter : std_logic_vector (15 downto 0);
|
198 |
|
|
signal program_counter_in : std_logic_vector (15 downto 0);
|
199 |
|
|
signal program_counter_high_fr : std_logic_vector (7 downto 0); -- TO STORE PC FOR CALL,IRQ,RCALL,ICALL
|
200 |
|
|
|
201 |
|
|
signal pc_low : std_logic_vector (7 downto 0);
|
202 |
|
|
signal pc_high : std_logic_vector (7 downto 0);
|
203 |
|
|
|
204 |
|
|
|
205 |
|
|
signal pc_low_en : std_logic;
|
206 |
|
|
signal pc_high_en : std_logic;
|
207 |
|
|
|
208 |
|
|
signal offset_brbx : std_logic_vector (15 downto 0); -- OFFSET FOR BRCS/BRCC INSTRUCTION !!CHECKED
|
209 |
|
|
signal offset_rxx : std_logic_vector (15 downto 0); -- OFFSET FOR RJMP/RCALL INSTRUCTION !!CHECKED
|
210 |
|
|
|
211 |
|
|
signal pa15_pm : std_logic; -- ADDRESS LINE 15 FOR LPM/ELPM INSTRUCTIONS ('0' FOR LPM,RAMPZ(0) FOR ELPM)
|
212 |
|
|
|
213 |
|
|
signal alu_reg_wr : std_logic; -- ALU INSTRUCTIONS PRODUCING WRITE TO THE GENERAL PURPOSE REGISTER FILE
|
214 |
|
|
|
215 |
|
|
-- DATA MEMORY,GENERAL PURPOSE REGISTERS AND I/O REGISTERS LOGIC
|
216 |
|
|
|
217 |
|
|
--! IMPORTANT NOTICE : OPERATIONS WHICH USE STACK POINTER (SPH:SPL) CAN NOT ACCCSESS GENERAL
|
218 |
|
|
-- PURPOSE REGISTER FILE AND INPUT/OUTPUT REGISTER FILE !
|
219 |
|
|
-- THESE OPERATIONS ARE : RCALL/ICALL/CALL/RET/RETI/PUSH/POP INSTRUCTIONS AND INTERRUPT
|
220 |
|
|
|
221 |
|
|
signal reg_file_adr_space : std_logic; -- ACCSESS TO THE REGISTER FILE
|
222 |
|
|
signal io_file_adr_space : std_logic; -- ACCSESS TO THE I/O FILE
|
223 |
|
|
|
224 |
|
|
-- STATE MACHINES SIGNALS
|
225 |
|
|
signal irq_start : std_logic;
|
226 |
|
|
|
227 |
|
|
signal nirq_st0 : std_logic;
|
228 |
|
|
signal irq_st1 : std_logic;
|
229 |
|
|
signal irq_st2 : std_logic;
|
230 |
|
|
signal irq_st3 : std_logic;
|
231 |
|
|
|
232 |
|
|
signal ncall_st0 : std_logic;
|
233 |
|
|
signal call_st1 : std_logic;
|
234 |
|
|
signal call_st2 : std_logic;
|
235 |
|
|
signal call_st3 : std_logic;
|
236 |
|
|
|
237 |
|
|
signal nrcall_st0 : std_logic;
|
238 |
|
|
signal rcall_st1 : std_logic;
|
239 |
|
|
signal rcall_st2 : std_logic;
|
240 |
|
|
|
241 |
|
|
signal nicall_st0 : std_logic;
|
242 |
|
|
signal icall_st1 : std_logic;
|
243 |
|
|
signal icall_st2 : std_logic;
|
244 |
|
|
|
245 |
|
|
signal njmp_st0 : std_logic;
|
246 |
|
|
signal jmp_st1 : std_logic;
|
247 |
|
|
signal jmp_st2 : std_logic;
|
248 |
|
|
|
249 |
|
|
signal ijmp_st : std_logic;
|
250 |
|
|
|
251 |
|
|
signal rjmp_st : std_logic;
|
252 |
|
|
|
253 |
|
|
signal nret_st0 : std_logic;
|
254 |
|
|
signal ret_st1 : std_logic;
|
255 |
|
|
signal ret_st2 : std_logic;
|
256 |
|
|
signal ret_st3 : std_logic;
|
257 |
|
|
|
258 |
|
|
signal nreti_st0 : std_logic;
|
259 |
|
|
signal reti_st1 : std_logic;
|
260 |
|
|
signal reti_st2 : std_logic;
|
261 |
|
|
signal reti_st3 : std_logic;
|
262 |
|
|
|
263 |
|
|
signal brxx_st : std_logic; -- BRANCHES
|
264 |
|
|
|
265 |
|
|
signal adiw_st : std_logic;
|
266 |
|
|
signal sbiw_st : std_logic;
|
267 |
|
|
|
268 |
|
|
signal nskip_inst_st0 : std_logic;
|
269 |
|
|
signal skip_inst_st1 : std_logic;
|
270 |
|
|
signal skip_inst_st2 : std_logic; -- ALL SKIP INSTRUCTIONS SBRS/SBRC/SBIS/SBIC/CPSE
|
271 |
|
|
|
272 |
|
|
signal skip_inst_start : std_logic;
|
273 |
|
|
|
274 |
|
|
signal nlpm_st0 : std_logic;
|
275 |
|
|
signal lpm_st1 : std_logic;
|
276 |
|
|
signal lpm_st2 : std_logic;
|
277 |
|
|
|
278 |
|
|
signal nelpm_st0 : std_logic;
|
279 |
|
|
signal elpm_st1 : std_logic;
|
280 |
|
|
signal elpm_st2 : std_logic;
|
281 |
|
|
|
282 |
|
|
--signal nsts_st0 : std_logic;
|
283 |
|
|
--signal sts_st1 : std_logic;
|
284 |
|
|
--signal sts_st2 : std_logic;
|
285 |
|
|
|
286 |
|
|
signal sts_st : std_logic;
|
287 |
|
|
|
288 |
|
|
--signal nlds_st0 : std_logic;
|
289 |
|
|
--signal lds_st1 : std_logic;
|
290 |
|
|
--signal lds_st2 : std_logic;
|
291 |
|
|
|
292 |
|
|
signal lds_st : std_logic;
|
293 |
|
|
|
294 |
|
|
signal st_st : std_logic;
|
295 |
|
|
signal ld_st : std_logic;
|
296 |
|
|
|
297 |
|
|
signal sbi_st : std_logic;
|
298 |
|
|
signal cbi_st : std_logic;
|
299 |
|
|
|
300 |
|
|
signal push_st : std_logic;
|
301 |
|
|
signal pop_st : std_logic;
|
302 |
|
|
|
303 |
|
|
-- INTERNAL STATE MACHINES
|
304 |
|
|
signal nop_insert_st : std_logic;
|
305 |
|
|
signal cpu_busy : std_logic;
|
306 |
|
|
|
307 |
|
|
-- INTERNAL COPIES OF OUTPUTS
|
308 |
|
|
signal pc_int : std_logic_vector (15 downto 0);
|
309 |
|
|
signal adr_int : std_logic_vector (5 downto 0);
|
310 |
|
|
signal iore_int : std_logic;
|
311 |
|
|
signal iowe_int : std_logic;
|
312 |
|
|
signal ramadr_int : std_logic_vector (15 downto 0);
|
313 |
|
|
signal ramre_int : std_logic;
|
314 |
|
|
signal ramwe_int : std_logic;
|
315 |
|
|
signal dbusout_int : std_logic_vector (7 downto 0);
|
316 |
|
|
|
317 |
|
|
-- COMMAND REGISTER
|
318 |
|
|
signal instruction_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER
|
319 |
|
|
signal instruction_code_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER WITH NOP INSERTION
|
320 |
|
|
signal instruction_reg_ena : std_logic; -- CLOCK ENABLE
|
321 |
|
|
|
322 |
|
|
|
323 |
|
|
-- IRQ INTERNAL LOGIC
|
324 |
|
|
signal irq_int : std_logic;
|
325 |
|
|
signal irq_vector_adr : std_logic_vector(15 downto 0);
|
326 |
|
|
|
327 |
|
|
-- INTERRUPT RELATING REGISTERS
|
328 |
|
|
signal pc_for_interrupt : std_logic_vector(15 downto 0);
|
329 |
|
|
|
330 |
|
|
-- DATA EXTRACTOR SIGNALS
|
331 |
|
|
signal dex_dat8_immed : std_logic_vector (7 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ANDI,ORI,SUBI,SBCI,CPI,LDI
|
332 |
|
|
signal dex_dat6_immed : std_logic_vector (5 downto 0); -- IMMEDIATE CONSTANT (DATA) -> ADIW,SBIW
|
333 |
|
|
signal dex_adr12mem_s : std_logic_vector (11 downto 0); -- RELATIVE ADDRESS (SIGNED) -> RCALL,RJMP
|
334 |
|
|
signal dex_adr6port : std_logic_vector (5 downto 0); -- I/O PORT ADDRESS -> IN,OUT
|
335 |
|
|
signal dex_adr5port : std_logic_vector (4 downto 0); -- I/O PORT ADDRESS -> CBI,SBI,SBIC,SBIS
|
336 |
|
|
signal dex_adr_disp : std_logic_vector (5 downto 0); -- DISPLACEMENT FO ADDDRESS -> STD,LDD
|
337 |
|
|
signal dex_condition : std_logic_vector (2 downto 0); -- CONDITION -> BRBC,BRBS
|
338 |
|
|
signal dex_bitnum_sreg : std_logic_vector (2 downto 0); -- NUMBER OF BIT IN SREG -> BCLR,BSET
|
339 |
|
|
signal dex_adrreg_r : std_logic_vector (4 downto 0); -- SOURCE REGISTER ADDRESS -> .......
|
340 |
|
|
signal dex_adrreg_d : std_logic_vector (4 downto 0); -- DESTINATION REGISTER ADDRESS -> ......
|
341 |
|
|
signal dex_bitop_bitnum : std_logic_vector(2 downto 0); -- NUMBER OF BIT FOR BIT ORIENTEDE OPERATION -> BST/BLD+SBI/CBI+SBIC/SBIS+SBRC/SBRS !! CHECKED
|
342 |
|
|
signal dex_brxx_offset : std_logic_vector (6 downto 0); -- RELATIVE ADDRESS (SIGNED) -> BRBC,BRBS !! CHECKED
|
343 |
|
|
signal dex_adiw_sbiw_reg_adr : std_logic_vector (1 downto 0); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS
|
344 |
|
|
|
345 |
|
|
signal dex_adrreg_d_latched : std_logic_vector (4 downto 0); -- STORE ADDRESS OF DESTINATION REGISTER FOR LDS/STS/POP INSTRUCTIONS
|
346 |
|
|
signal gp_reg_tmp : std_logic_vector (7 downto 0); -- STORE DATA FROM THE REGISTERS FOR STS,ST INSTRUCTIONS
|
347 |
|
|
signal cbi_sbi_io_adr_tmp : std_logic_vector (4 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION
|
348 |
|
|
signal cbi_sbi_bit_num_tmp : std_logic_vector (2 downto 0); -- STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION
|
349 |
|
|
|
350 |
|
|
-- INSTRUCTIONS DECODER SIGNALS
|
351 |
|
|
|
352 |
|
|
signal idc_adc : std_logic; -- INSTRUCTION ADC
|
353 |
|
|
signal idc_add : std_logic; -- INSTRUCTION ADD
|
354 |
|
|
signal idc_adiw : std_logic; -- INSTRUCTION ADIW
|
355 |
|
|
signal idc_and : std_logic; -- INSTRUCTION AND
|
356 |
|
|
signal idc_andi : std_logic; -- INSTRUCTION ANDI
|
357 |
|
|
signal idc_asr : std_logic; -- INSTRUCTION ASR
|
358 |
|
|
|
359 |
|
|
signal idc_bclr : std_logic; -- INSTRUCTION BCLR
|
360 |
|
|
signal idc_bld : std_logic; -- INSTRUCTION BLD
|
361 |
|
|
signal idc_brbc : std_logic; -- INSTRUCTION BRBC
|
362 |
|
|
signal idc_brbs : std_logic; -- INSTRUCTION BRBS
|
363 |
|
|
signal idc_bset : std_logic; -- INSTRUCTION BSET
|
364 |
|
|
signal idc_bst : std_logic; -- INSTRUCTION BST
|
365 |
|
|
|
366 |
|
|
signal idc_call : std_logic; -- INSTRUCTION CALL
|
367 |
|
|
signal idc_cbi : std_logic; -- INSTRUCTION CBI
|
368 |
|
|
signal idc_com : std_logic; -- INSTRUCTION COM
|
369 |
|
|
signal idc_cp : std_logic; -- INSTRUCTION CP
|
370 |
|
|
signal idc_cpc : std_logic; -- INSTRUCTION CPC
|
371 |
|
|
signal idc_cpi : std_logic; -- INSTRUCTION CPI
|
372 |
|
|
signal idc_cpse : std_logic; -- INSTRUCTION CPSE
|
373 |
|
|
|
374 |
|
|
signal idc_dec : std_logic; -- INSTRUCTION DEC
|
375 |
|
|
|
376 |
|
|
signal idc_elpm : std_logic; -- INSTRUCTION ELPM
|
377 |
|
|
signal idc_eor : std_logic; -- INSTRUCTION EOR
|
378 |
|
|
|
379 |
|
|
signal idc_icall : std_logic; -- INSTRUCTION ICALL
|
380 |
|
|
signal idc_ijmp : std_logic; -- INSTRUCTION IJMP
|
381 |
|
|
|
382 |
|
|
signal idc_in : std_logic; -- INSTRUCTION IN
|
383 |
|
|
signal idc_inc : std_logic; -- INSTRUCTION INC
|
384 |
|
|
|
385 |
|
|
signal idc_jmp : std_logic; -- INSTRUCTION JMP
|
386 |
|
|
|
387 |
|
|
signal idc_ld_x : std_logic; -- INSTRUCTION LD Rx,X ; LD Rx,X+ ;LD Rx,-X
|
388 |
|
|
signal idc_ld_y : std_logic; -- INSTRUCTION LD Rx,Y ; LD Rx,Y+ ;LD Rx,-Y
|
389 |
|
|
signal idc_ldd_y : std_logic; -- INSTRUCTION LDD Rx,Y+q
|
390 |
|
|
signal idc_ld_z : std_logic; -- INSTRUCTION LD Rx,Z ; LD Rx,Z+ ;LD Rx,-Z
|
391 |
|
|
signal idc_ldd_z : std_logic; -- INSTRUCTION LDD Rx,Z+q
|
392 |
|
|
|
393 |
|
|
signal idc_ldi : std_logic; -- INSTRUCTION LDI
|
394 |
|
|
signal idc_lds : std_logic; -- INSTRUCTION LDS
|
395 |
|
|
signal idc_lpm : std_logic; -- INSTRUCTION LPM
|
396 |
|
|
signal idc_lsr : std_logic; -- INSTRUCTION LSR
|
397 |
|
|
|
398 |
|
|
signal idc_mov : std_logic; -- INSTRUCTION MOV
|
399 |
|
|
signal idc_mul : std_logic; -- INSTRUCTION MUL
|
400 |
|
|
|
401 |
|
|
signal idc_neg : std_logic; -- INSTRUCTION NEG
|
402 |
|
|
signal idc_nop : std_logic; -- INSTRUCTION NOP
|
403 |
|
|
|
404 |
|
|
signal idc_or : std_logic; -- INSTRUCTION OR
|
405 |
|
|
signal idc_ori : std_logic; -- INSTRUCTION ORI
|
406 |
|
|
signal idc_out : std_logic; -- INSTRUCTION OUT
|
407 |
|
|
|
408 |
|
|
signal idc_pop : std_logic; -- INSTRUCTION POP
|
409 |
|
|
signal idc_push : std_logic; -- INSTRUCTION PUSH
|
410 |
|
|
|
411 |
|
|
signal idc_rcall : std_logic; -- INSTRUCTION RCALL
|
412 |
|
|
signal idc_ret : std_logic; -- INSTRUCTION RET
|
413 |
|
|
signal idc_reti : std_logic; -- INSTRUCTION RETI
|
414 |
|
|
signal idc_rjmp : std_logic; -- INSTRUCTION RJMP
|
415 |
|
|
signal idc_ror : std_logic; -- INSTRUCTION ROR
|
416 |
|
|
|
417 |
|
|
signal idc_sbc : std_logic; -- INSTRUCTION SBC
|
418 |
|
|
signal idc_sbci : std_logic; -- INSTRUCTION SBCI
|
419 |
|
|
signal idc_sbi : std_logic; -- INSTRUCTION SBI
|
420 |
|
|
signal idc_sbic : std_logic; -- INSTRUCTION SBIC
|
421 |
|
|
signal idc_sbis : std_logic; -- INSTRUCTION SBIS
|
422 |
|
|
signal idc_sbiw : std_logic; -- INSTRUCTION SBIW
|
423 |
|
|
signal idc_sbrc : std_logic; -- INSTRUCTION SBRC
|
424 |
|
|
signal idc_sbrs : std_logic; -- INSTRUCTION SBRS
|
425 |
|
|
signal idc_sleep : std_logic; -- INSTRUCTION SLEEP
|
426 |
|
|
|
427 |
|
|
signal idc_st_x : std_logic; -- INSTRUCTION LD X,Rx ; LD X+,Rx ;LD -X,Rx
|
428 |
|
|
signal idc_st_y : std_logic; -- INSTRUCTION LD Y,Rx ; LD Y+,Rx ;LD -Y,Rx
|
429 |
|
|
signal idc_std_y : std_logic; -- INSTRUCTION LDD Y+q,Rx
|
430 |
|
|
signal idc_st_z : std_logic; -- INSTRUCTION LD Z,Rx ; LD Z+,Rx ;LD -Z,Rx
|
431 |
|
|
signal idc_std_z : std_logic; -- INSTRUCTION LDD Z+q,Rx
|
432 |
|
|
|
433 |
|
|
signal idc_sts : std_logic; -- INSTRUCTION STS
|
434 |
|
|
signal idc_sub : std_logic; -- INSTRUCTION SUB
|
435 |
|
|
signal idc_subi : std_logic; -- INSTRUCTION SUBI
|
436 |
|
|
signal idc_swap : std_logic; -- INSTRUCTION SWAP
|
437 |
|
|
|
438 |
|
|
signal idc_wdr : std_logic; -- INSTRUCTION WDR
|
439 |
|
|
|
440 |
|
|
-- ADDITIONAL SIGNALS
|
441 |
|
|
signal idc_psinc : std_logic; -- POST INCREMENT FLAG FOR LD,ST INSTRUCTIONS
|
442 |
|
|
signal idc_prdec : std_logic; -- PRE DECREMENT FLAG FOR LD,ST INSTRUCTIONS
|
443 |
|
|
|
444 |
|
|
-- ##################################################
|
445 |
|
|
|
446 |
|
|
-- SREG FLAGS WRITE ENABLE SIGNALS
|
447 |
|
|
|
448 |
|
|
--alias sreg_c_wr_en : std_logic is sreg_fl_wr_en(0);
|
449 |
|
|
--alias sreg_z_wr_en : std_logic is sreg_fl_wr_en(1);
|
450 |
|
|
--alias sreg_n_wr_en : std_logic is sreg_fl_wr_en(2);
|
451 |
|
|
--alias sreg_v_wr_en : std_logic is sreg_fl_wr_en(3);
|
452 |
|
|
--alias sreg_s_wr_en : std_logic is sreg_fl_wr_en(4);
|
453 |
|
|
--alias sreg_h_wr_en : std_logic is sreg_fl_wr_en(5);
|
454 |
|
|
--alias sreg_t_wr_en : std_logic is sreg_fl_wr_en(6);
|
455 |
|
|
--alias sreg_i_wr_en : std_logic is sreg_fl_wr_en(7);
|
456 |
|
|
|
457 |
|
|
signal sreg_c_wr_en : std_logic; -- is sreg_fl_wr_en(0);
|
458 |
|
|
signal sreg_z_wr_en : std_logic; -- is sreg_fl_wr_en(1);
|
459 |
|
|
signal sreg_n_wr_en : std_logic; -- is sreg_fl_wr_en(2);
|
460 |
|
|
signal sreg_v_wr_en : std_logic; -- is sreg_fl_wr_en(3);
|
461 |
|
|
signal sreg_s_wr_en : std_logic; -- is sreg_fl_wr_en(4);
|
462 |
|
|
signal sreg_h_wr_en : std_logic; -- is sreg_fl_wr_en(5);
|
463 |
|
|
signal sreg_t_wr_en : std_logic; -- is sreg_fl_wr_en(6);
|
464 |
|
|
signal sreg_i_wr_en : std_logic; -- is sreg_fl_wr_en(7);
|
465 |
|
|
|
466 |
|
|
signal sreg_bop_wr_en : std_logic_vector (7 downto 0);
|
467 |
|
|
|
468 |
|
|
signal sreg_adr_eq : std_logic;
|
469 |
|
|
-- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
|
470 |
|
|
|
471 |
|
|
signal inst_cml_3 : std_logic_vector ( 15 downto 0 );
|
472 |
|
|
signal inst_cml_2 : std_logic_vector ( 15 downto 0 );
|
473 |
|
|
signal inst_cml_1 : std_logic_vector ( 15 downto 0 );
|
474 |
|
|
signal sp_ndown_up_cml_out : std_logic;
|
475 |
|
|
signal sp_en_cml_out : std_logic;
|
476 |
|
|
signal cpuwait_cml_3 : std_logic;
|
477 |
|
|
signal cpuwait_cml_2 : std_logic;
|
478 |
|
|
signal cpuwait_cml_1 : std_logic;
|
479 |
|
|
signal reg_rd_in_cml_out : std_logic_vector ( 7 downto 0 );
|
480 |
|
|
signal dbusin_cml_3 : std_logic_vector ( 7 downto 0 );
|
481 |
|
|
signal irqlines_cml_3 : std_logic_vector ( 22 downto 0 );
|
482 |
|
|
signal irqlines_cml_2 : std_logic_vector ( 22 downto 0 );
|
483 |
|
|
signal irqlines_cml_1 : std_logic_vector ( 22 downto 0 );
|
484 |
|
|
signal reg_rd_out_cml_3 : std_logic_vector ( 7 downto 0 );
|
485 |
|
|
signal reg_rd_out_cml_2 : std_logic_vector ( 7 downto 0 );
|
486 |
|
|
signal alu_data_r_in_cml_out : std_logic_vector ( 7 downto 0 );
|
487 |
|
|
signal reg_rr_out_cml_3 : std_logic_vector ( 7 downto 0 );
|
488 |
|
|
signal reg_rr_out_cml_2 : std_logic_vector ( 7 downto 0 );
|
489 |
|
|
signal reg_rr_out_cml_1 : std_logic_vector ( 7 downto 0 );
|
490 |
|
|
signal rampz_out_cml_3 : std_logic_vector ( 7 downto 0 );
|
491 |
|
|
signal bitpr_io_out_cml_3 : std_logic_vector ( 7 downto 0 );
|
492 |
|
|
signal bitpr_io_out_cml_2 : std_logic_vector ( 7 downto 0 );
|
493 |
|
|
signal bitpr_io_out_cml_1 : std_logic_vector ( 7 downto 0 );
|
494 |
|
|
signal ramadr_reg_in_cml_3 : std_logic_vector ( 15 downto 0 );
|
495 |
|
|
signal ramadr_reg_in_cml_2 : std_logic_vector ( 15 downto 0 );
|
496 |
|
|
signal irqack_cml_out : std_logic;
|
497 |
|
|
signal irqack_int_cml_3 : std_logic;
|
498 |
|
|
signal irqack_int_cml_2 : std_logic;
|
499 |
|
|
signal irqack_int_cml_1 : std_logic;
|
500 |
|
|
signal irqackad_cml_out : std_logic_vector ( 4 downto 0 );
|
501 |
|
|
signal irqackad_int_cml_3 : std_logic_vector ( irqackad 'range);
|
502 |
|
|
signal irqackad_int_cml_2 : std_logic_vector ( irqackad 'range);
|
503 |
|
|
signal irqackad_int_cml_1 : std_logic_vector ( irqackad 'range);
|
504 |
|
|
signal adiw_sbiw_encoder_out_cml_3 : std_logic_vector ( 4 downto 0 );
|
505 |
|
|
signal adiw_sbiw_encoder_out_cml_2 : std_logic_vector ( 4 downto 0 );
|
506 |
|
|
signal adiw_sbiw_encoder_out_cml_1 : std_logic_vector ( 4 downto 0 );
|
507 |
|
|
signal adiw_sbiw_encoder_mux_out_cml_3 : std_logic_vector ( 4 downto 0 );
|
508 |
|
|
signal adiw_sbiw_encoder_mux_out_cml_2 : std_logic_vector ( 4 downto 0 );
|
509 |
|
|
signal adiw_sbiw_encoder_mux_out_cml_1 : std_logic_vector ( 4 downto 0 );
|
510 |
|
|
signal program_counter_tmp_cml_3 : std_logic_vector ( 15 downto 0 );
|
511 |
|
|
signal program_counter_tmp_cml_2 : std_logic_vector ( 15 downto 0 );
|
512 |
|
|
signal program_counter_tmp_cml_1 : std_logic_vector ( 15 downto 0 );
|
513 |
|
|
signal program_counter_cml_3 : std_logic_vector ( 15 downto 0 );
|
514 |
|
|
signal program_counter_cml_2 : std_logic_vector ( 15 downto 0 );
|
515 |
|
|
signal program_counter_cml_1 : std_logic_vector ( 15 downto 0 );
|
516 |
|
|
signal program_counter_high_fr_cml_3 : std_logic_vector ( 7 downto 0 );
|
517 |
|
|
signal program_counter_high_fr_cml_2 : std_logic_vector ( 7 downto 0 );
|
518 |
|
|
signal program_counter_high_fr_cml_1 : std_logic_vector ( 7 downto 0 );
|
519 |
|
|
signal pc_low_cml_3 : std_logic_vector ( 7 downto 0 );
|
520 |
|
|
signal pc_low_cml_2 : std_logic_vector ( 7 downto 0 );
|
521 |
|
|
signal pc_low_cml_1 : std_logic_vector ( 7 downto 0 );
|
522 |
|
|
signal pc_high_cml_3 : std_logic_vector ( 7 downto 0 );
|
523 |
|
|
signal pc_high_cml_2 : std_logic_vector ( 7 downto 0 );
|
524 |
|
|
signal pc_high_cml_1 : std_logic_vector ( 7 downto 0 );
|
525 |
|
|
signal reg_rd_wr_cml_out : std_logic;
|
526 |
|
|
signal reg_file_adr_space_cml_3 : std_logic;
|
527 |
|
|
signal reg_file_adr_space_cml_2 : std_logic;
|
528 |
|
|
signal reg_file_adr_space_cml_1 : std_logic;
|
529 |
|
|
signal io_file_adr_space_cml_3 : std_logic;
|
530 |
|
|
signal io_file_adr_space_cml_2 : std_logic;
|
531 |
|
|
signal io_file_adr_space_cml_1 : std_logic;
|
532 |
|
|
signal nirq_st0_cml_3 : std_logic;
|
533 |
|
|
signal nirq_st0_cml_2 : std_logic;
|
534 |
|
|
signal nirq_st0_cml_1 : std_logic;
|
535 |
|
|
signal irq_st1_cml_3 : std_logic;
|
536 |
|
|
signal irq_st1_cml_2 : std_logic;
|
537 |
|
|
signal irq_st1_cml_1 : std_logic;
|
538 |
|
|
signal irq_st2_cml_3 : std_logic;
|
539 |
|
|
signal irq_st2_cml_2 : std_logic;
|
540 |
|
|
signal irq_st2_cml_1 : std_logic;
|
541 |
|
|
signal irq_st3_cml_3 : std_logic;
|
542 |
|
|
signal irq_st3_cml_2 : std_logic;
|
543 |
|
|
signal irq_st3_cml_1 : std_logic;
|
544 |
|
|
signal ncall_st0_cml_3 : std_logic;
|
545 |
|
|
signal ncall_st0_cml_2 : std_logic;
|
546 |
|
|
signal ncall_st0_cml_1 : std_logic;
|
547 |
|
|
signal call_st1_cml_3 : std_logic;
|
548 |
|
|
signal call_st1_cml_2 : std_logic;
|
549 |
|
|
signal call_st1_cml_1 : std_logic;
|
550 |
|
|
signal call_st2_cml_3 : std_logic;
|
551 |
|
|
signal call_st2_cml_2 : std_logic;
|
552 |
|
|
signal call_st2_cml_1 : std_logic;
|
553 |
|
|
signal call_st3_cml_3 : std_logic;
|
554 |
|
|
signal call_st3_cml_2 : std_logic;
|
555 |
|
|
signal call_st3_cml_1 : std_logic;
|
556 |
|
|
signal nrcall_st0_cml_3 : std_logic;
|
557 |
|
|
signal nrcall_st0_cml_2 : std_logic;
|
558 |
|
|
signal nrcall_st0_cml_1 : std_logic;
|
559 |
|
|
signal rcall_st1_cml_3 : std_logic;
|
560 |
|
|
signal rcall_st1_cml_2 : std_logic;
|
561 |
|
|
signal rcall_st1_cml_1 : std_logic;
|
562 |
|
|
signal rcall_st2_cml_3 : std_logic;
|
563 |
|
|
signal rcall_st2_cml_2 : std_logic;
|
564 |
|
|
signal rcall_st2_cml_1 : std_logic;
|
565 |
|
|
signal nicall_st0_cml_3 : std_logic;
|
566 |
|
|
signal nicall_st0_cml_2 : std_logic;
|
567 |
|
|
signal nicall_st0_cml_1 : std_logic;
|
568 |
|
|
signal icall_st1_cml_3 : std_logic;
|
569 |
|
|
signal icall_st1_cml_2 : std_logic;
|
570 |
|
|
signal icall_st1_cml_1 : std_logic;
|
571 |
|
|
signal icall_st2_cml_3 : std_logic;
|
572 |
|
|
signal icall_st2_cml_2 : std_logic;
|
573 |
|
|
signal icall_st2_cml_1 : std_logic;
|
574 |
|
|
signal njmp_st0_cml_3 : std_logic;
|
575 |
|
|
signal njmp_st0_cml_2 : std_logic;
|
576 |
|
|
signal njmp_st0_cml_1 : std_logic;
|
577 |
|
|
signal jmp_st1_cml_3 : std_logic;
|
578 |
|
|
signal jmp_st1_cml_2 : std_logic;
|
579 |
|
|
signal jmp_st1_cml_1 : std_logic;
|
580 |
|
|
signal jmp_st2_cml_3 : std_logic;
|
581 |
|
|
signal jmp_st2_cml_2 : std_logic;
|
582 |
|
|
signal jmp_st2_cml_1 : std_logic;
|
583 |
|
|
signal ijmp_st_cml_3 : std_logic;
|
584 |
|
|
signal ijmp_st_cml_2 : std_logic;
|
585 |
|
|
signal ijmp_st_cml_1 : std_logic;
|
586 |
|
|
signal rjmp_st_cml_3 : std_logic;
|
587 |
|
|
signal rjmp_st_cml_2 : std_logic;
|
588 |
|
|
signal rjmp_st_cml_1 : std_logic;
|
589 |
|
|
signal nret_st0_cml_3 : std_logic;
|
590 |
|
|
signal nret_st0_cml_2 : std_logic;
|
591 |
|
|
signal nret_st0_cml_1 : std_logic;
|
592 |
|
|
signal ret_st1_cml_3 : std_logic;
|
593 |
|
|
signal ret_st1_cml_2 : std_logic;
|
594 |
|
|
signal ret_st1_cml_1 : std_logic;
|
595 |
|
|
signal ret_st2_cml_3 : std_logic;
|
596 |
|
|
signal ret_st2_cml_2 : std_logic;
|
597 |
|
|
signal ret_st2_cml_1 : std_logic;
|
598 |
|
|
signal ret_st3_cml_3 : std_logic;
|
599 |
|
|
signal ret_st3_cml_2 : std_logic;
|
600 |
|
|
signal ret_st3_cml_1 : std_logic;
|
601 |
|
|
signal nreti_st0_cml_3 : std_logic;
|
602 |
|
|
signal nreti_st0_cml_2 : std_logic;
|
603 |
|
|
signal nreti_st0_cml_1 : std_logic;
|
604 |
|
|
signal reti_st1_cml_3 : std_logic;
|
605 |
|
|
signal reti_st1_cml_2 : std_logic;
|
606 |
|
|
signal reti_st1_cml_1 : std_logic;
|
607 |
|
|
signal reti_st2_cml_3 : std_logic;
|
608 |
|
|
signal reti_st2_cml_2 : std_logic;
|
609 |
|
|
signal reti_st2_cml_1 : std_logic;
|
610 |
|
|
signal sreg_fl_in_cml_out : std_logic_vector ( 7 downto 0 );
|
611 |
|
|
signal reti_st3_cml_3 : std_logic;
|
612 |
|
|
signal reti_st3_cml_2 : std_logic;
|
613 |
|
|
signal reti_st3_cml_1 : std_logic;
|
614 |
|
|
signal brxx_st_cml_3 : std_logic;
|
615 |
|
|
signal brxx_st_cml_2 : std_logic;
|
616 |
|
|
signal brxx_st_cml_1 : std_logic;
|
617 |
|
|
signal adiw_st_cml_3 : std_logic;
|
618 |
|
|
signal adiw_st_cml_2 : std_logic;
|
619 |
|
|
signal adiw_st_cml_1 : std_logic;
|
620 |
|
|
signal sbiw_st_cml_3 : std_logic;
|
621 |
|
|
signal sbiw_st_cml_2 : std_logic;
|
622 |
|
|
signal sbiw_st_cml_1 : std_logic;
|
623 |
|
|
signal nskip_inst_st0_cml_3 : std_logic;
|
624 |
|
|
signal nskip_inst_st0_cml_2 : std_logic;
|
625 |
|
|
signal nskip_inst_st0_cml_1 : std_logic;
|
626 |
|
|
signal skip_inst_st1_cml_3 : std_logic;
|
627 |
|
|
signal skip_inst_st1_cml_2 : std_logic;
|
628 |
|
|
signal skip_inst_st1_cml_1 : std_logic;
|
629 |
|
|
signal skip_inst_st2_cml_3 : std_logic;
|
630 |
|
|
signal skip_inst_st2_cml_2 : std_logic;
|
631 |
|
|
signal skip_inst_st2_cml_1 : std_logic;
|
632 |
|
|
signal nlpm_st0_cml_3 : std_logic;
|
633 |
|
|
signal nlpm_st0_cml_2 : std_logic;
|
634 |
|
|
signal nlpm_st0_cml_1 : std_logic;
|
635 |
|
|
signal lpm_st1_cml_3 : std_logic;
|
636 |
|
|
signal lpm_st1_cml_2 : std_logic;
|
637 |
|
|
signal lpm_st1_cml_1 : std_logic;
|
638 |
|
|
signal lpm_st2_cml_3 : std_logic;
|
639 |
|
|
signal lpm_st2_cml_2 : std_logic;
|
640 |
|
|
signal lpm_st2_cml_1 : std_logic;
|
641 |
|
|
signal sts_st_cml_3 : std_logic;
|
642 |
|
|
signal sts_st_cml_2 : std_logic;
|
643 |
|
|
signal sts_st_cml_1 : std_logic;
|
644 |
|
|
signal lds_st_cml_3 : std_logic;
|
645 |
|
|
signal lds_st_cml_2 : std_logic;
|
646 |
|
|
signal lds_st_cml_1 : std_logic;
|
647 |
|
|
signal st_st_cml_3 : std_logic;
|
648 |
|
|
signal st_st_cml_2 : std_logic;
|
649 |
|
|
signal st_st_cml_1 : std_logic;
|
650 |
|
|
signal ld_st_cml_3 : std_logic;
|
651 |
|
|
signal ld_st_cml_2 : std_logic;
|
652 |
|
|
signal ld_st_cml_1 : std_logic;
|
653 |
|
|
signal sbi_st_cml_3 : std_logic;
|
654 |
|
|
signal sbi_st_cml_2 : std_logic;
|
655 |
|
|
signal sbi_st_cml_1 : std_logic;
|
656 |
|
|
signal cbi_st_cml_3 : std_logic;
|
657 |
|
|
signal cbi_st_cml_2 : std_logic;
|
658 |
|
|
signal cbi_st_cml_1 : std_logic;
|
659 |
|
|
signal push_st_cml_3 : std_logic;
|
660 |
|
|
signal push_st_cml_2 : std_logic;
|
661 |
|
|
signal push_st_cml_1 : std_logic;
|
662 |
|
|
signal pop_st_cml_3 : std_logic;
|
663 |
|
|
signal pop_st_cml_2 : std_logic;
|
664 |
|
|
signal pop_st_cml_1 : std_logic;
|
665 |
|
|
signal adr_cml_out : std_logic_vector ( 5 downto 0 );
|
666 |
|
|
signal adr_int_cml_3 : std_logic_vector ( 5 downto 0 );
|
667 |
|
|
signal adr_int_cml_2 : std_logic_vector ( 5 downto 0 );
|
668 |
|
|
signal iore_cml_out : std_logic;
|
669 |
|
|
signal iore_int_cml_2 : std_logic;
|
670 |
|
|
signal ramadr_int_cml_3 : std_logic_vector ( 15 downto 0 );
|
671 |
|
|
signal ramadr_int_cml_2 : std_logic_vector ( 15 downto 0 );
|
672 |
|
|
signal ramadr_int_cml_1 : std_logic_vector ( 15 downto 0 );
|
673 |
|
|
signal ramre_int_cml_3 : std_logic;
|
674 |
|
|
signal ramre_int_cml_2 : std_logic;
|
675 |
|
|
signal ramre_int_cml_1 : std_logic;
|
676 |
|
|
signal ramwe_int_cml_3 : std_logic;
|
677 |
|
|
signal ramwe_int_cml_2 : std_logic;
|
678 |
|
|
signal ramwe_int_cml_1 : std_logic;
|
679 |
|
|
signal instruction_reg_cml_3 : std_logic_vector ( 15 downto 0 );
|
680 |
|
|
signal instruction_reg_cml_2 : std_logic_vector ( 15 downto 0 );
|
681 |
|
|
signal instruction_reg_cml_1 : std_logic_vector ( 15 downto 0 );
|
682 |
|
|
signal instruction_code_reg_cml_3 : std_logic_vector ( 15 downto 0 );
|
683 |
|
|
signal instruction_code_reg_cml_2 : std_logic_vector ( 15 downto 0 );
|
684 |
|
|
signal instruction_code_reg_cml_1 : std_logic_vector ( 15 downto 0 );
|
685 |
|
|
signal irq_vector_adr_cml_3 : std_logic_vector ( 15 downto 0 );
|
686 |
|
|
signal irq_vector_adr_cml_2 : std_logic_vector ( 15 downto 0 );
|
687 |
|
|
signal irq_vector_adr_cml_1 : std_logic_vector ( 15 downto 0 );
|
688 |
|
|
signal pc_for_interrupt_cml_3 : std_logic_vector ( 15 downto 0 );
|
689 |
|
|
signal pc_for_interrupt_cml_2 : std_logic_vector ( 15 downto 0 );
|
690 |
|
|
signal pc_for_interrupt_cml_1 : std_logic_vector ( 15 downto 0 );
|
691 |
|
|
signal dex_dat8_immed_cml_3 : std_logic_vector ( 7 downto 0 );
|
692 |
|
|
signal dex_dat8_immed_cml_2 : std_logic_vector ( 7 downto 0 );
|
693 |
|
|
signal dex_dat8_immed_cml_1 : std_logic_vector ( 7 downto 0 );
|
694 |
|
|
signal dex_dat6_immed_cml_1 : std_logic_vector ( 5 downto 0 );
|
695 |
|
|
signal dex_adr5port_cml_3 : std_logic_vector ( 4 downto 0 );
|
696 |
|
|
signal dex_adr5port_cml_2 : std_logic_vector ( 4 downto 0 );
|
697 |
|
|
signal dex_adrreg_d_cml_3 : std_logic_vector ( 4 downto 0 );
|
698 |
|
|
signal dex_adrreg_d_cml_2 : std_logic_vector ( 4 downto 0 );
|
699 |
|
|
signal dex_adrreg_d_cml_1 : std_logic_vector ( 4 downto 0 );
|
700 |
|
|
signal dex_bitop_bitnum_cml_3 : std_logic_vector ( 2 downto 0 );
|
701 |
|
|
signal dex_bitop_bitnum_cml_2 : std_logic_vector ( 2 downto 0 );
|
702 |
|
|
signal dex_bitop_bitnum_cml_1 : std_logic_vector ( 2 downto 0 );
|
703 |
|
|
signal dex_adrreg_d_latched_cml_3 : std_logic_vector ( 4 downto 0 );
|
704 |
|
|
signal dex_adrreg_d_latched_cml_2 : std_logic_vector ( 4 downto 0 );
|
705 |
|
|
signal dex_adrreg_d_latched_cml_1 : std_logic_vector ( 4 downto 0 );
|
706 |
|
|
signal gp_reg_tmp_cml_3 : std_logic_vector ( 7 downto 0 );
|
707 |
|
|
signal gp_reg_tmp_cml_2 : std_logic_vector ( 7 downto 0 );
|
708 |
|
|
signal gp_reg_tmp_cml_1 : std_logic_vector ( 7 downto 0 );
|
709 |
|
|
signal cbi_sbi_io_adr_tmp_cml_3 : std_logic_vector ( 4 downto 0 );
|
710 |
|
|
signal cbi_sbi_io_adr_tmp_cml_2 : std_logic_vector ( 4 downto 0 );
|
711 |
|
|
signal cbi_sbi_io_adr_tmp_cml_1 : std_logic_vector ( 4 downto 0 );
|
712 |
|
|
signal cbi_sbi_bit_num_tmp_cml_3 : std_logic_vector ( 2 downto 0 );
|
713 |
|
|
signal cbi_sbi_bit_num_tmp_cml_2 : std_logic_vector ( 2 downto 0 );
|
714 |
|
|
signal cbi_sbi_bit_num_tmp_cml_1 : std_logic_vector ( 2 downto 0 );
|
715 |
|
|
signal idc_adc_cml_3 : std_logic;
|
716 |
|
|
signal idc_adc_cml_2 : std_logic;
|
717 |
|
|
signal idc_adc_cml_1 : std_logic;
|
718 |
|
|
signal idc_add_cml_3 : std_logic;
|
719 |
|
|
signal idc_adiw_out_cml_out : std_logic;
|
720 |
|
|
signal idc_adiw_cml_3 : std_logic;
|
721 |
|
|
signal idc_adiw_cml_2 : std_logic;
|
722 |
|
|
signal idc_adiw_cml_1 : std_logic;
|
723 |
|
|
signal idc_and_cml_3 : std_logic;
|
724 |
|
|
signal idc_andi_out_cml_out : std_logic;
|
725 |
|
|
signal idc_andi_cml_3 : std_logic;
|
726 |
|
|
signal idc_andi_cml_2 : std_logic;
|
727 |
|
|
signal idc_andi_cml_1 : std_logic;
|
728 |
|
|
signal idc_asr_cml_3 : std_logic;
|
729 |
|
|
signal idc_cbi_cml_3 : std_logic;
|
730 |
|
|
signal idc_cbi_cml_2 : std_logic;
|
731 |
|
|
signal idc_com_cml_3 : std_logic;
|
732 |
|
|
signal idc_cp_cml_3 : std_logic;
|
733 |
|
|
signal idc_cp_cml_2 : std_logic;
|
734 |
|
|
signal idc_cp_cml_1 : std_logic;
|
735 |
|
|
signal idc_cpc_cml_3 : std_logic;
|
736 |
|
|
signal idc_cpc_cml_2 : std_logic;
|
737 |
|
|
signal idc_cpc_cml_1 : std_logic;
|
738 |
|
|
signal idc_cpi_cml_3 : std_logic;
|
739 |
|
|
signal idc_cpi_cml_2 : std_logic;
|
740 |
|
|
signal idc_cpi_cml_1 : std_logic;
|
741 |
|
|
signal idc_cpse_cml_3 : std_logic;
|
742 |
|
|
signal idc_cpse_cml_2 : std_logic;
|
743 |
|
|
signal idc_cpse_cml_1 : std_logic;
|
744 |
|
|
signal idc_dec_cml_3 : std_logic;
|
745 |
|
|
signal idc_dec_cml_2 : std_logic;
|
746 |
|
|
signal idc_eor_cml_3 : std_logic;
|
747 |
|
|
signal idc_icall_cml_3 : std_logic;
|
748 |
|
|
signal idc_icall_cml_2 : std_logic;
|
749 |
|
|
signal idc_icall_cml_1 : std_logic;
|
750 |
|
|
signal idc_in_cml_3 : std_logic;
|
751 |
|
|
signal idc_in_cml_2 : std_logic;
|
752 |
|
|
signal idc_inc_cml_3 : std_logic;
|
753 |
|
|
signal reg_h_wr_cml_out : std_logic;
|
754 |
|
|
signal idc_ld_x_cml_3 : std_logic;
|
755 |
|
|
signal idc_ld_x_cml_2 : std_logic;
|
756 |
|
|
signal idc_ld_x_cml_1 : std_logic;
|
757 |
|
|
signal idc_ld_y_cml_3 : std_logic;
|
758 |
|
|
signal idc_ld_y_cml_2 : std_logic;
|
759 |
|
|
signal idc_ld_y_cml_1 : std_logic;
|
760 |
|
|
signal idc_ldd_y_cml_3 : std_logic;
|
761 |
|
|
signal idc_ldd_y_cml_2 : std_logic;
|
762 |
|
|
signal idc_ldd_y_cml_1 : std_logic;
|
763 |
|
|
signal idc_ld_z_cml_3 : std_logic;
|
764 |
|
|
signal idc_ld_z_cml_2 : std_logic;
|
765 |
|
|
signal idc_ld_z_cml_1 : std_logic;
|
766 |
|
|
signal idc_ldd_z_cml_3 : std_logic;
|
767 |
|
|
signal idc_ldd_z_cml_2 : std_logic;
|
768 |
|
|
signal idc_ldd_z_cml_1 : std_logic;
|
769 |
|
|
signal idc_ldi_cml_3 : std_logic;
|
770 |
|
|
signal idc_ldi_cml_2 : std_logic;
|
771 |
|
|
signal idc_ldi_cml_1 : std_logic;
|
772 |
|
|
signal idc_lds_cml_3 : std_logic;
|
773 |
|
|
signal idc_lds_cml_2 : std_logic;
|
774 |
|
|
signal idc_lds_cml_1 : std_logic;
|
775 |
|
|
signal idc_lsr_cml_3 : std_logic;
|
776 |
|
|
signal idc_neg_cml_3 : std_logic;
|
777 |
|
|
signal idc_or_cml_3 : std_logic;
|
778 |
|
|
signal idc_ori_out_cml_out : std_logic;
|
779 |
|
|
signal idc_ori_cml_3 : std_logic;
|
780 |
|
|
signal idc_ori_cml_2 : std_logic;
|
781 |
|
|
signal idc_ori_cml_1 : std_logic;
|
782 |
|
|
signal idc_out_cml_3 : std_logic;
|
783 |
|
|
signal idc_out_cml_2 : std_logic;
|
784 |
|
|
signal idc_out_cml_1 : std_logic;
|
785 |
|
|
signal idc_pop_cml_3 : std_logic;
|
786 |
|
|
signal idc_pop_cml_2 : std_logic;
|
787 |
|
|
signal idc_pop_cml_1 : std_logic;
|
788 |
|
|
signal idc_push_cml_3 : std_logic;
|
789 |
|
|
signal idc_push_cml_2 : std_logic;
|
790 |
|
|
signal idc_push_cml_1 : std_logic;
|
791 |
|
|
signal idc_rcall_cml_3 : std_logic;
|
792 |
|
|
signal idc_rcall_cml_2 : std_logic;
|
793 |
|
|
signal idc_rcall_cml_1 : std_logic;
|
794 |
|
|
signal idc_ret_cml_3 : std_logic;
|
795 |
|
|
signal idc_ret_cml_2 : std_logic;
|
796 |
|
|
signal idc_ret_cml_1 : std_logic;
|
797 |
|
|
signal idc_reti_out_cml_out : std_logic;
|
798 |
|
|
signal idc_reti_cml_3 : std_logic;
|
799 |
|
|
signal idc_reti_cml_2 : std_logic;
|
800 |
|
|
signal idc_reti_cml_1 : std_logic;
|
801 |
|
|
signal idc_ror_cml_3 : std_logic;
|
802 |
|
|
signal idc_ror_cml_2 : std_logic;
|
803 |
|
|
signal idc_ror_cml_1 : std_logic;
|
804 |
|
|
signal idc_sbc_cml_3 : std_logic;
|
805 |
|
|
signal idc_sbc_cml_2 : std_logic;
|
806 |
|
|
signal idc_sbc_cml_1 : std_logic;
|
807 |
|
|
signal idc_sbci_cml_3 : std_logic;
|
808 |
|
|
signal idc_sbci_cml_2 : std_logic;
|
809 |
|
|
signal idc_sbci_cml_1 : std_logic;
|
810 |
|
|
signal idc_sbi_cml_3 : std_logic;
|
811 |
|
|
signal idc_sbi_cml_2 : std_logic;
|
812 |
|
|
signal idc_sbic_out_cml_out : std_logic;
|
813 |
|
|
signal idc_sbic_cml_3 : std_logic;
|
814 |
|
|
signal idc_sbic_cml_2 : std_logic;
|
815 |
|
|
signal idc_sbis_out_cml_out : std_logic;
|
816 |
|
|
signal idc_sbis_cml_3 : std_logic;
|
817 |
|
|
signal idc_sbis_cml_2 : std_logic;
|
818 |
|
|
signal idc_sbiw_cml_3 : std_logic;
|
819 |
|
|
signal idc_sbiw_cml_2 : std_logic;
|
820 |
|
|
signal idc_sbiw_cml_1 : std_logic;
|
821 |
|
|
signal idc_sbrc_out_cml_out : std_logic;
|
822 |
|
|
signal idc_sbrc_cml_3 : std_logic;
|
823 |
|
|
signal idc_sbrs_out_cml_out : std_logic;
|
824 |
|
|
signal idc_sbrs_cml_3 : std_logic;
|
825 |
|
|
signal idc_st_x_cml_3 : std_logic;
|
826 |
|
|
signal idc_st_x_cml_2 : std_logic;
|
827 |
|
|
signal idc_st_x_cml_1 : std_logic;
|
828 |
|
|
signal idc_st_y_cml_3 : std_logic;
|
829 |
|
|
signal idc_st_y_cml_2 : std_logic;
|
830 |
|
|
signal idc_st_y_cml_1 : std_logic;
|
831 |
|
|
signal idc_std_y_cml_3 : std_logic;
|
832 |
|
|
signal idc_std_y_cml_2 : std_logic;
|
833 |
|
|
signal idc_std_y_cml_1 : std_logic;
|
834 |
|
|
signal idc_st_z_cml_3 : std_logic;
|
835 |
|
|
signal idc_st_z_cml_2 : std_logic;
|
836 |
|
|
signal idc_st_z_cml_1 : std_logic;
|
837 |
|
|
signal idc_std_z_cml_3 : std_logic;
|
838 |
|
|
signal idc_std_z_cml_2 : std_logic;
|
839 |
|
|
signal idc_std_z_cml_1 : std_logic;
|
840 |
|
|
signal idc_sts_cml_3 : std_logic;
|
841 |
|
|
signal idc_sts_cml_2 : std_logic;
|
842 |
|
|
signal idc_sts_cml_1 : std_logic;
|
843 |
|
|
signal idc_sub_cml_3 : std_logic;
|
844 |
|
|
signal idc_sub_cml_2 : std_logic;
|
845 |
|
|
signal idc_sub_cml_1 : std_logic;
|
846 |
|
|
signal idc_subi_cml_3 : std_logic;
|
847 |
|
|
signal idc_subi_cml_2 : std_logic;
|
848 |
|
|
signal idc_subi_cml_1 : std_logic;
|
849 |
|
|
signal idc_swap_cml_3 : std_logic;
|
850 |
|
|
signal pre_dec_cml_out : std_logic;
|
851 |
|
|
signal idc_prdec_cml_3 : std_logic;
|
852 |
|
|
signal idc_prdec_cml_2 : std_logic;
|
853 |
|
|
signal idc_prdec_cml_1 : std_logic;
|
854 |
|
|
|
855 |
|
|
begin
|
856 |
|
|
|
857 |
|
|
|
858 |
|
|
|
859 |
|
|
process(cp2_cml_1) begin
|
860 |
|
|
if (cp2_cml_1 = '1' and cp2_cml_1'event) then
|
861 |
|
|
inst_cml_1 <= inst;
|
862 |
|
|
cpuwait_cml_1 <= cpuwait;
|
863 |
|
|
irqlines_cml_1 <= irqlines;
|
864 |
|
|
reg_rr_out_cml_1 <= reg_rr_out;
|
865 |
|
|
bitpr_io_out_cml_1 <= bitpr_io_out;
|
866 |
|
|
irqack_int_cml_1 <= irqack_int;
|
867 |
|
|
irqackad_int_cml_1 <= irqackad_int;
|
868 |
|
|
adiw_sbiw_encoder_out_cml_1 <= adiw_sbiw_encoder_out;
|
869 |
|
|
adiw_sbiw_encoder_mux_out_cml_1 <= adiw_sbiw_encoder_mux_out;
|
870 |
|
|
program_counter_tmp_cml_1 <= program_counter_tmp;
|
871 |
|
|
program_counter_cml_1 <= program_counter;
|
872 |
|
|
program_counter_high_fr_cml_1 <= program_counter_high_fr;
|
873 |
|
|
pc_low_cml_1 <= pc_low;
|
874 |
|
|
pc_high_cml_1 <= pc_high;
|
875 |
|
|
reg_file_adr_space_cml_1 <= reg_file_adr_space;
|
876 |
|
|
io_file_adr_space_cml_1 <= io_file_adr_space;
|
877 |
|
|
nirq_st0_cml_1 <= nirq_st0;
|
878 |
|
|
irq_st1_cml_1 <= irq_st1;
|
879 |
|
|
irq_st2_cml_1 <= irq_st2;
|
880 |
|
|
irq_st3_cml_1 <= irq_st3;
|
881 |
|
|
ncall_st0_cml_1 <= ncall_st0;
|
882 |
|
|
call_st1_cml_1 <= call_st1;
|
883 |
|
|
call_st2_cml_1 <= call_st2;
|
884 |
|
|
call_st3_cml_1 <= call_st3;
|
885 |
|
|
nrcall_st0_cml_1 <= nrcall_st0;
|
886 |
|
|
rcall_st1_cml_1 <= rcall_st1;
|
887 |
|
|
rcall_st2_cml_1 <= rcall_st2;
|
888 |
|
|
nicall_st0_cml_1 <= nicall_st0;
|
889 |
|
|
icall_st1_cml_1 <= icall_st1;
|
890 |
|
|
icall_st2_cml_1 <= icall_st2;
|
891 |
|
|
njmp_st0_cml_1 <= njmp_st0;
|
892 |
|
|
jmp_st1_cml_1 <= jmp_st1;
|
893 |
|
|
jmp_st2_cml_1 <= jmp_st2;
|
894 |
|
|
ijmp_st_cml_1 <= ijmp_st;
|
895 |
|
|
rjmp_st_cml_1 <= rjmp_st;
|
896 |
|
|
nret_st0_cml_1 <= nret_st0;
|
897 |
|
|
ret_st1_cml_1 <= ret_st1;
|
898 |
|
|
ret_st2_cml_1 <= ret_st2;
|
899 |
|
|
ret_st3_cml_1 <= ret_st3;
|
900 |
|
|
nreti_st0_cml_1 <= nreti_st0;
|
901 |
|
|
reti_st1_cml_1 <= reti_st1;
|
902 |
|
|
reti_st2_cml_1 <= reti_st2;
|
903 |
|
|
reti_st3_cml_1 <= reti_st3;
|
904 |
|
|
brxx_st_cml_1 <= brxx_st;
|
905 |
|
|
adiw_st_cml_1 <= adiw_st;
|
906 |
|
|
sbiw_st_cml_1 <= sbiw_st;
|
907 |
|
|
nskip_inst_st0_cml_1 <= nskip_inst_st0;
|
908 |
|
|
skip_inst_st1_cml_1 <= skip_inst_st1;
|
909 |
|
|
skip_inst_st2_cml_1 <= skip_inst_st2;
|
910 |
|
|
nlpm_st0_cml_1 <= nlpm_st0;
|
911 |
|
|
lpm_st1_cml_1 <= lpm_st1;
|
912 |
|
|
lpm_st2_cml_1 <= lpm_st2;
|
913 |
|
|
sts_st_cml_1 <= sts_st;
|
914 |
|
|
lds_st_cml_1 <= lds_st;
|
915 |
|
|
st_st_cml_1 <= st_st;
|
916 |
|
|
ld_st_cml_1 <= ld_st;
|
917 |
|
|
sbi_st_cml_1 <= sbi_st;
|
918 |
|
|
cbi_st_cml_1 <= cbi_st;
|
919 |
|
|
push_st_cml_1 <= push_st;
|
920 |
|
|
pop_st_cml_1 <= pop_st;
|
921 |
|
|
ramadr_int_cml_1 <= ramadr_int;
|
922 |
|
|
ramre_int_cml_1 <= ramre_int;
|
923 |
|
|
ramwe_int_cml_1 <= ramwe_int;
|
924 |
|
|
instruction_reg_cml_1 <= instruction_reg;
|
925 |
|
|
instruction_code_reg_cml_1 <= instruction_code_reg;
|
926 |
|
|
irq_vector_adr_cml_1 <= irq_vector_adr;
|
927 |
|
|
pc_for_interrupt_cml_1 <= pc_for_interrupt;
|
928 |
|
|
dex_dat8_immed_cml_1 <= dex_dat8_immed;
|
929 |
|
|
dex_dat6_immed_cml_1 <= dex_dat6_immed;
|
930 |
|
|
dex_adrreg_d_cml_1 <= dex_adrreg_d;
|
931 |
|
|
dex_bitop_bitnum_cml_1 <= dex_bitop_bitnum;
|
932 |
|
|
dex_adrreg_d_latched_cml_1 <= dex_adrreg_d_latched;
|
933 |
|
|
gp_reg_tmp_cml_1 <= gp_reg_tmp;
|
934 |
|
|
cbi_sbi_io_adr_tmp_cml_1 <= cbi_sbi_io_adr_tmp;
|
935 |
|
|
cbi_sbi_bit_num_tmp_cml_1 <= cbi_sbi_bit_num_tmp;
|
936 |
|
|
idc_adc_cml_1 <= idc_adc;
|
937 |
|
|
idc_adiw_cml_1 <= idc_adiw;
|
938 |
|
|
idc_andi_cml_1 <= idc_andi;
|
939 |
|
|
idc_cp_cml_1 <= idc_cp;
|
940 |
|
|
idc_cpc_cml_1 <= idc_cpc;
|
941 |
|
|
idc_cpi_cml_1 <= idc_cpi;
|
942 |
|
|
idc_cpse_cml_1 <= idc_cpse;
|
943 |
|
|
idc_icall_cml_1 <= idc_icall;
|
944 |
|
|
idc_ld_x_cml_1 <= idc_ld_x;
|
945 |
|
|
idc_ld_y_cml_1 <= idc_ld_y;
|
946 |
|
|
idc_ldd_y_cml_1 <= idc_ldd_y;
|
947 |
|
|
idc_ld_z_cml_1 <= idc_ld_z;
|
948 |
|
|
idc_ldd_z_cml_1 <= idc_ldd_z;
|
949 |
|
|
idc_ldi_cml_1 <= idc_ldi;
|
950 |
|
|
idc_lds_cml_1 <= idc_lds;
|
951 |
|
|
idc_ori_cml_1 <= idc_ori;
|
952 |
|
|
idc_out_cml_1 <= idc_out;
|
953 |
|
|
idc_pop_cml_1 <= idc_pop;
|
954 |
|
|
idc_push_cml_1 <= idc_push;
|
955 |
|
|
idc_rcall_cml_1 <= idc_rcall;
|
956 |
|
|
idc_ret_cml_1 <= idc_ret;
|
957 |
|
|
idc_reti_cml_1 <= idc_reti;
|
958 |
|
|
idc_ror_cml_1 <= idc_ror;
|
959 |
|
|
idc_sbc_cml_1 <= idc_sbc;
|
960 |
|
|
idc_sbci_cml_1 <= idc_sbci;
|
961 |
|
|
idc_sbiw_cml_1 <= idc_sbiw;
|
962 |
|
|
idc_st_x_cml_1 <= idc_st_x;
|
963 |
|
|
idc_st_y_cml_1 <= idc_st_y;
|
964 |
|
|
idc_std_y_cml_1 <= idc_std_y;
|
965 |
|
|
idc_st_z_cml_1 <= idc_st_z;
|
966 |
|
|
idc_std_z_cml_1 <= idc_std_z;
|
967 |
|
|
idc_sts_cml_1 <= idc_sts;
|
968 |
|
|
idc_sub_cml_1 <= idc_sub;
|
969 |
|
|
idc_subi_cml_1 <= idc_subi;
|
970 |
|
|
idc_prdec_cml_1 <= idc_prdec;
|
971 |
|
|
end if;
|
972 |
|
|
end process;
|
973 |
|
|
|
974 |
|
|
process(cp2_cml_2) begin
|
975 |
|
|
if (cp2_cml_2 = '1' and cp2_cml_2'event) then
|
976 |
|
|
inst_cml_2 <= inst_cml_1;
|
977 |
|
|
cpuwait_cml_2 <= cpuwait_cml_1;
|
978 |
|
|
irqlines_cml_2 <= irqlines_cml_1;
|
979 |
|
|
reg_rd_out_cml_2 <= reg_rd_out;
|
980 |
|
|
reg_rr_out_cml_2 <= reg_rr_out_cml_1;
|
981 |
|
|
bitpr_io_out_cml_2 <= bitpr_io_out_cml_1;
|
982 |
|
|
ramadr_reg_in_cml_2 <= ramadr_reg_in;
|
983 |
|
|
irqack_int_cml_2 <= irqack_int_cml_1;
|
984 |
|
|
irqackad_int_cml_2 <= irqackad_int_cml_1;
|
985 |
|
|
adiw_sbiw_encoder_out_cml_2 <= adiw_sbiw_encoder_out_cml_1;
|
986 |
|
|
adiw_sbiw_encoder_mux_out_cml_2 <= adiw_sbiw_encoder_mux_out_cml_1;
|
987 |
|
|
program_counter_tmp_cml_2 <= program_counter_tmp_cml_1;
|
988 |
|
|
program_counter_cml_2 <= program_counter_cml_1;
|
989 |
|
|
program_counter_high_fr_cml_2 <= program_counter_high_fr_cml_1;
|
990 |
|
|
pc_low_cml_2 <= pc_low_cml_1;
|
991 |
|
|
pc_high_cml_2 <= pc_high_cml_1;
|
992 |
|
|
reg_file_adr_space_cml_2 <= reg_file_adr_space_cml_1;
|
993 |
|
|
io_file_adr_space_cml_2 <= io_file_adr_space_cml_1;
|
994 |
|
|
nirq_st0_cml_2 <= nirq_st0_cml_1;
|
995 |
|
|
irq_st1_cml_2 <= irq_st1_cml_1;
|
996 |
|
|
irq_st2_cml_2 <= irq_st2_cml_1;
|
997 |
|
|
irq_st3_cml_2 <= irq_st3_cml_1;
|
998 |
|
|
ncall_st0_cml_2 <= ncall_st0_cml_1;
|
999 |
|
|
call_st1_cml_2 <= call_st1_cml_1;
|
1000 |
|
|
call_st2_cml_2 <= call_st2_cml_1;
|
1001 |
|
|
call_st3_cml_2 <= call_st3_cml_1;
|
1002 |
|
|
nrcall_st0_cml_2 <= nrcall_st0_cml_1;
|
1003 |
|
|
rcall_st1_cml_2 <= rcall_st1_cml_1;
|
1004 |
|
|
rcall_st2_cml_2 <= rcall_st2_cml_1;
|
1005 |
|
|
nicall_st0_cml_2 <= nicall_st0_cml_1;
|
1006 |
|
|
icall_st1_cml_2 <= icall_st1_cml_1;
|
1007 |
|
|
icall_st2_cml_2 <= icall_st2_cml_1;
|
1008 |
|
|
njmp_st0_cml_2 <= njmp_st0_cml_1;
|
1009 |
|
|
jmp_st1_cml_2 <= jmp_st1_cml_1;
|
1010 |
|
|
jmp_st2_cml_2 <= jmp_st2_cml_1;
|
1011 |
|
|
ijmp_st_cml_2 <= ijmp_st_cml_1;
|
1012 |
|
|
rjmp_st_cml_2 <= rjmp_st_cml_1;
|
1013 |
|
|
nret_st0_cml_2 <= nret_st0_cml_1;
|
1014 |
|
|
ret_st1_cml_2 <= ret_st1_cml_1;
|
1015 |
|
|
ret_st2_cml_2 <= ret_st2_cml_1;
|
1016 |
|
|
ret_st3_cml_2 <= ret_st3_cml_1;
|
1017 |
|
|
nreti_st0_cml_2 <= nreti_st0_cml_1;
|
1018 |
|
|
reti_st1_cml_2 <= reti_st1_cml_1;
|
1019 |
|
|
reti_st2_cml_2 <= reti_st2_cml_1;
|
1020 |
|
|
reti_st3_cml_2 <= reti_st3_cml_1;
|
1021 |
|
|
brxx_st_cml_2 <= brxx_st_cml_1;
|
1022 |
|
|
adiw_st_cml_2 <= adiw_st_cml_1;
|
1023 |
|
|
sbiw_st_cml_2 <= sbiw_st_cml_1;
|
1024 |
|
|
nskip_inst_st0_cml_2 <= nskip_inst_st0_cml_1;
|
1025 |
|
|
skip_inst_st1_cml_2 <= skip_inst_st1_cml_1;
|
1026 |
|
|
skip_inst_st2_cml_2 <= skip_inst_st2_cml_1;
|
1027 |
|
|
nlpm_st0_cml_2 <= nlpm_st0_cml_1;
|
1028 |
|
|
lpm_st1_cml_2 <= lpm_st1_cml_1;
|
1029 |
|
|
lpm_st2_cml_2 <= lpm_st2_cml_1;
|
1030 |
|
|
sts_st_cml_2 <= sts_st_cml_1;
|
1031 |
|
|
lds_st_cml_2 <= lds_st_cml_1;
|
1032 |
|
|
st_st_cml_2 <= st_st_cml_1;
|
1033 |
|
|
ld_st_cml_2 <= ld_st_cml_1;
|
1034 |
|
|
sbi_st_cml_2 <= sbi_st_cml_1;
|
1035 |
|
|
cbi_st_cml_2 <= cbi_st_cml_1;
|
1036 |
|
|
push_st_cml_2 <= push_st_cml_1;
|
1037 |
|
|
pop_st_cml_2 <= pop_st_cml_1;
|
1038 |
|
|
adr_int_cml_2 <= adr_int;
|
1039 |
|
|
iore_int_cml_2 <= iore_int;
|
1040 |
|
|
ramadr_int_cml_2 <= ramadr_int_cml_1;
|
1041 |
|
|
ramre_int_cml_2 <= ramre_int_cml_1;
|
1042 |
|
|
ramwe_int_cml_2 <= ramwe_int_cml_1;
|
1043 |
|
|
instruction_reg_cml_2 <= instruction_reg_cml_1;
|
1044 |
|
|
instruction_code_reg_cml_2 <= instruction_code_reg_cml_1;
|
1045 |
|
|
irq_vector_adr_cml_2 <= irq_vector_adr_cml_1;
|
1046 |
|
|
pc_for_interrupt_cml_2 <= pc_for_interrupt_cml_1;
|
1047 |
|
|
dex_dat8_immed_cml_2 <= dex_dat8_immed_cml_1;
|
1048 |
|
|
dex_adr5port_cml_2 <= dex_adr5port;
|
1049 |
|
|
dex_adrreg_d_cml_2 <= dex_adrreg_d_cml_1;
|
1050 |
|
|
dex_bitop_bitnum_cml_2 <= dex_bitop_bitnum_cml_1;
|
1051 |
|
|
dex_adrreg_d_latched_cml_2 <= dex_adrreg_d_latched_cml_1;
|
1052 |
|
|
gp_reg_tmp_cml_2 <= gp_reg_tmp_cml_1;
|
1053 |
|
|
cbi_sbi_io_adr_tmp_cml_2 <= cbi_sbi_io_adr_tmp_cml_1;
|
1054 |
|
|
cbi_sbi_bit_num_tmp_cml_2 <= cbi_sbi_bit_num_tmp_cml_1;
|
1055 |
|
|
idc_adc_cml_2 <= idc_adc_cml_1;
|
1056 |
|
|
idc_adiw_cml_2 <= idc_adiw_cml_1;
|
1057 |
|
|
idc_andi_cml_2 <= idc_andi_cml_1;
|
1058 |
|
|
idc_cbi_cml_2 <= idc_cbi;
|
1059 |
|
|
idc_cp_cml_2 <= idc_cp_cml_1;
|
1060 |
|
|
idc_cpc_cml_2 <= idc_cpc_cml_1;
|
1061 |
|
|
idc_cpi_cml_2 <= idc_cpi_cml_1;
|
1062 |
|
|
idc_cpse_cml_2 <= idc_cpse_cml_1;
|
1063 |
|
|
idc_dec_cml_2 <= idc_dec;
|
1064 |
|
|
idc_icall_cml_2 <= idc_icall_cml_1;
|
1065 |
|
|
idc_in_cml_2 <= idc_in;
|
1066 |
|
|
idc_ld_x_cml_2 <= idc_ld_x_cml_1;
|
1067 |
|
|
idc_ld_y_cml_2 <= idc_ld_y_cml_1;
|
1068 |
|
|
idc_ldd_y_cml_2 <= idc_ldd_y_cml_1;
|
1069 |
|
|
idc_ld_z_cml_2 <= idc_ld_z_cml_1;
|
1070 |
|
|
idc_ldd_z_cml_2 <= idc_ldd_z_cml_1;
|
1071 |
|
|
idc_ldi_cml_2 <= idc_ldi_cml_1;
|
1072 |
|
|
idc_lds_cml_2 <= idc_lds_cml_1;
|
1073 |
|
|
idc_ori_cml_2 <= idc_ori_cml_1;
|
1074 |
|
|
idc_out_cml_2 <= idc_out_cml_1;
|
1075 |
|
|
idc_pop_cml_2 <= idc_pop_cml_1;
|
1076 |
|
|
idc_push_cml_2 <= idc_push_cml_1;
|
1077 |
|
|
idc_rcall_cml_2 <= idc_rcall_cml_1;
|
1078 |
|
|
idc_ret_cml_2 <= idc_ret_cml_1;
|
1079 |
|
|
idc_reti_cml_2 <= idc_reti_cml_1;
|
1080 |
|
|
idc_ror_cml_2 <= idc_ror_cml_1;
|
1081 |
|
|
idc_sbc_cml_2 <= idc_sbc_cml_1;
|
1082 |
|
|
idc_sbci_cml_2 <= idc_sbci_cml_1;
|
1083 |
|
|
idc_sbi_cml_2 <= idc_sbi;
|
1084 |
|
|
idc_sbic_cml_2 <= idc_sbic;
|
1085 |
|
|
idc_sbis_cml_2 <= idc_sbis;
|
1086 |
|
|
idc_sbiw_cml_2 <= idc_sbiw_cml_1;
|
1087 |
|
|
idc_st_x_cml_2 <= idc_st_x_cml_1;
|
1088 |
|
|
idc_st_y_cml_2 <= idc_st_y_cml_1;
|
1089 |
|
|
idc_std_y_cml_2 <= idc_std_y_cml_1;
|
1090 |
|
|
idc_st_z_cml_2 <= idc_st_z_cml_1;
|
1091 |
|
|
idc_std_z_cml_2 <= idc_std_z_cml_1;
|
1092 |
|
|
idc_sts_cml_2 <= idc_sts_cml_1;
|
1093 |
|
|
idc_sub_cml_2 <= idc_sub_cml_1;
|
1094 |
|
|
idc_subi_cml_2 <= idc_subi_cml_1;
|
1095 |
|
|
idc_prdec_cml_2 <= idc_prdec_cml_1;
|
1096 |
|
|
end if;
|
1097 |
|
|
end process;
|
1098 |
|
|
|
1099 |
|
|
process(cp2_cml_3) begin
|
1100 |
|
|
if (cp2_cml_3 = '1' and cp2_cml_3'event) then
|
1101 |
|
|
inst_cml_3 <= inst_cml_2;
|
1102 |
|
|
cpuwait_cml_3 <= cpuwait_cml_2;
|
1103 |
|
|
dbusin_cml_3 <= dbusin;
|
1104 |
|
|
irqlines_cml_3 <= irqlines_cml_2;
|
1105 |
|
|
reg_rd_out_cml_3 <= reg_rd_out_cml_2;
|
1106 |
|
|
reg_rr_out_cml_3 <= reg_rr_out_cml_2;
|
1107 |
|
|
rampz_out_cml_3 <= rampz_out;
|
1108 |
|
|
bitpr_io_out_cml_3 <= bitpr_io_out_cml_2;
|
1109 |
|
|
ramadr_reg_in_cml_3 <= ramadr_reg_in_cml_2;
|
1110 |
|
|
irqack_int_cml_3 <= irqack_int_cml_2;
|
1111 |
|
|
irqackad_int_cml_3 <= irqackad_int_cml_2;
|
1112 |
|
|
adiw_sbiw_encoder_out_cml_3 <= adiw_sbiw_encoder_out_cml_2;
|
1113 |
|
|
adiw_sbiw_encoder_mux_out_cml_3 <= adiw_sbiw_encoder_mux_out_cml_2;
|
1114 |
|
|
program_counter_tmp_cml_3 <= program_counter_tmp_cml_2;
|
1115 |
|
|
program_counter_cml_3 <= program_counter_cml_2;
|
1116 |
|
|
program_counter_high_fr_cml_3 <= program_counter_high_fr_cml_2;
|
1117 |
|
|
pc_low_cml_3 <= pc_low_cml_2;
|
1118 |
|
|
pc_high_cml_3 <= pc_high_cml_2;
|
1119 |
|
|
reg_file_adr_space_cml_3 <= reg_file_adr_space_cml_2;
|
1120 |
|
|
io_file_adr_space_cml_3 <= io_file_adr_space_cml_2;
|
1121 |
|
|
nirq_st0_cml_3 <= nirq_st0_cml_2;
|
1122 |
|
|
irq_st1_cml_3 <= irq_st1_cml_2;
|
1123 |
|
|
irq_st2_cml_3 <= irq_st2_cml_2;
|
1124 |
|
|
irq_st3_cml_3 <= irq_st3_cml_2;
|
1125 |
|
|
ncall_st0_cml_3 <= ncall_st0_cml_2;
|
1126 |
|
|
call_st1_cml_3 <= call_st1_cml_2;
|
1127 |
|
|
call_st2_cml_3 <= call_st2_cml_2;
|
1128 |
|
|
call_st3_cml_3 <= call_st3_cml_2;
|
1129 |
|
|
nrcall_st0_cml_3 <= nrcall_st0_cml_2;
|
1130 |
|
|
rcall_st1_cml_3 <= rcall_st1_cml_2;
|
1131 |
|
|
rcall_st2_cml_3 <= rcall_st2_cml_2;
|
1132 |
|
|
nicall_st0_cml_3 <= nicall_st0_cml_2;
|
1133 |
|
|
icall_st1_cml_3 <= icall_st1_cml_2;
|
1134 |
|
|
icall_st2_cml_3 <= icall_st2_cml_2;
|
1135 |
|
|
njmp_st0_cml_3 <= njmp_st0_cml_2;
|
1136 |
|
|
jmp_st1_cml_3 <= jmp_st1_cml_2;
|
1137 |
|
|
jmp_st2_cml_3 <= jmp_st2_cml_2;
|
1138 |
|
|
ijmp_st_cml_3 <= ijmp_st_cml_2;
|
1139 |
|
|
rjmp_st_cml_3 <= rjmp_st_cml_2;
|
1140 |
|
|
nret_st0_cml_3 <= nret_st0_cml_2;
|
1141 |
|
|
ret_st1_cml_3 <= ret_st1_cml_2;
|
1142 |
|
|
ret_st2_cml_3 <= ret_st2_cml_2;
|
1143 |
|
|
ret_st3_cml_3 <= ret_st3_cml_2;
|
1144 |
|
|
nreti_st0_cml_3 <= nreti_st0_cml_2;
|
1145 |
|
|
reti_st1_cml_3 <= reti_st1_cml_2;
|
1146 |
|
|
reti_st2_cml_3 <= reti_st2_cml_2;
|
1147 |
|
|
reti_st3_cml_3 <= reti_st3_cml_2;
|
1148 |
|
|
brxx_st_cml_3 <= brxx_st_cml_2;
|
1149 |
|
|
adiw_st_cml_3 <= adiw_st_cml_2;
|
1150 |
|
|
sbiw_st_cml_3 <= sbiw_st_cml_2;
|
1151 |
|
|
nskip_inst_st0_cml_3 <= nskip_inst_st0_cml_2;
|
1152 |
|
|
skip_inst_st1_cml_3 <= skip_inst_st1_cml_2;
|
1153 |
|
|
skip_inst_st2_cml_3 <= skip_inst_st2_cml_2;
|
1154 |
|
|
nlpm_st0_cml_3 <= nlpm_st0_cml_2;
|
1155 |
|
|
lpm_st1_cml_3 <= lpm_st1_cml_2;
|
1156 |
|
|
lpm_st2_cml_3 <= lpm_st2_cml_2;
|
1157 |
|
|
sts_st_cml_3 <= sts_st_cml_2;
|
1158 |
|
|
lds_st_cml_3 <= lds_st_cml_2;
|
1159 |
|
|
st_st_cml_3 <= st_st_cml_2;
|
1160 |
|
|
ld_st_cml_3 <= ld_st_cml_2;
|
1161 |
|
|
sbi_st_cml_3 <= sbi_st_cml_2;
|
1162 |
|
|
cbi_st_cml_3 <= cbi_st_cml_2;
|
1163 |
|
|
push_st_cml_3 <= push_st_cml_2;
|
1164 |
|
|
pop_st_cml_3 <= pop_st_cml_2;
|
1165 |
|
|
adr_int_cml_3 <= adr_int_cml_2;
|
1166 |
|
|
ramadr_int_cml_3 <= ramadr_int_cml_2;
|
1167 |
|
|
ramre_int_cml_3 <= ramre_int_cml_2;
|
1168 |
|
|
ramwe_int_cml_3 <= ramwe_int_cml_2;
|
1169 |
|
|
instruction_reg_cml_3 <= instruction_reg_cml_2;
|
1170 |
|
|
instruction_code_reg_cml_3 <= instruction_code_reg_cml_2;
|
1171 |
|
|
irq_vector_adr_cml_3 <= irq_vector_adr_cml_2;
|
1172 |
|
|
pc_for_interrupt_cml_3 <= pc_for_interrupt_cml_2;
|
1173 |
|
|
dex_dat8_immed_cml_3 <= dex_dat8_immed_cml_2;
|
1174 |
|
|
dex_adr5port_cml_3 <= dex_adr5port_cml_2;
|
1175 |
|
|
dex_adrreg_d_cml_3 <= dex_adrreg_d_cml_2;
|
1176 |
|
|
dex_bitop_bitnum_cml_3 <= dex_bitop_bitnum_cml_2;
|
1177 |
|
|
dex_adrreg_d_latched_cml_3 <= dex_adrreg_d_latched_cml_2;
|
1178 |
|
|
gp_reg_tmp_cml_3 <= gp_reg_tmp_cml_2;
|
1179 |
|
|
cbi_sbi_io_adr_tmp_cml_3 <= cbi_sbi_io_adr_tmp_cml_2;
|
1180 |
|
|
cbi_sbi_bit_num_tmp_cml_3 <= cbi_sbi_bit_num_tmp_cml_2;
|
1181 |
|
|
idc_adc_cml_3 <= idc_adc_cml_2;
|
1182 |
|
|
idc_add_cml_3 <= idc_add;
|
1183 |
|
|
idc_adiw_cml_3 <= idc_adiw_cml_2;
|
1184 |
|
|
idc_and_cml_3 <= idc_and;
|
1185 |
|
|
idc_andi_cml_3 <= idc_andi_cml_2;
|
1186 |
|
|
idc_asr_cml_3 <= idc_asr;
|
1187 |
|
|
idc_cbi_cml_3 <= idc_cbi_cml_2;
|
1188 |
|
|
idc_com_cml_3 <= idc_com;
|
1189 |
|
|
idc_cp_cml_3 <= idc_cp_cml_2;
|
1190 |
|
|
idc_cpc_cml_3 <= idc_cpc_cml_2;
|
1191 |
|
|
idc_cpi_cml_3 <= idc_cpi_cml_2;
|
1192 |
|
|
idc_cpse_cml_3 <= idc_cpse_cml_2;
|
1193 |
|
|
idc_dec_cml_3 <= idc_dec_cml_2;
|
1194 |
|
|
idc_eor_cml_3 <= idc_eor;
|
1195 |
|
|
idc_icall_cml_3 <= idc_icall_cml_2;
|
1196 |
|
|
idc_in_cml_3 <= idc_in_cml_2;
|
1197 |
|
|
idc_inc_cml_3 <= idc_inc;
|
1198 |
|
|
idc_ld_x_cml_3 <= idc_ld_x_cml_2;
|
1199 |
|
|
idc_ld_y_cml_3 <= idc_ld_y_cml_2;
|
1200 |
|
|
idc_ldd_y_cml_3 <= idc_ldd_y_cml_2;
|
1201 |
|
|
idc_ld_z_cml_3 <= idc_ld_z_cml_2;
|
1202 |
|
|
idc_ldd_z_cml_3 <= idc_ldd_z_cml_2;
|
1203 |
|
|
idc_ldi_cml_3 <= idc_ldi_cml_2;
|
1204 |
|
|
idc_lds_cml_3 <= idc_lds_cml_2;
|
1205 |
|
|
idc_lsr_cml_3 <= idc_lsr;
|
1206 |
|
|
idc_neg_cml_3 <= idc_neg;
|
1207 |
|
|
idc_or_cml_3 <= idc_or;
|
1208 |
|
|
idc_ori_cml_3 <= idc_ori_cml_2;
|
1209 |
|
|
idc_out_cml_3 <= idc_out_cml_2;
|
1210 |
|
|
idc_pop_cml_3 <= idc_pop_cml_2;
|
1211 |
|
|
idc_push_cml_3 <= idc_push_cml_2;
|
1212 |
|
|
idc_rcall_cml_3 <= idc_rcall_cml_2;
|
1213 |
|
|
idc_ret_cml_3 <= idc_ret_cml_2;
|
1214 |
|
|
idc_reti_cml_3 <= idc_reti_cml_2;
|
1215 |
|
|
idc_ror_cml_3 <= idc_ror_cml_2;
|
1216 |
|
|
idc_sbc_cml_3 <= idc_sbc_cml_2;
|
1217 |
|
|
idc_sbci_cml_3 <= idc_sbci_cml_2;
|
1218 |
|
|
idc_sbi_cml_3 <= idc_sbi_cml_2;
|
1219 |
|
|
idc_sbic_cml_3 <= idc_sbic_cml_2;
|
1220 |
|
|
idc_sbis_cml_3 <= idc_sbis_cml_2;
|
1221 |
|
|
idc_sbiw_cml_3 <= idc_sbiw_cml_2;
|
1222 |
|
|
idc_sbrc_cml_3 <= idc_sbrc;
|
1223 |
|
|
idc_sbrs_cml_3 <= idc_sbrs;
|
1224 |
|
|
idc_st_x_cml_3 <= idc_st_x_cml_2;
|
1225 |
|
|
idc_st_y_cml_3 <= idc_st_y_cml_2;
|
1226 |
|
|
idc_std_y_cml_3 <= idc_std_y_cml_2;
|
1227 |
|
|
idc_st_z_cml_3 <= idc_st_z_cml_2;
|
1228 |
|
|
idc_std_z_cml_3 <= idc_std_z_cml_2;
|
1229 |
|
|
idc_sts_cml_3 <= idc_sts_cml_2;
|
1230 |
|
|
idc_sub_cml_3 <= idc_sub_cml_2;
|
1231 |
|
|
idc_subi_cml_3 <= idc_subi_cml_2;
|
1232 |
|
|
idc_swap_cml_3 <= idc_swap;
|
1233 |
|
|
idc_prdec_cml_3 <= idc_prdec_cml_2;
|
1234 |
|
|
end if;
|
1235 |
|
|
end process;
|
1236 |
|
|
sp_ndown_up <= sp_ndown_up_cml_out;
|
1237 |
|
|
sp_en <= sp_en_cml_out;
|
1238 |
|
|
reg_rd_in <= reg_rd_in_cml_out;
|
1239 |
|
|
alu_data_r_in <= alu_data_r_in_cml_out;
|
1240 |
|
|
irqack <= irqack_cml_out;
|
1241 |
|
|
irqackad <= irqackad_cml_out;
|
1242 |
|
|
reg_rd_wr <= reg_rd_wr_cml_out;
|
1243 |
|
|
sreg_fl_in <= sreg_fl_in_cml_out;
|
1244 |
|
|
adr <= adr_cml_out;
|
1245 |
|
|
iore <= iore_cml_out;
|
1246 |
|
|
idc_adiw_out <= idc_adiw_out_cml_out;
|
1247 |
|
|
idc_andi_out <= idc_andi_out_cml_out;
|
1248 |
|
|
reg_h_wr <= reg_h_wr_cml_out;
|
1249 |
|
|
idc_ori_out <= idc_ori_out_cml_out;
|
1250 |
|
|
idc_reti_out <= idc_reti_out_cml_out;
|
1251 |
|
|
idc_sbic_out <= idc_sbic_out_cml_out;
|
1252 |
|
|
idc_sbis_out <= idc_sbis_out_cml_out;
|
1253 |
|
|
idc_sbrc_out <= idc_sbrc_out_cml_out;
|
1254 |
|
|
idc_sbrs_out <= idc_sbrs_out_cml_out;
|
1255 |
|
|
pre_dec <= pre_dec_cml_out;
|
1256 |
|
|
|
1257 |
|
|
|
1258 |
|
|
sreg_fl_wr_en <= sreg_i_wr_en & sreg_t_wr_en & sreg_h_wr_en & sreg_s_wr_en & sreg_v_wr_en & sreg_n_wr_en & sreg_z_wr_en & sreg_c_wr_en;
|
1259 |
|
|
|
1260 |
|
|
|
1261 |
|
|
-- INSTRUCTION FETCH
|
1262 |
|
|
instruction_reg_ena <= '1'; -- FOR TEST
|
1263 |
|
|
|
1264 |
|
|
-- SynEDA CoreMultiplier
|
1265 |
|
|
-- assignment(s): instruction_reg
|
1266 |
|
|
-- replace(s): inst, instruction_reg
|
1267 |
|
|
|
1268 |
|
|
instruction_fetch:process(cp2,ireset)
|
1269 |
|
|
begin
|
1270 |
|
|
if ireset='0' then -- RESET
|
1271 |
|
|
instruction_reg <= (others => '0');
|
1272 |
|
|
elsif (cp2='1' and cp2'event) then instruction_reg <= instruction_reg_cml_3; -- CLOCK
|
1273 |
|
|
if (cp2en='1') then -- Clock enable
|
1274 |
|
|
if instruction_reg_ena='1' then
|
1275 |
|
|
instruction_reg <= inst_cml_3;
|
1276 |
|
|
end if;
|
1277 |
|
|
end if;
|
1278 |
|
|
end if;
|
1279 |
|
|
end process;
|
1280 |
|
|
|
1281 |
|
|
-- SynEDA CoreMultiplier
|
1282 |
|
|
-- assignment(s): two_word_inst
|
1283 |
|
|
-- replace(s): instruction_reg
|
1284 |
|
|
|
1285 |
|
|
-- TWO WORDS INSTRUCTION DETECTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)
|
1286 |
|
|
two_word_inst <= '1' when
|
1287 |
|
|
((instruction_reg_cml_3(15 downto 9)&instruction_reg_cml_3(3 downto 1)="1001010111") or -- CALL
|
1288 |
|
|
(instruction_reg_cml_3(15 downto 9)&instruction_reg_cml_3(3 downto 1)="1001010110")) or -- JMP
|
1289 |
|
|
(instruction_reg_cml_3(15 downto 9)&instruction_reg_cml_3(3 downto 0) = "10010000000") or -- LDS
|
1290 |
|
|
(instruction_reg_cml_3(15 downto 9)&instruction_reg_cml_3(3 downto 0) = "10010010000") -- STS
|
1291 |
|
|
else '0'; -- TO DETECT CALL/JMP/LDS/STS INSTRUCTIONS FOR SBRS/SBRC/SBIS/SBIC/CPSE
|
1292 |
|
|
|
1293 |
|
|
|
1294 |
|
|
|
1295 |
|
|
-- DATA EXTRACTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)
|
1296 |
|
|
dex_dat8_immed <= instruction_reg(11 downto 8) & instruction_reg(3 downto 0);
|
1297 |
|
|
dex_dat6_immed <= instruction_reg(7 downto 6) & instruction_reg(3 downto 0);
|
1298 |
|
|
-- SynEDA CoreMultiplier
|
1299 |
|
|
-- assignment(s): dex_adr12mem_s
|
1300 |
|
|
-- replace(s): instruction_reg
|
1301 |
|
|
|
1302 |
|
|
dex_adr12mem_s <= instruction_reg_cml_3(11 downto 0);
|
1303 |
|
|
-- SynEDA CoreMultiplier
|
1304 |
|
|
-- assignment(s): dex_adr6port
|
1305 |
|
|
-- replace(s): instruction_reg
|
1306 |
|
|
|
1307 |
|
|
dex_adr6port <= instruction_reg_cml_1(10 downto 9) & instruction_reg_cml_1(3 downto 0);
|
1308 |
|
|
-- SynEDA CoreMultiplier
|
1309 |
|
|
-- assignment(s): dex_adr5port
|
1310 |
|
|
-- replace(s): instruction_reg
|
1311 |
|
|
|
1312 |
|
|
dex_adr5port <= instruction_reg_cml_1(7 downto 3);
|
1313 |
|
|
-- SynEDA CoreMultiplier
|
1314 |
|
|
-- assignment(s): dex_adr_disp
|
1315 |
|
|
-- replace(s): instruction_reg
|
1316 |
|
|
|
1317 |
|
|
dex_adr_disp <= instruction_reg_cml_1(13) & instruction_reg_cml_1(11 downto 10) & instruction_reg_cml_1(2 downto 0);
|
1318 |
|
|
-- SynEDA CoreMultiplier
|
1319 |
|
|
-- assignment(s): dex_condition
|
1320 |
|
|
-- replace(s): instruction_reg
|
1321 |
|
|
|
1322 |
|
|
dex_condition <= instruction_reg_cml_2(2 downto 0);
|
1323 |
|
|
-- SynEDA CoreMultiplier
|
1324 |
|
|
-- assignment(s): dex_bitnum_sreg
|
1325 |
|
|
-- replace(s): instruction_reg
|
1326 |
|
|
|
1327 |
|
|
dex_bitop_bitnum <= instruction_reg(2 downto 0); -- NUMBER(POSITION) OF TESTING BIT IN SBRC/SBRS/SBIC/SBIS INSTRUCTION
|
1328 |
|
|
dex_bitnum_sreg <= instruction_reg_cml_3(6 downto 4);
|
1329 |
|
|
dex_adrreg_r <= instruction_reg(9) & instruction_reg(3 downto 0);
|
1330 |
|
|
dex_adrreg_d <= instruction_reg(8 downto 4);
|
1331 |
|
|
-- SynEDA CoreMultiplier
|
1332 |
|
|
-- assignment(s): dex_brxx_offset
|
1333 |
|
|
-- replace(s): instruction_reg
|
1334 |
|
|
|
1335 |
|
|
dex_brxx_offset <= instruction_reg_cml_3(9 downto 3); -- OFFSET FOR BRBC/BRBS
|
1336 |
|
|
dex_adiw_sbiw_reg_adr <= instruction_reg(5 downto 4); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS
|
1337 |
|
|
--dex_adrindreg <= instruction_reg(3 downto 2);
|
1338 |
|
|
|
1339 |
|
|
-- SynEDA CoreMultiplier
|
1340 |
|
|
-- assignment(s): dex_adrreg_d_latched
|
1341 |
|
|
-- replace(s): dex_adrreg_d, dex_adrreg_d_latched, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
|
1342 |
|
|
|
1343 |
|
|
-- LATCH Rd ADDDRESS FOR LDS/STS/POP INSTRUCTIONS
|
1344 |
|
|
latcht_rd_adr:process(cp2,ireset)
|
1345 |
|
|
begin
|
1346 |
|
|
if ireset ='0' then
|
1347 |
|
|
dex_adrreg_d_latched <= (others => '0');
|
1348 |
|
|
elsif (cp2='1' and cp2'event) then dex_adrreg_d_latched <= dex_adrreg_d_latched_cml_3;
|
1349 |
|
|
if (cp2en='1') then -- Clock enable
|
1350 |
|
|
if ((idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ldd_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_z_cml_3) or idc_sts_cml_3 or
|
1351 |
|
|
(idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3)or idc_lds_cml_3 or
|
1352 |
|
|
idc_pop_cml_3)='1' then
|
1353 |
|
|
dex_adrreg_d_latched <= dex_adrreg_d_cml_3;
|
1354 |
|
|
end if;
|
1355 |
|
|
end if;
|
1356 |
|
|
end if;
|
1357 |
|
|
end process;
|
1358 |
|
|
-- +++++++++++++++++++++++++++++++++++++++++++++++++
|
1359 |
|
|
|
1360 |
|
|
|
1361 |
|
|
-- R24:R25/R26:R27/R28:R29/R30:R31 ADIW/SBIW ADDRESS CONTROL LOGIC
|
1362 |
|
|
adiw_sbiw_encoder_out <= "11"&dex_adiw_sbiw_reg_adr&'0';
|
1363 |
|
|
|
1364 |
|
|
-- SynEDA CoreMultiplier
|
1365 |
|
|
-- assignment(s): adiw_sbiw_encoder_mux_out
|
1366 |
|
|
-- replace(s): adiw_sbiw_encoder_out, adiw_sbiw_encoder_mux_out
|
1367 |
|
|
|
1368 |
|
|
adiw_sbiw_high_reg_adr:process(cp2,ireset)
|
1369 |
|
|
begin
|
1370 |
|
|
if ireset ='0' then
|
1371 |
|
|
adiw_sbiw_encoder_mux_out <= (others=>'0');
|
1372 |
|
|
elsif(cp2='1' and cp2'event) then adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_mux_out_cml_3;
|
1373 |
|
|
if (cp2en='1') then -- Clock enable
|
1374 |
|
|
adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_out_cml_3 +1;
|
1375 |
|
|
end if;
|
1376 |
|
|
end if;
|
1377 |
|
|
end process;
|
1378 |
|
|
|
1379 |
|
|
-- ##########################
|
1380 |
|
|
|
1381 |
|
|
-- NOP INSERTION
|
1382 |
|
|
|
1383 |
|
|
--instruction_code_reg <= instruction_reg when nop_insert_st='0' else (others => '0');
|
1384 |
|
|
instruction_code_reg <= (others => '0') when (nop_insert_st='1') else -- NOP
|
1385 |
|
|
instruction_reg; -- Instruction
|
1386 |
|
|
|
1387 |
|
|
|
1388 |
|
|
nop_insert_st <= adiw_st or sbiw_st or cbi_st or sbi_st or rjmp_st or ijmp_st or pop_st or push_st or
|
1389 |
|
|
brxx_st or ld_st or st_st or ncall_st0 or nirq_st0 or nret_st0 or nreti_st0 or nlpm_st0 or njmp_st0 or
|
1390 |
|
|
nrcall_st0 or nicall_st0 or sts_st or lds_st or nskip_inst_st0;
|
1391 |
|
|
|
1392 |
|
|
|
1393 |
|
|
-- INSTRUCTION DECODER (CONNECTED AFTER NOP INSERTION LOGIC)
|
1394 |
|
|
|
1395 |
|
|
-- SynEDA CoreMultiplier
|
1396 |
|
|
-- assignment(s): idc_add
|
1397 |
|
|
-- replace(s): instruction_code_reg
|
1398 |
|
|
|
1399 |
|
|
idc_adc <= '1' when instruction_code_reg(15 downto 10) = "000111" else '0'; -- 000111XXXXXXXXXX
|
1400 |
|
|
idc_add <= '1' when instruction_code_reg_cml_2(15 downto 10) = "000011" else '0'; -- 000011XXXXXXXXXX
|
1401 |
|
|
|
1402 |
|
|
idc_adiw <= '1' when instruction_code_reg(15 downto 8) = "10010110" else '0'; -- 10010110XXXXXXXX
|
1403 |
|
|
|
1404 |
|
|
-- SynEDA CoreMultiplier
|
1405 |
|
|
-- assignment(s): idc_and
|
1406 |
|
|
-- replace(s): instruction_code_reg
|
1407 |
|
|
|
1408 |
|
|
idc_and <= '1' when instruction_code_reg_cml_2(15 downto 10) = "001000" else '0'; -- 001000XXXXXXXXXX
|
1409 |
|
|
idc_andi <= '1' when instruction_code_reg(15 downto 12) = "0111" else '0'; -- 0111XXXXXXXXXXXX
|
1410 |
|
|
|
1411 |
|
|
-- SynEDA CoreMultiplier
|
1412 |
|
|
-- assignment(s): idc_asr
|
1413 |
|
|
-- replace(s): instruction_code_reg
|
1414 |
|
|
|
1415 |
|
|
idc_asr <= '1' when instruction_code_reg_cml_2(15 downto 9)&instruction_code_reg_cml_2(3 downto 0) = "10010100101" else '0'; -- 1001010XXXXX0101
|
1416 |
|
|
|
1417 |
|
|
-- SynEDA CoreMultiplier
|
1418 |
|
|
-- assignment(s): idc_bclr
|
1419 |
|
|
-- replace(s): instruction_code_reg
|
1420 |
|
|
|
1421 |
|
|
idc_bclr <= '1' when instruction_code_reg_cml_3(15 downto 7)&instruction_code_reg_cml_3(3 downto 0) = "1001010011000" else '0'; -- 100101001XXX1000
|
1422 |
|
|
|
1423 |
|
|
-- SynEDA CoreMultiplier
|
1424 |
|
|
-- assignment(s): idc_bld
|
1425 |
|
|
-- replace(s): instruction_code_reg
|
1426 |
|
|
|
1427 |
|
|
idc_bld <= '1' when instruction_code_reg_cml_3(15 downto 9)&instruction_code_reg_cml_3(3) = "11111000" else '0'; -- 1111100XXXXX0XXX
|
1428 |
|
|
|
1429 |
|
|
-- SynEDA CoreMultiplier
|
1430 |
|
|
-- assignment(s): idc_brbs
|
1431 |
|
|
-- replace(s): instruction_code_reg
|
1432 |
|
|
|
1433 |
|
|
-- SynEDA CoreMultiplier
|
1434 |
|
|
-- assignment(s): idc_brbc
|
1435 |
|
|
-- replace(s): instruction_code_reg
|
1436 |
|
|
|
1437 |
|
|
idc_brbc <= '1' when instruction_code_reg_cml_3(15 downto 10) = "111101" else '0'; -- 111101XXXXXXXXXX
|
1438 |
|
|
idc_brbs <= '1' when instruction_code_reg_cml_3(15 downto 10) = "111100" else '0'; -- 111100XXXXXXXXXX
|
1439 |
|
|
|
1440 |
|
|
-- SynEDA CoreMultiplier
|
1441 |
|
|
-- assignment(s): idc_bset
|
1442 |
|
|
-- replace(s): instruction_code_reg
|
1443 |
|
|
|
1444 |
|
|
idc_bset <= '1' when instruction_code_reg_cml_3(15 downto 7)&instruction_code_reg_cml_3(3 downto 0) = "1001010001000" else '0'; -- 100101000XXX1000
|
1445 |
|
|
|
1446 |
|
|
-- SynEDA CoreMultiplier
|
1447 |
|
|
-- assignment(s): idc_bst
|
1448 |
|
|
-- replace(s): instruction_code_reg
|
1449 |
|
|
|
1450 |
|
|
idc_bst <= '1' when instruction_code_reg_cml_3(15 downto 9) = "1111101" else '0'; -- 1111101XXXXXXXXX
|
1451 |
|
|
|
1452 |
|
|
-- SynEDA CoreMultiplier
|
1453 |
|
|
-- assignment(s): idc_call
|
1454 |
|
|
-- replace(s): instruction_code_reg
|
1455 |
|
|
|
1456 |
|
|
idc_call <= '1' when instruction_code_reg_cml_3(15 downto 9)&instruction_code_reg_cml_3(3 downto 1) = "1001010111" else '0'; -- 1001010XXXXX111X
|
1457 |
|
|
|
1458 |
|
|
-- SynEDA CoreMultiplier
|
1459 |
|
|
-- assignment(s): idc_cbi
|
1460 |
|
|
-- replace(s): instruction_code_reg
|
1461 |
|
|
|
1462 |
|
|
idc_cbi <= '1' when instruction_code_reg_cml_1(15 downto 8) = "10011000" else '0'; -- 10011000XXXXXXXX
|
1463 |
|
|
|
1464 |
|
|
-- SynEDA CoreMultiplier
|
1465 |
|
|
-- assignment(s): idc_com
|
1466 |
|
|
-- replace(s): instruction_code_reg
|
1467 |
|
|
|
1468 |
|
|
idc_com <= '1' when instruction_code_reg_cml_2(15 downto 9)&instruction_code_reg_cml_2(3 downto 0) = "10010100000" else '0'; -- 1001010XXXXX0000
|
1469 |
|
|
|
1470 |
|
|
idc_cp <= '1' when instruction_code_reg(15 downto 10) = "000101" else '0'; -- 000101XXXXXXXXXX
|
1471 |
|
|
|
1472 |
|
|
idc_cpc <= '1' when instruction_code_reg(15 downto 10) = "000001" else '0'; -- 000001XXXXXXXXXX
|
1473 |
|
|
|
1474 |
|
|
idc_cpi <= '1' when instruction_code_reg(15 downto 12) = "0011" else '0'; -- 0011XXXXXXXXXXXX
|
1475 |
|
|
|
1476 |
|
|
idc_cpse <= '1' when instruction_code_reg(15 downto 10) = "000100" else '0'; -- 000100XXXXXXXXXX
|
1477 |
|
|
|
1478 |
|
|
-- SynEDA CoreMultiplier
|
1479 |
|
|
-- assignment(s): idc_dec
|
1480 |
|
|
-- replace(s): instruction_code_reg
|
1481 |
|
|
|
1482 |
|
|
idc_dec <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010101010" else '0'; -- 1001010XXXXX1010
|
1483 |
|
|
|
1484 |
|
|
-- SynEDA CoreMultiplier
|
1485 |
|
|
-- assignment(s): idc_elpm
|
1486 |
|
|
-- replace(s): instruction_code_reg
|
1487 |
|
|
|
1488 |
|
|
idc_elpm <= '1' when instruction_code_reg_cml_3 = "1001010111011000" else '0'; -- 1001010111011000
|
1489 |
|
|
|
1490 |
|
|
-- SynEDA CoreMultiplier
|
1491 |
|
|
-- assignment(s): idc_eor
|
1492 |
|
|
-- replace(s): instruction_code_reg
|
1493 |
|
|
|
1494 |
|
|
idc_eor <= '1' when instruction_code_reg_cml_2(15 downto 10) = "001001" else '0'; -- 001001XXXXXXXXXX
|
1495 |
|
|
|
1496 |
|
|
idc_icall<= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101011001" else '0'; -- 10010101XXXX1001
|
1497 |
|
|
|
1498 |
|
|
-- SynEDA CoreMultiplier
|
1499 |
|
|
-- assignment(s): idc_ijmp
|
1500 |
|
|
-- replace(s): instruction_code_reg
|
1501 |
|
|
|
1502 |
|
|
idc_ijmp <= '1' when instruction_code_reg_cml_3(15 downto 8)&instruction_code_reg_cml_3(3 downto 0) = "100101001001" else '0'; -- 10010100XXXX1001
|
1503 |
|
|
|
1504 |
|
|
-- SynEDA CoreMultiplier
|
1505 |
|
|
-- assignment(s): idc_in
|
1506 |
|
|
-- replace(s): instruction_code_reg
|
1507 |
|
|
|
1508 |
|
|
idc_in <= '1' when instruction_code_reg_cml_1(15 downto 11) = "10110" else '0'; -- 10110XXXXXXXXXXX
|
1509 |
|
|
|
1510 |
|
|
-- SynEDA CoreMultiplier
|
1511 |
|
|
-- assignment(s): idc_inc
|
1512 |
|
|
-- replace(s): instruction_code_reg
|
1513 |
|
|
|
1514 |
|
|
idc_inc <= '1' when instruction_code_reg_cml_2(15 downto 9)&instruction_code_reg_cml_2(3 downto 0) = "10010100011" else '0'; -- 1001010XXXXX0011
|
1515 |
|
|
|
1516 |
|
|
-- SynEDA CoreMultiplier
|
1517 |
|
|
-- assignment(s): idc_jmp
|
1518 |
|
|
-- replace(s): instruction_code_reg
|
1519 |
|
|
|
1520 |
|
|
idc_jmp <= '1' when instruction_code_reg_cml_3(15 downto 9)&instruction_code_reg_cml_3(3 downto 1) = "1001010110" else '0'; -- 1001010XXXXX110X
|
1521 |
|
|
|
1522 |
|
|
|
1523 |
|
|
-- LD,LDD
|
1524 |
|
|
idc_ld_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001100" or
|
1525 |
|
|
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001101" or
|
1526 |
|
|
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001110" else '0';
|
1527 |
|
|
|
1528 |
|
|
idc_ld_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001001" or
|
1529 |
|
|
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001010") else '0';
|
1530 |
|
|
|
1531 |
|
|
idc_ldd_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10001" else '0'; -- 10X0XX0XXXXX1XXX
|
1532 |
|
|
|
1533 |
|
|
idc_ld_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000001" or
|
1534 |
|
|
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000010") else '0';
|
1535 |
|
|
|
1536 |
|
|
idc_ldd_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10000" else '0'; -- 10X0XX0XXXXX0XXX
|
1537 |
|
|
-- ######
|
1538 |
|
|
|
1539 |
|
|
|
1540 |
|
|
idc_ldi <= '1' when instruction_code_reg(15 downto 12) = "1110" else '0'; -- 1110XXXXXXXXXXXX
|
1541 |
|
|
|
1542 |
|
|
idc_lds <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010000000" else '0'; -- 1001000XXXXX0000
|
1543 |
|
|
|
1544 |
|
|
-- SynEDA CoreMultiplier
|
1545 |
|
|
-- assignment(s): idc_lpm
|
1546 |
|
|
-- replace(s): instruction_code_reg
|
1547 |
|
|
|
1548 |
|
|
idc_lpm <= '1' when instruction_code_reg_cml_3 = "1001010111001000" else '0'; -- 1001010111001000
|
1549 |
|
|
|
1550 |
|
|
-- SynEDA CoreMultiplier
|
1551 |
|
|
-- assignment(s): idc_lsr
|
1552 |
|
|
-- replace(s): instruction_code_reg
|
1553 |
|
|
|
1554 |
|
|
idc_lsr <= '1' when instruction_code_reg_cml_2(15 downto 9)&instruction_code_reg_cml_2(3 downto 0) = "10010100110" else '0'; -- 1001010XXXXX0110
|
1555 |
|
|
|
1556 |
|
|
-- SynEDA CoreMultiplier
|
1557 |
|
|
-- assignment(s): idc_mov
|
1558 |
|
|
-- replace(s): instruction_code_reg
|
1559 |
|
|
|
1560 |
|
|
idc_mov <= '1' when instruction_code_reg_cml_3(15 downto 10) = "001011" else '0'; -- 001011XXXXXXXXXX
|
1561 |
|
|
|
1562 |
|
|
idc_mul <= '1' when instruction_code_reg(15 downto 10) = "100111" else '0'; -- 100111XXXXXXXXXX
|
1563 |
|
|
|
1564 |
|
|
-- SynEDA CoreMultiplier
|
1565 |
|
|
-- assignment(s): idc_neg
|
1566 |
|
|
-- replace(s): instruction_code_reg
|
1567 |
|
|
|
1568 |
|
|
idc_neg <= '1' when instruction_code_reg_cml_2(15 downto 9)&instruction_code_reg_cml_2(3 downto 0) = "10010100001" else '0'; -- 1001010XXXXX0001
|
1569 |
|
|
|
1570 |
|
|
idc_nop <= '1' when instruction_code_reg = "0000000000000000" else '0'; -- 0000000000000000
|
1571 |
|
|
|
1572 |
|
|
-- SynEDA CoreMultiplier
|
1573 |
|
|
-- assignment(s): idc_or
|
1574 |
|
|
-- replace(s): instruction_code_reg
|
1575 |
|
|
|
1576 |
|
|
idc_or <= '1' when instruction_code_reg_cml_2(15 downto 10) = "001010" else '0'; -- 001010XXXXXXXXXX
|
1577 |
|
|
|
1578 |
|
|
idc_ori <= '1' when instruction_code_reg(15 downto 12) = "0110" else '0'; -- 0110XXXXXXXXXXXX
|
1579 |
|
|
|
1580 |
|
|
idc_out <= '1' when instruction_code_reg(15 downto 11) = "10111" else '0'; -- 10111XXXXXXXXXXX
|
1581 |
|
|
|
1582 |
|
|
idc_pop <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001111" else '0'; -- 1001000XXXXX1111
|
1583 |
|
|
|
1584 |
|
|
idc_push<= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011111" else '0'; -- 1001001XXXXX1111
|
1585 |
|
|
|
1586 |
|
|
idc_rcall<= '1' when instruction_code_reg(15 downto 12) = "1101" else '0'; -- 1101XXXXXXXXXXXX
|
1587 |
|
|
|
1588 |
|
|
idc_ret <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101001000" else '0'; -- 100101010XX01000
|
1589 |
|
|
|
1590 |
|
|
idc_reti <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101011000" else '0'; -- 100101010XX11000
|
1591 |
|
|
|
1592 |
|
|
-- SynEDA CoreMultiplier
|
1593 |
|
|
-- assignment(s): idc_rjmp
|
1594 |
|
|
-- replace(s): instruction_code_reg
|
1595 |
|
|
|
1596 |
|
|
idc_rjmp <= '1' when instruction_code_reg_cml_3(15 downto 12) = "1100" else '0'; -- 1100XXXXXXXXXXXX
|
1597 |
|
|
|
1598 |
|
|
idc_ror <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100111" else '0'; -- 1001010XXXXX0111
|
1599 |
|
|
|
1600 |
|
|
idc_sbc <= '1' when instruction_code_reg(15 downto 10) = "000010" else '0'; -- 000010XXXXXXXXXX
|
1601 |
|
|
|
1602 |
|
|
idc_sbci <= '1' when instruction_code_reg(15 downto 12) = "0100" else '0'; -- 0100XXXXXXXXXXXX
|
1603 |
|
|
|
1604 |
|
|
-- SynEDA CoreMultiplier
|
1605 |
|
|
-- assignment(s): idc_sbi
|
1606 |
|
|
-- replace(s): instruction_code_reg
|
1607 |
|
|
|
1608 |
|
|
idc_sbi <= '1' when instruction_code_reg_cml_1(15 downto 8) = "10011010" else '0'; -- 10011010XXXXXXXX
|
1609 |
|
|
|
1610 |
|
|
-- SynEDA CoreMultiplier
|
1611 |
|
|
-- assignment(s): idc_sbic
|
1612 |
|
|
-- replace(s): instruction_code_reg
|
1613 |
|
|
|
1614 |
|
|
idc_sbic <= '1' when instruction_code_reg_cml_1(15 downto 8) = "10011001" else '0'; -- 10011001XXXXXXXX
|
1615 |
|
|
|
1616 |
|
|
-- SynEDA CoreMultiplier
|
1617 |
|
|
-- assignment(s): idc_sbis
|
1618 |
|
|
-- replace(s): instruction_code_reg
|
1619 |
|
|
|
1620 |
|
|
idc_sbis <= '1' when instruction_code_reg_cml_1(15 downto 8) = "10011011" else '0'; -- 10011011XXXXXXXX
|
1621 |
|
|
|
1622 |
|
|
idc_sbiw <= '1' when instruction_code_reg(15 downto 8) = "10010111" else '0'; -- 10010111XXXXXXXX
|
1623 |
|
|
|
1624 |
|
|
-- SynEDA CoreMultiplier
|
1625 |
|
|
-- assignment(s): idc_sbrc
|
1626 |
|
|
-- replace(s): instruction_code_reg
|
1627 |
|
|
|
1628 |
|
|
idc_sbrc <= '1' when instruction_code_reg_cml_2(15 downto 9) = "1111110" else '0'; -- 1111110XXXXXXXXX
|
1629 |
|
|
|
1630 |
|
|
-- SynEDA CoreMultiplier
|
1631 |
|
|
-- assignment(s): idc_sbrs
|
1632 |
|
|
-- replace(s): instruction_code_reg
|
1633 |
|
|
|
1634 |
|
|
idc_sbrs <= '1' when instruction_code_reg_cml_2(15 downto 9) = "1111111" else '0'; -- 1111111XXXXXXXXX
|
1635 |
|
|
|
1636 |
|
|
-- SynEDA CoreMultiplier
|
1637 |
|
|
-- assignment(s): idc_sleep
|
1638 |
|
|
-- replace(s): instruction_code_reg
|
1639 |
|
|
|
1640 |
|
|
idc_sleep<= '1' when instruction_code_reg_cml_3(15 downto 5)&instruction_code_reg_cml_3(3 downto 0) = "100101011001000" else '0'; -- 10010101100X1000
|
1641 |
|
|
|
1642 |
|
|
|
1643 |
|
|
-- ST,STD
|
1644 |
|
|
idc_st_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011100" or
|
1645 |
|
|
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011101" or
|
1646 |
|
|
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011110" else '0';
|
1647 |
|
|
|
1648 |
|
|
idc_st_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011001" or
|
1649 |
|
|
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011010") else '0';
|
1650 |
|
|
|
1651 |
|
|
idc_std_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10011" else '0'; -- 10X0XX1XXXXX1XXX
|
1652 |
|
|
|
1653 |
|
|
idc_st_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010001" or
|
1654 |
|
|
instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010010") else '0';
|
1655 |
|
|
|
1656 |
|
|
idc_std_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10010" else '0'; -- 10X0XX1XXXXX0XXX
|
1657 |
|
|
-- ######
|
1658 |
|
|
|
1659 |
|
|
idc_sts <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010010000" else '0'; -- 1001001XXXXX0000
|
1660 |
|
|
|
1661 |
|
|
idc_sub <= '1' when instruction_code_reg(15 downto 10) = "000110" else '0'; -- 000110XXXXXXXXXX
|
1662 |
|
|
|
1663 |
|
|
idc_subi <= '1' when instruction_code_reg(15 downto 12) = "0101" else '0'; -- 0101XXXXXXXXXXXX
|
1664 |
|
|
|
1665 |
|
|
-- SynEDA CoreMultiplier
|
1666 |
|
|
-- assignment(s): idc_swap
|
1667 |
|
|
-- replace(s): instruction_code_reg
|
1668 |
|
|
|
1669 |
|
|
idc_swap <= '1' when instruction_code_reg_cml_2(15 downto 9)&instruction_code_reg_cml_2(3 downto 0) = "10010100010" else '0'; -- 1001010XXXXX0010
|
1670 |
|
|
|
1671 |
|
|
-- SynEDA CoreMultiplier
|
1672 |
|
|
-- assignment(s): idc_wdr
|
1673 |
|
|
-- replace(s): instruction_code_reg
|
1674 |
|
|
|
1675 |
|
|
idc_wdr <= '1' when instruction_code_reg_cml_3(15 downto 5)&instruction_code_reg_cml_3(3 downto 0) = "100101011011000" else '0'; -- 10010101101X1000
|
1676 |
|
|
|
1677 |
|
|
-- SynEDA CoreMultiplier
|
1678 |
|
|
-- assignment(s): idc_psinc
|
1679 |
|
|
-- replace(s): instruction_code_reg, idc_ld_x, idc_ld_y, idc_ld_z, idc_st_x, idc_st_y, idc_st_z
|
1680 |
|
|
|
1681 |
|
|
-- ADDITIONAL SIGNALS
|
1682 |
|
|
idc_psinc <= '1' when (instruction_code_reg_cml_3(1 downto 0) = "01" and
|
1683 |
|
|
(idc_st_x_cml_3 or idc_st_y_cml_3 or idc_st_z_cml_3 or idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ld_z_cml_3)='1') else '0'; -- POST INCREMENT FOR LD/ST INSTRUCTIONS
|
1684 |
|
|
|
1685 |
|
|
idc_prdec <= '1' when (instruction_code_reg(1 downto 0) = "10" and
|
1686 |
|
|
(idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0'; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
|
1687 |
|
|
|
1688 |
|
|
|
1689 |
|
|
-- ##########################################################################################################
|
1690 |
|
|
|
1691 |
|
|
-- SynEDA CoreMultiplier
|
1692 |
|
|
-- assignment(s): ramadr_reg_en
|
1693 |
|
|
-- replace(s): cpuwait, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
|
1694 |
|
|
|
1695 |
|
|
-- WRITE ENABLE SIGNALS FOR ramadr_reg
|
1696 |
|
|
ramadr_reg_en <= idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ldd_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_z_cml_3 or idc_lds_cml_3 or -- LD/LDD/LDS(two cycle execution)
|
1697 |
|
|
idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3 or idc_sts_cml_3 or -- ST/STS/STS(two cycle execution)
|
1698 |
|
|
idc_push_cml_3 or idc_pop_cml_3 or
|
1699 |
|
|
idc_rcall_cml_3 or (rcall_st1_cml_3 and not cpuwait_cml_3) or idc_icall_cml_3 or (icall_st1_cml_3 and not cpuwait_cml_3) or -- RCALL/ICALL
|
1700 |
|
|
call_st1_cml_3 or (call_st2_cml_3 and not cpuwait_cml_3) or irq_st1_cml_3 or (irq_st2_cml_3 and not cpuwait_cml_3) or -- CALL/IRQ
|
1701 |
|
|
idc_ret_cml_3 or (ret_st1_cml_3 and not cpuwait_cml_3 ) or idc_reti_cml_3 or (reti_st1_cml_3 and not cpuwait_cml_3); -- RET/RETI -- ??
|
1702 |
|
|
|
1703 |
|
|
|
1704 |
|
|
-- SynEDA CoreMultiplier
|
1705 |
|
|
-- assignment(s): ramadr_reg_in
|
1706 |
|
|
-- replace(s): inst, cpuwait, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_ld_x, idc_ld_y, idc_ld_z, idc_lds, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_st_x, idc_st_y, idc_st_z, idc_sts
|
1707 |
|
|
|
1708 |
|
|
-- RAMADR MUX
|
1709 |
|
|
ramadr_reg_in <= sph_out&spl_out when
|
1710 |
|
|
(idc_rcall_cml_1 or (rcall_st1_cml_1 and not cpuwait_cml_1)or idc_icall_cml_1 or (icall_st1_cml_1 and not cpuwait_cml_1)or -- RCALL/ICALL
|
1711 |
|
|
call_st1_cml_1 or (call_st2_cml_1 and not cpuwait_cml_1) or irq_st1_cml_1 or (irq_st2_cml_1 and not cpuwait_cml_1) or -- CALL/IRQ
|
1712 |
|
|
idc_push_cml_1 )='1' else -- PUSH
|
1713 |
|
|
(sph_out&spl_out)+1 when (idc_ret_cml_1 or (ret_st1_cml_1 and not cpuwait_cml_1) or idc_reti_cml_1 or (reti_st1_cml_1 and not cpuwait_cml_1) or idc_pop_cml_1)='1' else -- RET/RETI/POP
|
1714 |
|
|
inst_cml_1 when (idc_lds_cml_1 or idc_sts_cml_1) ='1' else -- LDS/STS (two cycle execution)
|
1715 |
|
|
reg_h_out when (idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ld_z_cml_1 or idc_st_x_cml_1 or idc_st_y_cml_1 or idc_st_z_cml_1)='1' else -- LD/ST
|
1716 |
|
|
(reg_h_out + ("000000000"&dex_adr_disp)); -- LDD/STD
|
1717 |
|
|
|
1718 |
|
|
|
1719 |
|
|
-- SynEDA CoreMultiplier
|
1720 |
|
|
-- assignment(s): ramadr_int
|
1721 |
|
|
-- replace(s): ramadr_reg_in, ramadr_int
|
1722 |
|
|
|
1723 |
|
|
-- ADDRESS REGISTER
|
1724 |
|
|
ramadr_reg:process(cp2,ireset)
|
1725 |
|
|
begin
|
1726 |
|
|
if ireset='0' then
|
1727 |
|
|
ramadr_int <= (others => '0');
|
1728 |
|
|
elsif(cp2='1' and cp2'event) then ramadr_int <= ramadr_int_cml_3;
|
1729 |
|
|
if (cp2en='1') then -- Clock enable
|
1730 |
|
|
if (ramadr_reg_en='1') then
|
1731 |
|
|
ramadr_int <= ramadr_reg_in_cml_3;
|
1732 |
|
|
end if;
|
1733 |
|
|
end if;
|
1734 |
|
|
end if;
|
1735 |
|
|
end process;
|
1736 |
|
|
|
1737 |
|
|
ramadr <= ramadr_int;
|
1738 |
|
|
|
1739 |
|
|
-- SynEDA CoreMultiplier
|
1740 |
|
|
-- assignment(s): reg_file_adr_space
|
1741 |
|
|
-- replace(s): ramadr_reg_in, reg_file_adr_space
|
1742 |
|
|
|
1743 |
|
|
-- GENERAL PURPOSE REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS
|
1744 |
|
|
gp_reg_adr:process(cp2,ireset)
|
1745 |
|
|
begin
|
1746 |
|
|
if ireset='0' then
|
1747 |
|
|
reg_file_adr_space <='0';
|
1748 |
|
|
elsif(cp2='1' and cp2'event) then reg_file_adr_space <= reg_file_adr_space_cml_3;
|
1749 |
|
|
if (cp2en='1') then -- Clock enable
|
1750 |
|
|
if (ramadr_reg_en='1') then
|
1751 |
|
|
if (ramadr_reg_in_cml_3(15 downto 5)=const_ram_to_reg) then
|
1752 |
|
|
reg_file_adr_space <= '1'; -- ADRESS RANGE 0x0000-0x001F -> REGISTERS (R0-R31)
|
1753 |
|
|
else
|
1754 |
|
|
reg_file_adr_space <= '0';
|
1755 |
|
|
end if;
|
1756 |
|
|
end if;
|
1757 |
|
|
end if;
|
1758 |
|
|
end if;
|
1759 |
|
|
end process;
|
1760 |
|
|
|
1761 |
|
|
-- SynEDA CoreMultiplier
|
1762 |
|
|
-- assignment(s): io_file_adr_space
|
1763 |
|
|
-- replace(s): ramadr_reg_in, io_file_adr_space
|
1764 |
|
|
|
1765 |
|
|
-- I/O REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS
|
1766 |
|
|
io_reg_adr:process(cp2,ireset)
|
1767 |
|
|
begin
|
1768 |
|
|
if ireset='0' then io_file_adr_space<='0';
|
1769 |
|
|
elsif(cp2='1' and cp2'event) then io_file_adr_space <= io_file_adr_space_cml_3;
|
1770 |
|
|
if (cp2en='1') then -- Clock enable
|
1771 |
|
|
if (ramadr_reg_en='1') then
|
1772 |
|
|
if (ramadr_reg_in_cml_3(15 downto 5)=const_ram_to_io_a or ramadr_reg_in_cml_3(15 downto 5)=const_ram_to_io_b) then
|
1773 |
|
|
io_file_adr_space <= '1'; -- ADRESS RANGE 0x0020-0x005F -> I/O PORTS (0x00-0x3F)
|
1774 |
|
|
else
|
1775 |
|
|
io_file_adr_space <= '0';
|
1776 |
|
|
end if;
|
1777 |
|
|
end if;
|
1778 |
|
|
end if;
|
1779 |
|
|
end if;
|
1780 |
|
|
end process;
|
1781 |
|
|
|
1782 |
|
|
|
1783 |
|
|
|
1784 |
|
|
-- ##########################################################################################################
|
1785 |
|
|
|
1786 |
|
|
|
1787 |
|
|
-- REGRE/REGWE LOGIC (5 BIT ADDSRESS BUS (INTERNAL ONLY) 32 LOCATIONS (R0-R31))
|
1788 |
|
|
|
1789 |
|
|
-- SynEDA CoreMultiplier
|
1790 |
|
|
-- assignment(s): alu_reg_wr
|
1791 |
|
|
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_adiw, idc_and, idc_andi, idc_asr, idc_com, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi, idc_swap
|
1792 |
|
|
|
1793 |
|
|
-- WRITE ENABLE FOR Rd REGISTERS
|
1794 |
|
|
alu_reg_wr <= idc_adc_cml_3 or idc_add_cml_3 or idc_adiw_cml_3 or adiw_st_cml_3 or idc_sub_cml_3 or idc_subi_cml_3 or idc_sbc_cml_3 or idc_sbci_cml_3 or
|
1795 |
|
|
idc_sbiw_cml_3 or sbiw_st_cml_3 or idc_and_cml_3 or idc_andi_cml_3 or idc_or_cml_3 or idc_ori_cml_3 or idc_eor_cml_3 or idc_com_cml_3 or
|
1796 |
|
|
idc_neg_cml_3 or idc_inc_cml_3 or idc_dec_cml_3 or idc_lsr_cml_3 or idc_ror_cml_3 or idc_asr_cml_3 or idc_swap_cml_3;
|
1797 |
|
|
|
1798 |
|
|
|
1799 |
|
|
-- SynEDA CoreMultiplier
|
1800 |
|
|
-- assignment(s): reg_rd_wr
|
1801 |
|
|
-- replace(s): reg_file_adr_space, lpm_st2, sts_st, lds_st, st_st, ld_st, pop_st, idc_in, idc_ldi
|
1802 |
|
|
|
1803 |
|
|
reg_rd_wr_cml_out <= idc_in_cml_3 or alu_reg_wr or idc_bld or -- ALU INSTRUCTIONS + IN/BLD INSRTRUCTION
|
1804 |
|
|
(pop_st_cml_3 or ld_st_cml_3 or lds_st_cml_3)or -- POP/LD/LDD/LDS INSTRUCTIONS
|
1805 |
|
|
((st_st_cml_3 or sts_st_cml_3) and reg_file_adr_space_cml_3)or -- ST/STD/STS INSTRUCTION
|
1806 |
|
|
lpm_st2_cml_3 or idc_ldi_cml_3 or idc_mov; -- LPM/LDI/MOV INSTRUCTION
|
1807 |
|
|
|
1808 |
|
|
|
1809 |
|
|
reg_rd_adr <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else
|
1810 |
|
|
"00000" when lpm_st2='1' else
|
1811 |
|
|
adiw_sbiw_encoder_out when (idc_adiw or idc_sbiw)='1' else
|
1812 |
|
|
adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else
|
1813 |
|
|
dex_adrreg_d_latched when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else
|
1814 |
|
|
ramadr_int(4 downto 0) when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
|
1815 |
|
|
dex_adrreg_d;
|
1816 |
|
|
|
1817 |
|
|
reg_rd_adr_int <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else
|
1818 |
|
|
"00000" when lpm_st2='1' else
|
1819 |
|
|
adiw_sbiw_encoder_out when (idc_adiw or idc_sbiw)='1' else
|
1820 |
|
|
adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else
|
1821 |
|
|
dex_adrreg_d_latched when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else
|
1822 |
|
|
ramadr_int(4 downto 0) when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
|
1823 |
|
|
dex_adrreg_d;
|
1824 |
|
|
|
1825 |
|
|
reg_rr_adr <= ramadr_int(4 downto 0) when ((ld_st or lds_st) and reg_file_adr_space)='1'else --!!??
|
1826 |
|
|
dex_adrreg_d_latched when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
|
1827 |
|
|
dex_adrreg_r;
|
1828 |
|
|
|
1829 |
|
|
-- SynEDA CoreMultiplier
|
1830 |
|
|
-- assignment(s): reg_rd_in
|
1831 |
|
|
-- replace(s): dbusin, reg_rr_out, reg_file_adr_space, lpm_st2, sts_st, lds_st, st_st, ld_st, pop_st, instruction_reg, dex_dat8_immed, gp_reg_tmp, idc_in, idc_ldi
|
1832 |
|
|
|
1833 |
|
|
-- MULTIPLEXER FOR REGISTER FILE Rd INPUT
|
1834 |
|
|
reg_rd_in_cml_out <= dbusin_cml_3 when (idc_in_cml_3 or ((lds_st_cml_3 or ld_st_cml_3)and not reg_file_adr_space_cml_3) or pop_st_cml_3)='1' else -- FROM INPUT DATA BUS
|
1835 |
|
|
reg_rr_out_cml_3 when ((lds_st_cml_3 or ld_st_cml_3) and reg_file_adr_space_cml_3)='1' else
|
1836 |
|
|
gp_reg_tmp_cml_3 when ((st_st_cml_3 or sts_st_cml_3) and reg_file_adr_space_cml_3)='1' else -- ST/STD/STS & ADDRESS FROM 0 TO 31 (REGISTER FILE)
|
1837 |
|
|
bld_op_out when (idc_bld='1')else -- FROM BIT PROCESSOR BLD COMMAND
|
1838 |
|
|
reg_rr_out_cml_3 when (idc_mov='1')else -- FOR MOV INSTRUCTION
|
1839 |
|
|
instruction_reg_cml_3(15 downto 8) when (lpm_st2_cml_3='1' and reg_z_out(0)='1') else -- LPM/ELPM
|
1840 |
|
|
instruction_reg_cml_3(7 downto 0) when (lpm_st2_cml_3='1' and reg_z_out(0)='0') else -- LPM/ELPM
|
1841 |
|
|
dex_dat8_immed_cml_3 when idc_ldi_cml_3='1' else
|
1842 |
|
|
alu_data_out; -- FROM ALU DATA OUT
|
1843 |
|
|
|
1844 |
|
|
-- SynEDA CoreMultiplier
|
1845 |
|
|
-- assignment(s): iowe_int
|
1846 |
|
|
-- replace(s): io_file_adr_space, sts_st, st_st, sbi_st, cbi_st, idc_out
|
1847 |
|
|
|
1848 |
|
|
-- SynEDA CoreMultiplier
|
1849 |
|
|
-- assignment(s): iore_int
|
1850 |
|
|
-- replace(s): io_file_adr_space, lds_st, ld_st
|
1851 |
|
|
|
1852 |
|
|
-- IORE/IOWE LOGIC (6 BIT ADDRESS adr[5..0] FOR I/O PORTS(64 LOCATIONS))
|
1853 |
|
|
iore_int <= idc_in or idc_sbi or idc_cbi or idc_sbic or idc_sbis or ((ld_st_cml_1 or lds_st_cml_1) and io_file_adr_space_cml_1); -- IN/SBI/CBI
|
1854 |
|
|
iowe_int <= '1' when ((idc_out_cml_3 or sbi_st_cml_3 or cbi_st_cml_3) or
|
1855 |
|
|
((st_st_cml_3 or sts_st_cml_3) and io_file_adr_space_cml_3))='1' else '0'; -- OUT/SBI/CBI + !! ST/STS/STD
|
1856 |
|
|
|
1857 |
|
|
|
1858 |
|
|
-- SynEDA CoreMultiplier
|
1859 |
|
|
-- assignment(s): adr_int
|
1860 |
|
|
-- replace(s): sbi_st, cbi_st, ramadr_int, cbi_sbi_io_adr_tmp, idc_out
|
1861 |
|
|
|
1862 |
|
|
-- adr[5..0] BUS MULTIPLEXER
|
1863 |
|
|
adr_int <= dex_adr6port when (idc_in or idc_out_cml_1) = '1' else -- IN/OUT INSTRUCTIONS
|
1864 |
|
|
'0'&dex_adr5port when (idc_cbi or idc_sbi or idc_sbic or idc_sbis) ='1' else -- CBI/SBI (READ PHASE) + SBIS/SBIC
|
1865 |
|
|
'0'&cbi_sbi_io_adr_tmp_cml_1 when (cbi_st_cml_1 or sbi_st_cml_1)='1' else -- CBI/SBI (WRITE PHASE)
|
1866 |
|
|
ramadr_int_cml_1(6)&ramadr_int_cml_1(4 downto 0); -- LD/LDS/LDD/ST/STS/STD
|
1867 |
|
|
|
1868 |
|
|
-- ramre LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS))
|
1869 |
|
|
--ramre_int <= not(reg_file_adr_space or io_file_adr_space) and
|
1870 |
|
|
-- (ld_st or lds_st2 or pop_st or -- LD/LDD/LDS/POP/
|
1871 |
|
|
-- ret_st1 or ret_st2 or reti_st1 or reti_st2); -- RET/RETI
|
1872 |
|
|
|
1873 |
|
|
-- SynEDA CoreMultiplier
|
1874 |
|
|
-- assignment(s): ramre_int
|
1875 |
|
|
-- replace(s): cpuwait, ramadr_reg_in, ret_st2, reti_st2, lds_st, ld_st, pop_st, ramre_int, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_ret, idc_reti
|
1876 |
|
|
|
1877 |
|
|
DataMemoryRead:process(cp2,ireset)
|
1878 |
|
|
begin
|
1879 |
|
|
if ireset='0' then -- Reset
|
1880 |
|
|
ramre_int <= '0';
|
1881 |
|
|
elsif (cp2='1' and cp2'event) then ramre_int <= ramre_int_cml_3; -- Clock
|
1882 |
|
|
if (cp2en='1') then -- Clock enable
|
1883 |
|
|
case ramre_int_cml_3 is
|
1884 |
|
|
when '0' =>
|
1885 |
|
|
if(ramadr_reg_in_cml_3(15 downto 5)/=const_ram_to_io_a and
|
1886 |
|
|
ramadr_reg_in_cml_3(15 downto 5)/=const_ram_to_io_b and
|
1887 |
|
|
ramadr_reg_in_cml_3(15 downto 5)/=const_ram_to_reg and
|
1888 |
|
|
(idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ldd_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_z_cml_3 or -- LD/LDD instruction
|
1889 |
|
|
idc_lds_cml_3 or -- LDS instruction(two cycle execution)
|
1890 |
|
|
idc_pop_cml_3 or -- POP instruction
|
1891 |
|
|
idc_ret_cml_3 or -- RET instruction
|
1892 |
|
|
idc_reti_cml_3)='1') -- RETI instruction
|
1893 |
|
|
then ramre_int <='1';
|
1894 |
|
|
end if;
|
1895 |
|
|
when '1' =>
|
1896 |
|
|
if ((ld_st_cml_3 or lds_st_cml_3 or pop_st_cml_3 or ret_st2_cml_3 or reti_st2_cml_3)and not cpuwait_cml_3)='1' then
|
1897 |
|
|
ramre_int <='0';
|
1898 |
|
|
end if;
|
1899 |
|
|
when others => null;
|
1900 |
|
|
end case;
|
1901 |
|
|
end if;
|
1902 |
|
|
end if;
|
1903 |
|
|
end process;
|
1904 |
|
|
|
1905 |
|
|
-- ramwe LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS))
|
1906 |
|
|
--ramwe_int <= not(reg_file_adr_space or io_file_adr_space) and
|
1907 |
|
|
-- (st_st or sts_st2 or push_st or rcall_st1 or rcall_st2 or -- ST/STD/STS/PUSH/RCALL
|
1908 |
|
|
-- icall_st1 or icall_st2 or -- ICALL
|
1909 |
|
|
-- call_st2 or call_st3 or -- CALL
|
1910 |
|
|
-- irq_st2 or irq_st3); -- INTERRUPT
|
1911 |
|
|
|
1912 |
|
|
-- SynEDA CoreMultiplier
|
1913 |
|
|
-- assignment(s): ramwe_int
|
1914 |
|
|
-- replace(s): cpuwait, ramadr_reg_in, irq_st1, irq_st3, call_st1, call_st3, rcall_st2, icall_st2, sts_st, st_st, push_st, ramwe_int, idc_icall, idc_push, idc_rcall, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
|
1915 |
|
|
|
1916 |
|
|
DataMemoryWrite:process(cp2,ireset)
|
1917 |
|
|
begin
|
1918 |
|
|
if ireset='0' then -- Reset
|
1919 |
|
|
ramwe_int <= '0';
|
1920 |
|
|
elsif (cp2='1' and cp2'event) then ramwe_int <= ramwe_int_cml_3; -- Clock
|
1921 |
|
|
if (cp2en='1') then -- Clock enable
|
1922 |
|
|
case ramwe_int_cml_3 is
|
1923 |
|
|
when '0' =>
|
1924 |
|
|
if(ramadr_reg_in_cml_3(15 downto 5)/=const_ram_to_io_a and
|
1925 |
|
|
ramadr_reg_in_cml_3(15 downto 5)/=const_ram_to_io_b and
|
1926 |
|
|
ramadr_reg_in_cml_3(15 downto 5)/=const_ram_to_reg and
|
1927 |
|
|
(idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3 or -- ST/STD instruction
|
1928 |
|
|
idc_sts_cml_3 or -- STS instruction (two cycle execution)
|
1929 |
|
|
idc_push_cml_3 or -- PUSH instruction
|
1930 |
|
|
idc_rcall_cml_3 or -- RCALL instruction
|
1931 |
|
|
idc_icall_cml_3 or -- ICALL instruction
|
1932 |
|
|
call_st1_cml_3 or -- CALL instruction
|
1933 |
|
|
irq_st1_cml_3)='1') -- Interrupt
|
1934 |
|
|
then ramwe_int <='1';
|
1935 |
|
|
end if;
|
1936 |
|
|
when '1' =>
|
1937 |
|
|
if ((st_st_cml_3 or sts_st_cml_3 or push_st_cml_3 or rcall_st2_cml_3 or
|
1938 |
|
|
icall_st2_cml_3 or call_st3_cml_3 or irq_st3_cml_3)and not cpuwait_cml_3)='1' then ramwe_int <='0';
|
1939 |
|
|
end if;
|
1940 |
|
|
when others => null;
|
1941 |
|
|
end case;
|
1942 |
|
|
end if;
|
1943 |
|
|
end if;
|
1944 |
|
|
end process;
|
1945 |
|
|
|
1946 |
|
|
-- DBUSOUT MULTIPLEXER
|
1947 |
|
|
--dbusout_mux_logic: for i in dbusout_int'range generate
|
1948 |
|
|
--dbusout_int(i)<= (reg_rd_out(i) and (idc_push or idc_sts or
|
1949 |
|
|
-- (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
1950 |
|
|
-- (gp_reg_tmp(i) and (st_st or sts_st))or -- NEW
|
1951 |
|
|
-- (bitpr_io_out(i) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS
|
1952 |
|
|
-- (program_counter(i) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC (program_counter_high_fr(i) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC
|
1953 |
|
|
-- (pc_for_interrupt(i) and irq_st1) or
|
1954 |
|
|
-- (pc_for_interrupt(8) and irq_st2) or
|
1955 |
|
|
-- (reg_rd_out(i) and idc_out); -- OUT
|
1956 |
|
|
--end generate;
|
1957 |
|
|
|
1958 |
|
|
dbusout_int(0)<= (reg_rd_out_cml_3(0) and (idc_push_cml_3 or idc_sts_cml_3 or
|
1959 |
|
|
(idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
1960 |
|
|
(gp_reg_tmp_cml_3(0) and (st_st_cml_3 or sts_st_cml_3))or -- NEW
|
1961 |
|
|
(bitpr_io_out_cml_3(0) and (cbi_st_cml_3 or sbi_st_cml_3))or -- CBI/SBI INSTRUCTIONS
|
1962 |
|
|
(program_counter_cml_3(0) and (idc_rcall_cml_3 or idc_icall_cml_3 or call_st1_cml_3))or -- LOW PART OF PC
|
1963 |
|
|
(program_counter_high_fr_cml_3(0) and (rcall_st1_cml_3 or icall_st1_cml_3 or call_st2_cml_3))or -- HIGH PART OF PC
|
1964 |
|
|
(pc_for_interrupt_cml_3(0) and irq_st1_cml_3) or
|
1965 |
|
|
(pc_for_interrupt_cml_3(8) and irq_st2_cml_3) or
|
1966 |
|
|
(reg_rd_out_cml_3(0) and idc_out_cml_3); -- OUT
|
1967 |
|
|
|
1968 |
|
|
dbusout_int(1)<= (reg_rd_out_cml_3(1) and (idc_push_cml_3 or idc_sts_cml_3 or
|
1969 |
|
|
(idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
1970 |
|
|
(gp_reg_tmp_cml_3(1) and (st_st_cml_3 or sts_st_cml_3))or -- NEW
|
1971 |
|
|
(bitpr_io_out_cml_3(1) and (cbi_st_cml_3 or sbi_st_cml_3))or -- CBI/SBI INSTRUCTIONS
|
1972 |
|
|
(program_counter_cml_3(1) and (idc_rcall_cml_3 or idc_icall_cml_3 or call_st1_cml_3))or -- LOW PART OF PC
|
1973 |
|
|
(program_counter_high_fr_cml_3(1) and (rcall_st1_cml_3 or icall_st1_cml_3 or call_st2_cml_3))or -- HIGH PART OF PC
|
1974 |
|
|
(pc_for_interrupt_cml_3(1) and irq_st1_cml_3) or
|
1975 |
|
|
(pc_for_interrupt_cml_3(9) and irq_st2_cml_3) or
|
1976 |
|
|
(reg_rd_out_cml_3(1) and idc_out_cml_3); -- OUT
|
1977 |
|
|
|
1978 |
|
|
dbusout_int(2)<= (reg_rd_out_cml_3(2) and (idc_push_cml_3 or idc_sts_cml_3 or
|
1979 |
|
|
(idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
1980 |
|
|
(gp_reg_tmp_cml_3(2) and (st_st_cml_3 or sts_st_cml_3))or -- NEW
|
1981 |
|
|
(bitpr_io_out_cml_3(2) and (cbi_st_cml_3 or sbi_st_cml_3))or -- CBI/SBI INSTRUCTIONS
|
1982 |
|
|
(program_counter_cml_3(2) and (idc_rcall_cml_3 or idc_icall_cml_3 or call_st1_cml_3))or -- LOW PART OF PC
|
1983 |
|
|
(program_counter_high_fr_cml_3(2) and (rcall_st1_cml_3 or icall_st1_cml_3 or call_st2_cml_3))or -- HIGH PART OF PC
|
1984 |
|
|
(pc_for_interrupt_cml_3(2) and irq_st1_cml_3) or
|
1985 |
|
|
(pc_for_interrupt_cml_3(10) and irq_st2_cml_3) or
|
1986 |
|
|
(reg_rd_out_cml_3(2) and idc_out_cml_3); -- OUT
|
1987 |
|
|
|
1988 |
|
|
dbusout_int(3)<= (reg_rd_out_cml_3(3) and (idc_push_cml_3 or idc_sts_cml_3 or
|
1989 |
|
|
(idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
1990 |
|
|
(gp_reg_tmp_cml_3(3) and (st_st_cml_3 or sts_st_cml_3))or -- NEW
|
1991 |
|
|
(bitpr_io_out_cml_3(3) and (cbi_st_cml_3 or sbi_st_cml_3))or -- CBI/SBI INSTRUCTIONS
|
1992 |
|
|
(program_counter_cml_3(3) and (idc_rcall_cml_3 or idc_icall_cml_3 or call_st1_cml_3))or -- LOW PART OF PC
|
1993 |
|
|
(program_counter_high_fr_cml_3(3) and (rcall_st1_cml_3 or icall_st1_cml_3 or call_st2_cml_3))or -- HIGH PART OF PC
|
1994 |
|
|
(pc_for_interrupt_cml_3(3) and irq_st1_cml_3) or
|
1995 |
|
|
(pc_for_interrupt_cml_3(11) and irq_st2_cml_3) or
|
1996 |
|
|
(reg_rd_out_cml_3(3) and idc_out_cml_3); -- OUT
|
1997 |
|
|
|
1998 |
|
|
dbusout_int(4)<= (reg_rd_out_cml_3(4) and (idc_push_cml_3 or idc_sts_cml_3 or
|
1999 |
|
|
(idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
2000 |
|
|
(gp_reg_tmp_cml_3(4) and (st_st_cml_3 or sts_st_cml_3))or -- NEW
|
2001 |
|
|
(bitpr_io_out_cml_3(4) and (cbi_st_cml_3 or sbi_st_cml_3))or -- CBI/SBI INSTRUCTIONS
|
2002 |
|
|
(program_counter_cml_3(4) and (idc_rcall_cml_3 or idc_icall_cml_3 or call_st1_cml_3))or -- LOW PART OF PC
|
2003 |
|
|
(program_counter_high_fr_cml_3(4) and (rcall_st1_cml_3 or icall_st1_cml_3 or call_st2_cml_3))or -- HIGH PART OF PC
|
2004 |
|
|
(pc_for_interrupt_cml_3(4) and irq_st1_cml_3) or
|
2005 |
|
|
(pc_for_interrupt_cml_3(12) and irq_st2_cml_3) or
|
2006 |
|
|
(reg_rd_out_cml_3(4) and idc_out_cml_3); -- OUT
|
2007 |
|
|
|
2008 |
|
|
dbusout_int(5)<= (reg_rd_out_cml_3(5) and (idc_push_cml_3 or idc_sts_cml_3 or
|
2009 |
|
|
(idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
2010 |
|
|
(gp_reg_tmp_cml_3(5) and (st_st_cml_3 or sts_st_cml_3))or -- NEW
|
2011 |
|
|
(bitpr_io_out_cml_3(5) and (cbi_st_cml_3 or sbi_st_cml_3))or -- CBI/SBI INSTRUCTIONS
|
2012 |
|
|
(program_counter_cml_3(5) and (idc_rcall_cml_3 or idc_icall_cml_3 or call_st1_cml_3))or -- LOW PART OF PC
|
2013 |
|
|
(program_counter_high_fr_cml_3(5) and (rcall_st1_cml_3 or icall_st1_cml_3 or call_st2_cml_3))or -- HIGH PART OF PC
|
2014 |
|
|
(pc_for_interrupt_cml_3(5) and irq_st1_cml_3) or
|
2015 |
|
|
(pc_for_interrupt_cml_3(13) and irq_st2_cml_3) or
|
2016 |
|
|
(reg_rd_out_cml_3(5) and idc_out_cml_3); -- OUT
|
2017 |
|
|
|
2018 |
|
|
dbusout_int(6)<= (reg_rd_out_cml_3(6) and (idc_push_cml_3 or idc_sts_cml_3 or
|
2019 |
|
|
(idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
2020 |
|
|
(gp_reg_tmp_cml_3(6) and (st_st_cml_3 or sts_st_cml_3))or -- NEW
|
2021 |
|
|
(bitpr_io_out_cml_3(6) and (cbi_st_cml_3 or sbi_st_cml_3))or -- CBI/SBI INSTRUCTIONS
|
2022 |
|
|
(program_counter_cml_3(6) and (idc_rcall_cml_3 or idc_icall_cml_3 or call_st1_cml_3))or -- LOW PART OF PC
|
2023 |
|
|
(program_counter_high_fr_cml_3(6) and (rcall_st1_cml_3 or icall_st1_cml_3 or call_st2_cml_3))or -- HIGH PART OF PC
|
2024 |
|
|
(pc_for_interrupt_cml_3(6) and irq_st1_cml_3) or
|
2025 |
|
|
(pc_for_interrupt_cml_3(14) and irq_st2_cml_3) or
|
2026 |
|
|
(reg_rd_out_cml_3(6) and idc_out_cml_3); -- OUT
|
2027 |
|
|
|
2028 |
|
|
-- SynEDA CoreMultiplier
|
2029 |
|
|
-- assignment(s): dbusout_int
|
2030 |
|
|
-- replace(s): reg_rd_out, bitpr_io_out, program_counter, program_counter_high_fr, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, sts_st, st_st, sbi_st, cbi_st, pc_for_interrupt, gp_reg_tmp, idc_icall, idc_out, idc_push, idc_rcall, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
|
2031 |
|
|
|
2032 |
|
|
dbusout_int(7)<= (reg_rd_out_cml_3(7) and (idc_push_cml_3 or idc_sts_cml_3 or
|
2033 |
|
|
(idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
2034 |
|
|
(gp_reg_tmp_cml_3(7) and (st_st_cml_3 or sts_st_cml_3))or -- NEW
|
2035 |
|
|
(bitpr_io_out_cml_3(7) and (cbi_st_cml_3 or sbi_st_cml_3))or -- CBI/SBI INSTRUCTIONS
|
2036 |
|
|
(program_counter_cml_3(7) and (idc_rcall_cml_3 or idc_icall_cml_3 or call_st1_cml_3))or -- LOW PART OF PC
|
2037 |
|
|
(program_counter_high_fr_cml_3(7) and (rcall_st1_cml_3 or icall_st1_cml_3 or call_st2_cml_3))or -- HIGH PART OF PC
|
2038 |
|
|
(pc_for_interrupt_cml_3(7) and irq_st1_cml_3) or
|
2039 |
|
|
(pc_for_interrupt_cml_3(15) and irq_st2_cml_3) or
|
2040 |
|
|
(reg_rd_out_cml_3(7) and idc_out_cml_3); -- OUT
|
2041 |
|
|
|
2042 |
|
|
dbusout_int_route <= dbusout_int;
|
2043 |
|
|
|
2044 |
|
|
dbusout(0)<= (reg_rd_out_int(0) and (idc_push or idc_sts or
|
2045 |
|
|
(idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
2046 |
|
|
(gp_reg_tmp(0) and (st_st or sts_st))or -- NEW
|
2047 |
|
|
(bitpr_io_out(0) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS
|
2048 |
|
|
(program_counter(0) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC
|
2049 |
|
|
(program_counter_high_fr(0) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC
|
2050 |
|
|
(pc_for_interrupt(0) and irq_st1) or
|
2051 |
|
|
(pc_for_interrupt(8) and irq_st2) or
|
2052 |
|
|
(reg_rd_out_int(0) and idc_out); -- OUT
|
2053 |
|
|
|
2054 |
|
|
dbusout(1)<= (reg_rd_out_int(1) and (idc_push or idc_sts or
|
2055 |
|
|
(idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
2056 |
|
|
(gp_reg_tmp(1) and (st_st or sts_st))or -- NEW
|
2057 |
|
|
(bitpr_io_out(1) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS
|
2058 |
|
|
(program_counter(1) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC
|
2059 |
|
|
(program_counter_high_fr(1) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC
|
2060 |
|
|
(pc_for_interrupt(1) and irq_st1) or
|
2061 |
|
|
(pc_for_interrupt(9) and irq_st2) or
|
2062 |
|
|
(reg_rd_out_int(1) and idc_out); -- OUT
|
2063 |
|
|
|
2064 |
|
|
dbusout(2)<= (reg_rd_out_int(2) and (idc_push or idc_sts or
|
2065 |
|
|
(idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
2066 |
|
|
(gp_reg_tmp(2) and (st_st or sts_st))or -- NEW
|
2067 |
|
|
(bitpr_io_out(2) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS
|
2068 |
|
|
(program_counter(2) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC
|
2069 |
|
|
(program_counter_high_fr(2) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC
|
2070 |
|
|
(pc_for_interrupt(2) and irq_st1) or
|
2071 |
|
|
(pc_for_interrupt(10) and irq_st2) or
|
2072 |
|
|
(reg_rd_out_int(2) and idc_out); -- OUT
|
2073 |
|
|
|
2074 |
|
|
dbusout(3)<= (reg_rd_out_int(3) and (idc_push or idc_sts or
|
2075 |
|
|
(idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
2076 |
|
|
(gp_reg_tmp(3) and (st_st or sts_st))or -- NEW
|
2077 |
|
|
(bitpr_io_out(3) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS
|
2078 |
|
|
(program_counter(3) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC
|
2079 |
|
|
(program_counter_high_fr(3) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC
|
2080 |
|
|
(pc_for_interrupt(3) and irq_st1) or
|
2081 |
|
|
(pc_for_interrupt(11) and irq_st2) or
|
2082 |
|
|
(reg_rd_out_int(3) and idc_out); -- OUT
|
2083 |
|
|
|
2084 |
|
|
dbusout(4)<= (reg_rd_out_int(4) and (idc_push or idc_sts or
|
2085 |
|
|
(idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
2086 |
|
|
(gp_reg_tmp(4) and (st_st or sts_st))or -- NEW
|
2087 |
|
|
(bitpr_io_out(4) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS
|
2088 |
|
|
(program_counter(4) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC
|
2089 |
|
|
(program_counter_high_fr(4) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC
|
2090 |
|
|
(pc_for_interrupt(4) and irq_st1) or
|
2091 |
|
|
(pc_for_interrupt(12) and irq_st2) or
|
2092 |
|
|
(reg_rd_out_int(4) and idc_out); -- OUT
|
2093 |
|
|
|
2094 |
|
|
dbusout(5)<= (reg_rd_out_int(5) and (idc_push or idc_sts or
|
2095 |
|
|
(idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
2096 |
|
|
(gp_reg_tmp(5) and (st_st or sts_st))or -- NEW
|
2097 |
|
|
(bitpr_io_out(5) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS
|
2098 |
|
|
(program_counter(5) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC
|
2099 |
|
|
(program_counter_high_fr(5) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC
|
2100 |
|
|
(pc_for_interrupt(5) and irq_st1) or
|
2101 |
|
|
(pc_for_interrupt(13) and irq_st2) or
|
2102 |
|
|
(reg_rd_out_int(5) and idc_out); -- OUT
|
2103 |
|
|
|
2104 |
|
|
dbusout(6)<= (reg_rd_out_int(6) and (idc_push or idc_sts or
|
2105 |
|
|
(idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
2106 |
|
|
(gp_reg_tmp(6) and (st_st or sts_st))or -- NEW
|
2107 |
|
|
(bitpr_io_out(6) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS
|
2108 |
|
|
(program_counter(6) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC
|
2109 |
|
|
(program_counter_high_fr(6) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC
|
2110 |
|
|
(pc_for_interrupt(6) and irq_st1) or
|
2111 |
|
|
(pc_for_interrupt(14) and irq_st2) or
|
2112 |
|
|
(reg_rd_out_int(6) and idc_out); -- OUT
|
2113 |
|
|
|
2114 |
|
|
dbusout(7)<= (reg_rd_out_int(7) and (idc_push or idc_sts or
|
2115 |
|
|
(idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or -- PUSH/ST/STD/STS INSTRUCTIONS
|
2116 |
|
|
(gp_reg_tmp(7) and (st_st or sts_st))or -- NEW
|
2117 |
|
|
(bitpr_io_out(7) and (cbi_st or sbi_st))or -- CBI/SBI INSTRUCTIONS
|
2118 |
|
|
(program_counter(7) and (idc_rcall or idc_icall or call_st1))or -- LOW PART OF PC
|
2119 |
|
|
(program_counter_high_fr(7) and (rcall_st1 or icall_st1 or call_st2))or -- HIGH PART OF PC
|
2120 |
|
|
(pc_for_interrupt(7) and irq_st1) or
|
2121 |
|
|
(pc_for_interrupt(15) and irq_st2) or
|
2122 |
|
|
(reg_rd_out_int(7) and idc_out); -- OUT
|
2123 |
|
|
|
2124 |
|
|
|
2125 |
|
|
-- ALU CONNECTION
|
2126 |
|
|
|
2127 |
|
|
-- SynEDA CoreMultiplier
|
2128 |
|
|
-- assignment(s): alu_data_r_in
|
2129 |
|
|
-- replace(s): reg_rr_out, adiw_st, sbiw_st, dex_dat8_immed, dex_dat6_immed, idc_adiw, idc_andi, idc_cpi, idc_ori, idc_sbci, idc_sbiw, idc_subi
|
2130 |
|
|
|
2131 |
|
|
-- ALU Rr INPUT MUX
|
2132 |
|
|
alu_data_r_in_cml_out <= dex_dat8_immed_cml_1 when (idc_subi_cml_1 or idc_sbci_cml_1 or idc_andi_cml_1 or idc_ori_cml_1 or idc_cpi_cml_1)='1' else
|
2133 |
|
|
"00"&dex_dat6_immed_cml_1 when (idc_adiw_cml_1 or idc_sbiw_cml_1) ='1' else
|
2134 |
|
|
"00000000" when (adiw_st_cml_1 or sbiw_st_cml_1) ='1' else
|
2135 |
|
|
reg_rr_out_cml_1;
|
2136 |
|
|
|
2137 |
|
|
|
2138 |
|
|
-- SynEDA CoreMultiplier
|
2139 |
|
|
-- assignment(s): gp_reg_tmp
|
2140 |
|
|
-- replace(s): reg_rd_out, gp_reg_tmp, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
|
2141 |
|
|
|
2142 |
|
|
-- gp_reg_tmp STORES TEMPREOARY THE VALUE OF SOURCE REGISTER DURING ST/STD/STS INSTRUCTION
|
2143 |
|
|
gp_registers_trig:process(cp2,ireset)
|
2144 |
|
|
begin
|
2145 |
|
|
if (ireset='0') then
|
2146 |
|
|
gp_reg_tmp <= (others=>'0');
|
2147 |
|
|
elsif (cp2='1' and cp2'event) then gp_reg_tmp <= gp_reg_tmp_cml_3;
|
2148 |
|
|
if (cp2en='1') then -- Clock enable
|
2149 |
|
|
-- if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or sts_st1)='1' then -- CLOCK ENABLE
|
2150 |
|
|
if ((idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3) or idc_sts_cml_3)='1' then -- CLOCK ENABLE
|
2151 |
|
|
gp_reg_tmp <= reg_rd_out_cml_3;
|
2152 |
|
|
end if;
|
2153 |
|
|
end if;
|
2154 |
|
|
end if;
|
2155 |
|
|
end process;
|
2156 |
|
|
|
2157 |
|
|
-- **********************************************************************************************************
|
2158 |
|
|
|
2159 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
2160 |
|
|
-- +++++++++++++++++++++++++++++++++++++++ PROGRAM COUNTER ++++++++++++++++++++++++++++++++++++++++++++++++++
|
2161 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
2162 |
|
|
|
2163 |
|
|
-- SynEDA CoreMultiplier
|
2164 |
|
|
-- assignment(s): program_counter_high_fr
|
2165 |
|
|
-- replace(s): program_counter, program_counter_high_fr, irq_st1, call_st1, idc_icall, idc_rcall
|
2166 |
|
|
|
2167 |
|
|
program_counter_high_store:process(cp2,ireset)
|
2168 |
|
|
begin
|
2169 |
|
|
if ireset='0' then -- RESET
|
2170 |
|
|
program_counter_high_fr <=(others => '0');
|
2171 |
|
|
elsif (cp2='1' and cp2'event) then program_counter_high_fr <= program_counter_high_fr_cml_3; -- CLOCK
|
2172 |
|
|
if (cp2en='1') then -- Clock enable
|
2173 |
|
|
if (idc_rcall_cml_3 or idc_icall_cml_3 or call_st1_cml_3 or irq_st1_cml_3) ='1' then
|
2174 |
|
|
program_counter_high_fr <= program_counter_cml_3(15 downto 8); -- STORE HIGH BYTE OF THE PROGRAMM COUNTER FOR RCALL/ICALL/CALL INSTRUCTIONS AND INTERRUPTS
|
2175 |
|
|
end if;
|
2176 |
|
|
end if;
|
2177 |
|
|
end if;
|
2178 |
|
|
end process;
|
2179 |
|
|
|
2180 |
|
|
|
2181 |
|
|
-- SynEDA CoreMultiplier
|
2182 |
|
|
-- assignment(s): program_counter_tmp
|
2183 |
|
|
-- replace(s): program_counter_tmp, program_counter
|
2184 |
|
|
|
2185 |
|
|
program_counter_for_lpm_elpm:process(cp2,ireset)
|
2186 |
|
|
begin
|
2187 |
|
|
if ireset='0' then -- RESET
|
2188 |
|
|
program_counter_tmp<=(others => '0');
|
2189 |
|
|
elsif (cp2='1' and cp2'event) then program_counter_tmp <= program_counter_tmp_cml_3; -- CLOCK
|
2190 |
|
|
if (cp2en='1') then -- Clock enable
|
2191 |
|
|
if (idc_lpm or idc_elpm) ='1' then
|
2192 |
|
|
program_counter_tmp <= program_counter_cml_3;
|
2193 |
|
|
end if;
|
2194 |
|
|
end if;
|
2195 |
|
|
end if;
|
2196 |
|
|
end process;
|
2197 |
|
|
|
2198 |
|
|
-- SynEDA CoreMultiplier
|
2199 |
|
|
-- assignment(s): pa15_pm
|
2200 |
|
|
-- replace(s): rampz_out
|
2201 |
|
|
|
2202 |
|
|
pa15_pm <= rampz_out_cml_3(0) and idc_elpm; -- '0' WHEN LPM INSTRUCTIONS RAMPZ(0) WHEN ELPM INSTRUCTION
|
2203 |
|
|
|
2204 |
|
|
-- OFFSET FOR BRBC/BRBS INSTRUCTIONS +63/-64
|
2205 |
|
|
offset_brbx <= "0000000000"&dex_brxx_offset(5 downto 0) when (dex_brxx_offset(6)='0') else -- +
|
2206 |
|
|
"1111111111"&dex_brxx_offset(5 downto 0); -- -
|
2207 |
|
|
|
2208 |
|
|
-- OFFSET FOR RJMP/RCALL INSTRUCTIONS +2047/-2048
|
2209 |
|
|
offset_rxx <= "00000"&dex_adr12mem_s(10 downto 0) when (dex_adr12mem_s(11)='0') else -- +
|
2210 |
|
|
"11111"&dex_adr12mem_s(10 downto 0); -- -
|
2211 |
|
|
|
2212 |
|
|
program_counter <= pc_high&pc_low;
|
2213 |
|
|
|
2214 |
|
|
-- SynEDA CoreMultiplier
|
2215 |
|
|
-- assignment(s): program_counter_in
|
2216 |
|
|
-- replace(s): dbusin, irqackad_int, program_counter_tmp, program_counter, irq_st1, call_st1, jmp_st1, ret_st1, ret_st2, reti_st1, reti_st2, lpm_st1, instruction_reg, idc_icall, idc_rcall
|
2217 |
|
|
|
2218 |
|
|
program_counter_in <= program_counter_cml_3 + offset_brbx when ((idc_brbc or idc_brbs) and bit_test_op_out) ='1'else -- BRBC/BRBS
|
2219 |
|
|
program_counter_cml_3 + offset_rxx when (idc_rjmp or idc_rcall_cml_3)='1'else -- RJMP/RCALL
|
2220 |
|
|
reg_z_out when (idc_ijmp or idc_icall_cml_3)='1'else -- IJMP/ICALL
|
2221 |
|
|
pa15_pm®_z_out(15 downto 1) when (idc_lpm or idc_elpm) ='1'else -- LPM/ELPM
|
2222 |
|
|
instruction_reg_cml_3 when (jmp_st1_cml_3 or call_st1_cml_3)='1'else -- JMP/CALL
|
2223 |
|
|
"0000000000"&irqackad_int_cml_3&'0' when irq_st1_cml_3 ='1' else -- INTERRUPT
|
2224 |
|
|
dbusin_cml_3&"00000000" when (ret_st1_cml_3 or reti_st1_cml_3)='1' else -- RET/RETI -> PC HIGH BYTE
|
2225 |
|
|
"00000000"&dbusin_cml_3 when (ret_st2_cml_3 or reti_st2_cml_3)='1' else -- RET/RETI -> PC LOW BYTE
|
2226 |
|
|
program_counter_tmp_cml_3 when (lpm_st1_cml_3)='1' -- AFTER LPM/ELPM INSTRUCTION
|
2227 |
|
|
else program_counter_cml_3+1; -- THE MOST USUAL CASE
|
2228 |
|
|
|
2229 |
|
|
|
2230 |
|
|
|
2231 |
|
|
-- SynEDA CoreMultiplier
|
2232 |
|
|
-- assignment(s): pc_low_en
|
2233 |
|
|
-- replace(s): cpuwait, irq_st2, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, sts_st, lds_st, idc_adiw, idc_cbi, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_pop, idc_push, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
|
2234 |
|
|
|
2235 |
|
|
pc_low_en <= not (idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_y_cml_3 or idc_ldd_z_cml_3 or
|
2236 |
|
|
idc_st_x_cml_3 or idc_st_y_cml_3 or idc_st_z_cml_3 or idc_std_y_cml_3 or idc_std_z_cml_3 or
|
2237 |
|
|
((sts_st_cml_3 or lds_st_cml_3) and cpuwait_cml_3)or
|
2238 |
|
|
idc_adiw_cml_3 or idc_sbiw_cml_3 or
|
2239 |
|
|
idc_push_cml_3 or idc_pop_cml_3 or
|
2240 |
|
|
idc_cbi_cml_3 or idc_sbi_cml_3 or
|
2241 |
|
|
rcall_st1_cml_3 or icall_st1_cml_3 or call_st2_cml_3 or irq_st2_cml_3 or cpuwait_cml_3 or
|
2242 |
|
|
ret_st1_cml_3 or reti_st1_cml_3);
|
2243 |
|
|
|
2244 |
|
|
|
2245 |
|
|
-- SynEDA CoreMultiplier
|
2246 |
|
|
-- assignment(s): pc_high_en
|
2247 |
|
|
-- replace(s): cpuwait, irq_st2, call_st2, rcall_st1, icall_st1, ret_st2, reti_st2, sts_st, lds_st, idc_adiw, idc_cbi, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_pop, idc_push, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
|
2248 |
|
|
|
2249 |
|
|
pc_high_en <= not (idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_y_cml_3 or idc_ldd_z_cml_3 or
|
2250 |
|
|
idc_st_x_cml_3 or idc_st_y_cml_3 or idc_st_z_cml_3 or idc_std_y_cml_3 or idc_std_z_cml_3 or
|
2251 |
|
|
((sts_st_cml_3 or lds_st_cml_3) and cpuwait_cml_3) or
|
2252 |
|
|
idc_adiw_cml_3 or idc_sbiw_cml_3 or
|
2253 |
|
|
idc_push_cml_3 or idc_pop_cml_3 or
|
2254 |
|
|
idc_cbi_cml_3 or idc_sbi_cml_3 or
|
2255 |
|
|
rcall_st1_cml_3 or icall_st1_cml_3 or call_st2_cml_3 or irq_st2_cml_3 or cpuwait_cml_3 or
|
2256 |
|
|
ret_st2_cml_3 or reti_st2_cml_3);
|
2257 |
|
|
|
2258 |
|
|
-- SynEDA CoreMultiplier
|
2259 |
|
|
-- assignment(s): pc_low
|
2260 |
|
|
-- replace(s): pc_low
|
2261 |
|
|
|
2262 |
|
|
program_counter_low:process(cp2,ireset)
|
2263 |
|
|
begin
|
2264 |
|
|
if ireset='0' then -- RESET
|
2265 |
|
|
pc_low<=(others => '0');
|
2266 |
|
|
elsif (cp2='1' and cp2'event) then pc_low <= pc_low_cml_3; -- CLOCK
|
2267 |
|
|
if (cp2en='1') then -- Clock enable
|
2268 |
|
|
if pc_low_en ='1' then
|
2269 |
|
|
pc_low <= program_counter_in(7 downto 0);
|
2270 |
|
|
end if;
|
2271 |
|
|
end if;
|
2272 |
|
|
end if;
|
2273 |
|
|
end process;
|
2274 |
|
|
|
2275 |
|
|
-- SynEDA CoreMultiplier
|
2276 |
|
|
-- assignment(s): pc_high
|
2277 |
|
|
-- replace(s): pc_high
|
2278 |
|
|
|
2279 |
|
|
program_counter_high:process(cp2,ireset)
|
2280 |
|
|
begin
|
2281 |
|
|
if ireset='0' then -- RESET
|
2282 |
|
|
pc_high<=(others => '0');
|
2283 |
|
|
elsif (cp2='1' and cp2'event) then pc_high <= pc_high_cml_3; -- CLOCK
|
2284 |
|
|
if (cp2en='1') then -- Clock enable
|
2285 |
|
|
if pc_high_en ='1' then
|
2286 |
|
|
pc_high <= program_counter_in(15 downto 8);
|
2287 |
|
|
end if;
|
2288 |
|
|
end if;
|
2289 |
|
|
end if;
|
2290 |
|
|
end process;
|
2291 |
|
|
|
2292 |
|
|
pc <= program_counter;
|
2293 |
|
|
|
2294 |
|
|
|
2295 |
|
|
-- SynEDA CoreMultiplier
|
2296 |
|
|
-- assignment(s): pc_for_interrupt
|
2297 |
|
|
-- replace(s): program_counter, pc_for_interrupt
|
2298 |
|
|
|
2299 |
|
|
program_counter_for_interrupt:process(cp2,ireset)
|
2300 |
|
|
begin
|
2301 |
|
|
if ireset='0' then -- RESET
|
2302 |
|
|
pc_for_interrupt <=(others => '0');
|
2303 |
|
|
elsif (cp2='1' and cp2'event) then pc_for_interrupt <= pc_for_interrupt_cml_3; -- CLOCK
|
2304 |
|
|
if (cp2en='1') then -- Clock enable
|
2305 |
|
|
if irq_start ='1' then
|
2306 |
|
|
pc_for_interrupt <= program_counter_cml_3;
|
2307 |
|
|
end if;
|
2308 |
|
|
end if;
|
2309 |
|
|
end if;
|
2310 |
|
|
end process;
|
2311 |
|
|
|
2312 |
|
|
-- END OF PROGRAM COUNTER
|
2313 |
|
|
|
2314 |
|
|
-- STATE MACHINES
|
2315 |
|
|
|
2316 |
|
|
-- SynEDA CoreMultiplier
|
2317 |
|
|
-- assignment(s): skip_inst_start
|
2318 |
|
|
-- replace(s): idc_cpse, idc_sbic, idc_sbis, idc_sbrc, idc_sbrs
|
2319 |
|
|
|
2320 |
|
|
skip_inst_start <= ((idc_sbrc_cml_3 or idc_sbrs_cml_3 or idc_sbic_cml_3 or idc_sbis_cml_3) and bit_test_op_out)or
|
2321 |
|
|
(idc_cpse_cml_3 and alu_z_flag_out);
|
2322 |
|
|
|
2323 |
|
|
-- SynEDA CoreMultiplier
|
2324 |
|
|
-- assignment(s): nskip_inst_st0, skip_inst_st1, skip_inst_st2
|
2325 |
|
|
-- replace(s): nskip_inst_st0, skip_inst_st1, skip_inst_st2
|
2326 |
|
|
|
2327 |
|
|
skip_instruction_sm:process(cp2,ireset)
|
2328 |
|
|
begin
|
2329 |
|
|
if ireset='0' then -- RESET
|
2330 |
|
|
nskip_inst_st0 <= '0';
|
2331 |
|
|
skip_inst_st1 <= '0';
|
2332 |
|
|
skip_inst_st2 <= '0';
|
2333 |
|
|
elsif (cp2='1' and cp2'event) then skip_inst_st2 <= skip_inst_st2_cml_3; skip_inst_st1 <= skip_inst_st1_cml_3; nskip_inst_st0 <= nskip_inst_st0_cml_3; -- CLOCK
|
2334 |
|
|
if (cp2en='1') then -- Clock enable
|
2335 |
|
|
nskip_inst_st0 <= (not nskip_inst_st0_cml_3 and skip_inst_start) or
|
2336 |
|
|
(nskip_inst_st0_cml_3 and not((skip_inst_st1_cml_3 and not two_word_inst) or skip_inst_st2_cml_3));
|
2337 |
|
|
skip_inst_st1 <= (not skip_inst_st1_cml_3 and not nskip_inst_st0_cml_3 and skip_inst_start);
|
2338 |
|
|
skip_inst_st2 <= not skip_inst_st2_cml_3 and skip_inst_st1_cml_3 and two_word_inst;
|
2339 |
|
|
end if;
|
2340 |
|
|
end if;
|
2341 |
|
|
end process;
|
2342 |
|
|
|
2343 |
|
|
|
2344 |
|
|
|
2345 |
|
|
-- SynEDA CoreMultiplier
|
2346 |
|
|
-- assignment(s): adiw_st, sbiw_st
|
2347 |
|
|
-- replace(s): adiw_st, idc_adiw, sbiw_st, idc_sbiw
|
2348 |
|
|
|
2349 |
|
|
alu_state_machines:process(cp2,ireset)
|
2350 |
|
|
begin
|
2351 |
|
|
if ireset='0' then -- RESET
|
2352 |
|
|
adiw_st <= '0';
|
2353 |
|
|
sbiw_st <= '0';
|
2354 |
|
|
elsif (cp2='1' and cp2'event) then sbiw_st <= sbiw_st_cml_3; adiw_st <= adiw_st_cml_3; -- CLOCK
|
2355 |
|
|
if (cp2en='1') then -- Clock enable
|
2356 |
|
|
adiw_st <= not adiw_st_cml_3 and idc_adiw_cml_3;
|
2357 |
|
|
sbiw_st <= not sbiw_st_cml_3 and idc_sbiw_cml_3;
|
2358 |
|
|
end if;
|
2359 |
|
|
end if;
|
2360 |
|
|
end process;
|
2361 |
|
|
|
2362 |
|
|
|
2363 |
|
|
-- SynEDA CoreMultiplier
|
2364 |
|
|
-- assignment(s): nlpm_st0, lpm_st1, lpm_st2
|
2365 |
|
|
-- replace(s): nlpm_st0, lpm_st2, lpm_st1
|
2366 |
|
|
|
2367 |
|
|
lpm_state_machine:process(cp2,ireset)
|
2368 |
|
|
begin
|
2369 |
|
|
if ireset='0' then -- RESET
|
2370 |
|
|
nlpm_st0 <= '0';
|
2371 |
|
|
lpm_st1 <= '0';
|
2372 |
|
|
lpm_st2 <= '0';
|
2373 |
|
|
elsif (cp2='1' and cp2'event) then lpm_st2 <= lpm_st2_cml_3; lpm_st1 <= lpm_st1_cml_3; nlpm_st0 <= nlpm_st0_cml_3; -- CLOCK
|
2374 |
|
|
if (cp2en='1') then -- Clock enable
|
2375 |
|
|
nlpm_st0 <= (not nlpm_st0_cml_3 and (idc_lpm or idc_elpm)) or (nlpm_st0_cml_3 and not lpm_st2_cml_3);
|
2376 |
|
|
lpm_st1 <= (not lpm_st1_cml_3 and not nlpm_st0_cml_3 and (idc_lpm or idc_elpm)); -- ??
|
2377 |
|
|
lpm_st2 <= not lpm_st2_cml_3 and lpm_st1_cml_3;
|
2378 |
|
|
end if;
|
2379 |
|
|
end if;
|
2380 |
|
|
end process;
|
2381 |
|
|
|
2382 |
|
|
|
2383 |
|
|
-- SynEDA CoreMultiplier
|
2384 |
|
|
-- assignment(s): lds_st
|
2385 |
|
|
-- replace(s): cpuwait, lds_st, idc_lds
|
2386 |
|
|
|
2387 |
|
|
lds_state_machine:process(cp2,ireset)
|
2388 |
|
|
begin
|
2389 |
|
|
if ireset='0' then -- RESET
|
2390 |
|
|
lds_st <= '0';
|
2391 |
|
|
elsif (cp2='1' and cp2'event) then lds_st <= lds_st_cml_3; -- CLOCK
|
2392 |
|
|
if (cp2en='1') then -- Clock enable
|
2393 |
|
|
lds_st <= (not lds_st_cml_3 and idc_lds_cml_3) or (lds_st_cml_3 and cpuwait_cml_3);
|
2394 |
|
|
end if;
|
2395 |
|
|
end if;
|
2396 |
|
|
end process;
|
2397 |
|
|
|
2398 |
|
|
|
2399 |
|
|
-- SynEDA CoreMultiplier
|
2400 |
|
|
-- assignment(s): sts_st
|
2401 |
|
|
-- replace(s): cpuwait, sts_st, idc_sts
|
2402 |
|
|
|
2403 |
|
|
sts_state_machine:process(cp2,ireset)
|
2404 |
|
|
begin
|
2405 |
|
|
if ireset='0' then -- RESET
|
2406 |
|
|
sts_st <= '0';
|
2407 |
|
|
elsif (cp2='1' and cp2'event) then sts_st <= sts_st_cml_3; -- CLOCK
|
2408 |
|
|
if (cp2en='1') then -- Clock enable
|
2409 |
|
|
sts_st <= (not sts_st_cml_3 and idc_sts_cml_3) or (sts_st_cml_3 and cpuwait_cml_3);
|
2410 |
|
|
end if;
|
2411 |
|
|
end if;
|
2412 |
|
|
end process;
|
2413 |
|
|
|
2414 |
|
|
-- SynEDA CoreMultiplier
|
2415 |
|
|
-- assignment(s): njmp_st0, jmp_st1, jmp_st2
|
2416 |
|
|
-- replace(s): njmp_st0, jmp_st2, jmp_st1
|
2417 |
|
|
|
2418 |
|
|
jmp_state_machine:process(cp2,ireset)
|
2419 |
|
|
begin
|
2420 |
|
|
if ireset='0' then -- RESET
|
2421 |
|
|
njmp_st0 <= '0';
|
2422 |
|
|
jmp_st1 <= '0';
|
2423 |
|
|
jmp_st2 <= '0';
|
2424 |
|
|
elsif (cp2='1' and cp2'event) then jmp_st2 <= jmp_st2_cml_3; jmp_st1 <= jmp_st1_cml_3; njmp_st0 <= njmp_st0_cml_3; -- CLOCK
|
2425 |
|
|
if (cp2en='1') then -- Clock enable
|
2426 |
|
|
njmp_st0 <= (not njmp_st0_cml_3 and idc_jmp) or (njmp_st0_cml_3 and not jmp_st2_cml_3);
|
2427 |
|
|
jmp_st1 <= not jmp_st1_cml_3 and not njmp_st0_cml_3 and idc_jmp; -- ??
|
2428 |
|
|
jmp_st2 <= not jmp_st2_cml_3 and jmp_st1_cml_3;
|
2429 |
|
|
end if;
|
2430 |
|
|
end if;
|
2431 |
|
|
end process;
|
2432 |
|
|
|
2433 |
|
|
-- SynEDA CoreMultiplier
|
2434 |
|
|
-- assignment(s): nrcall_st0, rcall_st1, rcall_st2
|
2435 |
|
|
-- replace(s): cpuwait, nrcall_st0, rcall_st2, idc_rcall, rcall_st1
|
2436 |
|
|
|
2437 |
|
|
rcall_state_machine:process(cp2,ireset)
|
2438 |
|
|
begin
|
2439 |
|
|
if ireset='0' then -- RESET
|
2440 |
|
|
nrcall_st0 <= '0';
|
2441 |
|
|
rcall_st1 <= '0';
|
2442 |
|
|
rcall_st2 <= '0';
|
2443 |
|
|
elsif (cp2='1' and cp2'event) then rcall_st2 <= rcall_st2_cml_3; rcall_st1 <= rcall_st1_cml_3; nrcall_st0 <= nrcall_st0_cml_3; -- CLOCK
|
2444 |
|
|
if (cp2en='1') then -- Clock enable
|
2445 |
|
|
nrcall_st0 <= (not nrcall_st0_cml_3 and idc_rcall_cml_3) or (nrcall_st0_cml_3 and not (rcall_st2_cml_3 and not cpuwait_cml_3));
|
2446 |
|
|
rcall_st1 <= (not rcall_st1_cml_3 and not nrcall_st0_cml_3 and idc_rcall_cml_3) or (rcall_st1_cml_3 and cpuwait_cml_3);
|
2447 |
|
|
rcall_st2 <= (not rcall_st2_cml_3 and rcall_st1_cml_3 and not cpuwait_cml_3) or (rcall_st2_cml_3 and cpuwait_cml_3);
|
2448 |
|
|
end if;
|
2449 |
|
|
end if;
|
2450 |
|
|
end process;
|
2451 |
|
|
|
2452 |
|
|
-- SynEDA CoreMultiplier
|
2453 |
|
|
-- assignment(s): nicall_st0, icall_st1, icall_st2
|
2454 |
|
|
-- replace(s): cpuwait, nicall_st0, icall_st2, idc_icall, icall_st1
|
2455 |
|
|
|
2456 |
|
|
icall_state_machine:process(cp2,ireset)
|
2457 |
|
|
begin
|
2458 |
|
|
if ireset='0' then -- RESET
|
2459 |
|
|
nicall_st0 <= '0';
|
2460 |
|
|
icall_st1 <= '0';
|
2461 |
|
|
icall_st2 <= '0';
|
2462 |
|
|
elsif (cp2='1' and cp2'event) then icall_st2 <= icall_st2_cml_3; icall_st1 <= icall_st1_cml_3; nicall_st0 <= nicall_st0_cml_3; -- CLOCK
|
2463 |
|
|
if (cp2en='1') then -- Clock enable
|
2464 |
|
|
nicall_st0 <= (not nicall_st0_cml_3 and idc_icall_cml_3) or (nicall_st0_cml_3 and not (icall_st2_cml_3 and not cpuwait_cml_3));
|
2465 |
|
|
icall_st1 <= (not icall_st1_cml_3 and not nicall_st0_cml_3 and idc_icall_cml_3) or (icall_st1_cml_3 and cpuwait_cml_3);
|
2466 |
|
|
icall_st2 <= (not icall_st2_cml_3 and icall_st1_cml_3 and not cpuwait_cml_3) or (icall_st2_cml_3 and cpuwait_cml_3);
|
2467 |
|
|
end if;
|
2468 |
|
|
end if;
|
2469 |
|
|
end process;
|
2470 |
|
|
|
2471 |
|
|
-- SynEDA CoreMultiplier
|
2472 |
|
|
-- assignment(s): ncall_st0, call_st1, call_st2, call_st3
|
2473 |
|
|
-- replace(s): cpuwait, ncall_st0, call_st3, call_st1, call_st2
|
2474 |
|
|
|
2475 |
|
|
call_state_machine:process(cp2,ireset)
|
2476 |
|
|
begin
|
2477 |
|
|
if ireset='0' then -- RESET
|
2478 |
|
|
ncall_st0 <= '0';
|
2479 |
|
|
call_st1 <= '0';
|
2480 |
|
|
call_st2 <= '0';
|
2481 |
|
|
call_st3 <= '0';
|
2482 |
|
|
elsif (cp2='1' and cp2'event) then call_st3 <= call_st3_cml_3; call_st2 <= call_st2_cml_3; call_st1 <= call_st1_cml_3; ncall_st0 <= ncall_st0_cml_3; -- CLOCK
|
2483 |
|
|
if (cp2en='1') then -- Clock enable
|
2484 |
|
|
ncall_st0 <= (not ncall_st0_cml_3 and idc_call) or (ncall_st0_cml_3 and not( call_st3_cml_3 and not cpuwait_cml_3));
|
2485 |
|
|
call_st1 <= not call_st1_cml_3 and not ncall_st0_cml_3 and idc_call;
|
2486 |
|
|
call_st2 <= (not call_st2_cml_3 and call_st1_cml_3) or (call_st2_cml_3 and cpuwait_cml_3);
|
2487 |
|
|
call_st3 <= (not call_st3_cml_3 and call_st2_cml_3 and not cpuwait_cml_3) or (call_st3_cml_3 and cpuwait_cml_3);
|
2488 |
|
|
end if;
|
2489 |
|
|
end if;
|
2490 |
|
|
end process;
|
2491 |
|
|
|
2492 |
|
|
-- SynEDA CoreMultiplier
|
2493 |
|
|
-- assignment(s): nret_st0, ret_st1, ret_st2, ret_st3
|
2494 |
|
|
-- replace(s): nret_st0, ret_st3, idc_ret, cpuwait, ret_st1, ret_st2
|
2495 |
|
|
|
2496 |
|
|
ret_state_machine:process(cp2,ireset)
|
2497 |
|
|
begin
|
2498 |
|
|
if ireset='0' then -- RESET
|
2499 |
|
|
nret_st0 <= '0';
|
2500 |
|
|
ret_st1 <= '0';
|
2501 |
|
|
ret_st2 <= '0';
|
2502 |
|
|
ret_st3 <= '0';
|
2503 |
|
|
elsif (cp2='1' and cp2'event) then ret_st3 <= ret_st3_cml_3; ret_st2 <= ret_st2_cml_3; ret_st1 <= ret_st1_cml_3; nret_st0 <= nret_st0_cml_3; -- CLOCK
|
2504 |
|
|
if (cp2en='1') then -- Clock enable
|
2505 |
|
|
nret_st0 <= (not nret_st0_cml_3 and idc_ret_cml_3) or (nret_st0_cml_3 and not ret_st3_cml_3);
|
2506 |
|
|
ret_st1 <= (not ret_st1_cml_3 and not nret_st0_cml_3 and idc_ret_cml_3) or (ret_st1_cml_3 and cpuwait_cml_3);
|
2507 |
|
|
ret_st2 <= (not ret_st2_cml_3 and ret_st1_cml_3 and not cpuwait_cml_3) or (ret_st2_cml_3 and cpuwait_cml_3) ;
|
2508 |
|
|
ret_st3 <= not ret_st3_cml_3 and ret_st2_cml_3 and not cpuwait_cml_3;
|
2509 |
|
|
end if;
|
2510 |
|
|
end if;
|
2511 |
|
|
end process;
|
2512 |
|
|
|
2513 |
|
|
-- SynEDA CoreMultiplier
|
2514 |
|
|
-- assignment(s): nreti_st0, reti_st1, reti_st2, reti_st3
|
2515 |
|
|
-- replace(s): nreti_st0, reti_st3, idc_reti, cpuwait, reti_st1, reti_st2
|
2516 |
|
|
|
2517 |
|
|
reti_state_machine:process(cp2,ireset)
|
2518 |
|
|
begin
|
2519 |
|
|
if ireset='0' then -- RESET
|
2520 |
|
|
nreti_st0 <= '0';
|
2521 |
|
|
reti_st1 <= '0';
|
2522 |
|
|
reti_st2 <= '0';
|
2523 |
|
|
reti_st3 <= '0';
|
2524 |
|
|
elsif (cp2='1' and cp2'event) then reti_st3 <= reti_st3_cml_3; reti_st2 <= reti_st2_cml_3; reti_st1 <= reti_st1_cml_3; nreti_st0 <= nreti_st0_cml_3; -- CLOCK
|
2525 |
|
|
if (cp2en='1') then -- Clock enable
|
2526 |
|
|
nreti_st0 <= (not nreti_st0_cml_3 and idc_reti_cml_3) or (nreti_st0_cml_3 and not reti_st3_cml_3);
|
2527 |
|
|
reti_st1 <= (not reti_st1_cml_3 and not nreti_st0_cml_3 and idc_reti_cml_3) or (reti_st1_cml_3 and cpuwait_cml_3);
|
2528 |
|
|
reti_st2 <= (not reti_st2_cml_3 and reti_st1_cml_3 and not cpuwait_cml_3) or (reti_st2_cml_3 and cpuwait_cml_3) ;
|
2529 |
|
|
reti_st3 <= not reti_st3_cml_3 and reti_st2_cml_3 and not cpuwait_cml_3;
|
2530 |
|
|
end if;
|
2531 |
|
|
end if;
|
2532 |
|
|
end process;
|
2533 |
|
|
|
2534 |
|
|
|
2535 |
|
|
-- INTERRUPT LOGIC AND STATE MACHINE
|
2536 |
|
|
|
2537 |
|
|
-- SynEDA CoreMultiplier
|
2538 |
|
|
-- assignment(s): irq_int
|
2539 |
|
|
-- replace(s): irqlines
|
2540 |
|
|
|
2541 |
|
|
irq_int <= '0' when irqlines_cml_3="00000000000000000000000" else '1';
|
2542 |
|
|
|
2543 |
|
|
irq_vector_adr(15 downto 6)<=(others => '0');
|
2544 |
|
|
irq_vector_adr(0) <= '0';
|
2545 |
|
|
-- PRIORITY ENCODER
|
2546 |
|
|
irq_vector_adr(5 downto 1) <= "00001" when irqlines(0)='1' else -- 0x0002
|
2547 |
|
|
"00010" when irqlines(1)='1' else -- 0x0004
|
2548 |
|
|
"00011" when irqlines(2)='1' else -- 0x0006
|
2549 |
|
|
"00100" when irqlines(3)='1' else -- 0x0008
|
2550 |
|
|
"00101" when irqlines(4)='1' else -- 0x000A
|
2551 |
|
|
"00110" when irqlines(5)='1' else -- 0x000C
|
2552 |
|
|
"00111" when irqlines(6)='1' else -- 0x000E
|
2553 |
|
|
"01000" when irqlines(7)='1' else -- 0x0010
|
2554 |
|
|
"01001" when irqlines(8)='1' else -- 0x0012
|
2555 |
|
|
"01010" when irqlines(9)='1' else -- 0x0014
|
2556 |
|
|
"01011" when irqlines(10)='1' else -- 0x0016
|
2557 |
|
|
"01100" when irqlines(11)='1' else -- 0x0018
|
2558 |
|
|
"01101" when irqlines(12)='1' else -- 0x001A
|
2559 |
|
|
"01110" when irqlines(13)='1' else -- 0x001C
|
2560 |
|
|
"01111" when irqlines(14)='1' else -- 0x001E
|
2561 |
|
|
"10000" when irqlines(15)='1' else -- 0x0020
|
2562 |
|
|
"10001" when irqlines(16)='1' else -- 0x0022
|
2563 |
|
|
"10010" when irqlines(17)='1' else -- 0x0024
|
2564 |
|
|
"10011" when irqlines(18)='1' else -- 0x0026
|
2565 |
|
|
"10100" when irqlines(19)='1' else -- 0x0028
|
2566 |
|
|
"10101" when irqlines(20)='1' else -- 0x002A
|
2567 |
|
|
"10110" when irqlines(21)='1' else -- 0x002C
|
2568 |
|
|
"10111" when irqlines(22)='1' else -- 0x002E
|
2569 |
|
|
"00000";
|
2570 |
|
|
|
2571 |
|
|
-- SynEDA CoreMultiplier
|
2572 |
|
|
-- assignment(s): cpu_busy
|
2573 |
|
|
-- replace(s): cpuwait, nirq_st0, call_st1, call_st2, call_st3, rcall_st1, rcall_st2, icall_st1, icall_st2, jmp_st1, ret_st1, ret_st2, reti_st1, reti_st2, skip_inst_st1, lpm_st1, sts_st, lds_st, st_st, ld_st, push_st, pop_st, idc_adiw, idc_cbi, idc_icall, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
|
2574 |
|
|
|
2575 |
|
|
-- MULTI CYCLE INSTRUCTION FLAG FOR IRQ
|
2576 |
|
|
cpu_busy <= idc_adiw_cml_3 or idc_sbiw_cml_3 or idc_cbi_cml_3 or idc_sbi_cml_3 or
|
2577 |
|
|
idc_rjmp or idc_ijmp or
|
2578 |
|
|
idc_jmp or jmp_st1_cml_3 or
|
2579 |
|
|
-- idc_brbs or idc_brbc or -- Old variant
|
2580 |
|
|
((idc_brbc or idc_brbs) and bit_test_op_out) or
|
2581 |
|
|
idc_lpm or lpm_st1_cml_3 or
|
2582 |
|
|
skip_inst_start or (skip_inst_st1_cml_3 and two_word_inst) or
|
2583 |
|
|
idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ldd_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_z_cml_3 or (ld_st_cml_3 and cpuwait_cml_3) or
|
2584 |
|
|
idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3 or (st_st_cml_3 and cpuwait_cml_3) or
|
2585 |
|
|
idc_lds_cml_3 or (lds_st_cml_3 and cpuwait_cml_3) or
|
2586 |
|
|
idc_sts_cml_3 or (sts_st_cml_3 and cpuwait_cml_3) or
|
2587 |
|
|
idc_rcall_cml_3 or rcall_st1_cml_3 or (rcall_st2_cml_3 and cpuwait_cml_3) or -- RCALL
|
2588 |
|
|
idc_icall_cml_3 or icall_st1_cml_3 or (icall_st2_cml_3 and cpuwait_cml_3) or -- ICALL
|
2589 |
|
|
idc_call or call_st1_cml_3 or call_st2_cml_3 or (call_st3_cml_3 and cpuwait_cml_3) or -- CALL
|
2590 |
|
|
idc_push_cml_3 or (push_st_cml_3 and cpuwait_cml_3) or -- PUSH (added 14.07.05)
|
2591 |
|
|
idc_pop_cml_3 or (pop_st_cml_3 and cpuwait_cml_3) or -- POP (added 14.07.05)
|
2592 |
|
|
(idc_bclr and sreg_bop_wr_en(7)) or -- ??? CLI
|
2593 |
|
|
(iowe_int and sreg_adr_eq and not dbusout_int(7))or -- ??? Writing '0' to I flag (OUT/STD/ST/STD)
|
2594 |
|
|
nirq_st0_cml_3 or
|
2595 |
|
|
-- idc_ret or nret_st0 or -- Old variant
|
2596 |
|
|
idc_ret_cml_3 or ret_st1_cml_3 or ret_st2_cml_3 or
|
2597 |
|
|
-- idc_reti or nreti_st0; -- At least one instruction must be executed after RETI and before the new interrupt.
|
2598 |
|
|
idc_reti_cml_3 or reti_st1_cml_3 or reti_st2_cml_3;
|
2599 |
|
|
|
2600 |
|
|
-- SynEDA CoreMultiplier
|
2601 |
|
|
-- assignment(s): sreg_adr_eq
|
2602 |
|
|
-- replace(s): adr_int
|
2603 |
|
|
|
2604 |
|
|
sreg_adr_eq <= '1' when adr_int_cml_3=SREG_Address else '0';
|
2605 |
|
|
|
2606 |
|
|
--irq_start <= irq_int and not cpu_busy and globint;
|
2607 |
|
|
irq_start <= irq_int and not cpu_busy and globint;
|
2608 |
|
|
|
2609 |
|
|
-- SynEDA CoreMultiplier
|
2610 |
|
|
-- assignment(s): nirq_st0, irq_st1, irq_st2, irq_st3
|
2611 |
|
|
-- replace(s): cpuwait, nirq_st0, irq_st3, irq_st1, irq_st2
|
2612 |
|
|
|
2613 |
|
|
irq_state_machine:process(cp2,ireset)
|
2614 |
|
|
begin
|
2615 |
|
|
if ireset='0' then -- RESET
|
2616 |
|
|
nirq_st0 <= '0';
|
2617 |
|
|
irq_st1 <= '0';
|
2618 |
|
|
irq_st2 <= '0';
|
2619 |
|
|
irq_st3 <= '0';
|
2620 |
|
|
elsif (cp2='1' and cp2'event) then irq_st3 <= irq_st3_cml_3; irq_st2 <= irq_st2_cml_3; irq_st1 <= irq_st1_cml_3; nirq_st0 <= nirq_st0_cml_3; -- CLOCK
|
2621 |
|
|
if (cp2en='1') then -- Clock enable
|
2622 |
|
|
nirq_st0 <= (not nirq_st0_cml_3 and irq_start) or (nirq_st0_cml_3 and not (irq_st3_cml_3 and not cpuwait_cml_3));
|
2623 |
|
|
irq_st1 <= (not irq_st1_cml_3 and not nirq_st0_cml_3 and irq_start);
|
2624 |
|
|
irq_st2 <= (not irq_st2_cml_3 and irq_st1_cml_3) or (irq_st2_cml_3 and cpuwait_cml_3);
|
2625 |
|
|
irq_st3 <= (not irq_st3_cml_3 and irq_st2_cml_3 and not cpuwait_cml_3) or (irq_st3_cml_3 and cpuwait_cml_3);
|
2626 |
|
|
end if;
|
2627 |
|
|
end if;
|
2628 |
|
|
end process;
|
2629 |
|
|
|
2630 |
|
|
-- SynEDA CoreMultiplier
|
2631 |
|
|
-- assignment(s): irqack_int
|
2632 |
|
|
-- replace(s): irqack_int
|
2633 |
|
|
|
2634 |
|
|
irqack_reg:process(cp2,ireset)
|
2635 |
|
|
begin
|
2636 |
|
|
if ireset='0' then -- RESET
|
2637 |
|
|
irqack_int<='0';
|
2638 |
|
|
elsif (cp2='1' and cp2'event) then irqack_int <= irqack_int_cml_3; -- CLOCK
|
2639 |
|
|
if (cp2en='1') then -- Clock enable
|
2640 |
|
|
irqack_int<= not irqack_int_cml_3 and irq_start;
|
2641 |
|
|
end if;
|
2642 |
|
|
end if;
|
2643 |
|
|
end process;
|
2644 |
|
|
-- SynEDA CoreMultiplier
|
2645 |
|
|
-- assignment(s): irqack
|
2646 |
|
|
-- replace(s): irqack_int
|
2647 |
|
|
|
2648 |
|
|
irqack_cml_out <= irqack_int_cml_3;
|
2649 |
|
|
|
2650 |
|
|
-- SynEDA CoreMultiplier
|
2651 |
|
|
-- assignment(s): irqackad_int
|
2652 |
|
|
-- replace(s): irqackad_int, irq_vector_adr
|
2653 |
|
|
|
2654 |
|
|
irqackad_reg:process(cp2,ireset)
|
2655 |
|
|
begin
|
2656 |
|
|
if ireset='0' then -- RESET
|
2657 |
|
|
irqackad_int<=(others=>'0');
|
2658 |
|
|
elsif (cp2='1' and cp2'event) then irqackad_int <= irqackad_int_cml_3; -- CLOCK
|
2659 |
|
|
if (cp2en='1') then -- Clock enable
|
2660 |
|
|
irqackad_int <= irq_vector_adr_cml_3(5 downto 1);
|
2661 |
|
|
end if;
|
2662 |
|
|
end if;
|
2663 |
|
|
end process;
|
2664 |
|
|
-- SynEDA CoreMultiplier
|
2665 |
|
|
-- assignment(s): irqackad
|
2666 |
|
|
-- replace(s): irqackad_int
|
2667 |
|
|
|
2668 |
|
|
irqackad_cml_out <= irqackad_int_cml_3;
|
2669 |
|
|
|
2670 |
|
|
-- *******************************************************************************************
|
2671 |
|
|
|
2672 |
|
|
-- SynEDA CoreMultiplier
|
2673 |
|
|
-- assignment(s): ijmp_st, rjmp_st, brxx_st, push_st, pop_st
|
2674 |
|
|
-- replace(s): ijmp_st, rjmp_st, brxx_st, cpuwait, push_st, idc_push, pop_st, idc_pop
|
2675 |
|
|
|
2676 |
|
|
rjmp_push_pop_ijmp_state_brxx_machine:process(cp2,ireset)
|
2677 |
|
|
begin
|
2678 |
|
|
if ireset='0' then -- RESET
|
2679 |
|
|
rjmp_st <= '0';
|
2680 |
|
|
ijmp_st <= '0';
|
2681 |
|
|
push_st <= '0';
|
2682 |
|
|
pop_st <= '0';
|
2683 |
|
|
brxx_st <= '0';
|
2684 |
|
|
elsif (cp2='1' and cp2'event) then pop_st <= pop_st_cml_3; push_st <= push_st_cml_3; brxx_st <= brxx_st_cml_3; rjmp_st <= rjmp_st_cml_3; ijmp_st <= ijmp_st_cml_3; -- CLOCK
|
2685 |
|
|
if (cp2en='1') then -- Clock enable
|
2686 |
|
|
rjmp_st <= idc_rjmp; -- ??
|
2687 |
|
|
ijmp_st <= idc_ijmp;
|
2688 |
|
|
push_st <= (not push_st_cml_3 and idc_push_cml_3) or (push_st_cml_3 and cpuwait_cml_3);
|
2689 |
|
|
pop_st <= (not pop_st_cml_3 and idc_pop_cml_3) or (pop_st_cml_3 and cpuwait_cml_3);
|
2690 |
|
|
brxx_st <= not brxx_st_cml_3 and (idc_brbc or idc_brbs) and bit_test_op_out;
|
2691 |
|
|
end if;
|
2692 |
|
|
end if;
|
2693 |
|
|
end process;
|
2694 |
|
|
|
2695 |
|
|
-- SynEDA CoreMultiplier
|
2696 |
|
|
-- assignment(s): st_st, ld_st
|
2697 |
|
|
-- replace(s): cpuwait, st_st, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, ld_st, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z
|
2698 |
|
|
|
2699 |
|
|
-- LD/LDD/ST/STD
|
2700 |
|
|
ld_st_state_machine:process(cp2,ireset)
|
2701 |
|
|
begin
|
2702 |
|
|
if ireset='0' then -- RESET
|
2703 |
|
|
ld_st <= '0';
|
2704 |
|
|
st_st <= '0';
|
2705 |
|
|
elsif (cp2='1' and cp2'event) then ld_st <= ld_st_cml_3; st_st <= st_st_cml_3; -- CLOCK
|
2706 |
|
|
if (cp2en='1') then -- Clock enable
|
2707 |
|
|
ld_st <= (not ld_st_cml_3 and (idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ldd_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_z_cml_3)) or (ld_st_cml_3 and cpuwait_cml_3);
|
2708 |
|
|
st_st <= (not st_st_cml_3 and (idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3)) or (st_st_cml_3 and cpuwait_cml_3);
|
2709 |
|
|
end if;
|
2710 |
|
|
end if;
|
2711 |
|
|
end process;
|
2712 |
|
|
|
2713 |
|
|
-- SynEDA CoreMultiplier
|
2714 |
|
|
-- assignment(s): sbi_st, cbi_st, cbi_sbi_io_adr_tmp, cbi_sbi_bit_num_tmp
|
2715 |
|
|
-- replace(s): sbi_st, idc_sbi, cbi_st, idc_cbi, dex_adr5port, cbi_sbi_io_adr_tmp, dex_bitop_bitnum, cbi_sbi_bit_num_tmp
|
2716 |
|
|
|
2717 |
|
|
-- SBI/CBI
|
2718 |
|
|
sbi_cbi_machine:process(cp2,ireset)
|
2719 |
|
|
begin
|
2720 |
|
|
if ireset='0' then -- RESET
|
2721 |
|
|
sbi_st <= '0';
|
2722 |
|
|
cbi_st <= '0';
|
2723 |
|
|
cbi_sbi_io_adr_tmp <= (others => '0');
|
2724 |
|
|
cbi_sbi_bit_num_tmp <= (others => '0');
|
2725 |
|
|
elsif (cp2='1' and cp2'event) then cbi_sbi_bit_num_tmp <= cbi_sbi_bit_num_tmp_cml_3; cbi_sbi_io_adr_tmp <= cbi_sbi_io_adr_tmp_cml_3; cbi_st <= cbi_st_cml_3; sbi_st <= sbi_st_cml_3; -- CLOCK
|
2726 |
|
|
if (cp2en='1') then -- Clock enable
|
2727 |
|
|
sbi_st <= not sbi_st_cml_3 and idc_sbi_cml_3;
|
2728 |
|
|
cbi_st <= not cbi_st_cml_3 and idc_cbi_cml_3;
|
2729 |
|
|
cbi_sbi_io_adr_tmp <= dex_adr5port_cml_3;
|
2730 |
|
|
cbi_sbi_bit_num_tmp <= dex_bitop_bitnum_cml_3;
|
2731 |
|
|
end if;
|
2732 |
|
|
end if;
|
2733 |
|
|
end process;
|
2734 |
|
|
|
2735 |
|
|
-- ########################################################################################
|
2736 |
|
|
|
2737 |
|
|
-- SREG FLAGS WRITE ENABLE LOGIC
|
2738 |
|
|
|
2739 |
|
|
--bclr_bset_op_en_logic:for i in sreg_bop_wr_en'range generate
|
2740 |
|
|
--sreg_bop_wr_en(i) <= '1' when (dex_bitnum_sreg=i and (idc_bclr or idc_bset)='1') else '0';
|
2741 |
|
|
--end generate;
|
2742 |
|
|
|
2743 |
|
|
sreg_bop_wr_en(0) <= '1' when (dex_bitnum_sreg=0 and (idc_bclr or idc_bset)='1') else '0';
|
2744 |
|
|
sreg_bop_wr_en(1) <= '1' when (dex_bitnum_sreg=1 and (idc_bclr or idc_bset)='1') else '0';
|
2745 |
|
|
sreg_bop_wr_en(2) <= '1' when (dex_bitnum_sreg=2 and (idc_bclr or idc_bset)='1') else '0';
|
2746 |
|
|
sreg_bop_wr_en(3) <= '1' when (dex_bitnum_sreg=3 and (idc_bclr or idc_bset)='1') else '0';
|
2747 |
|
|
sreg_bop_wr_en(4) <= '1' when (dex_bitnum_sreg=4 and (idc_bclr or idc_bset)='1') else '0';
|
2748 |
|
|
sreg_bop_wr_en(5) <= '1' when (dex_bitnum_sreg=5 and (idc_bclr or idc_bset)='1') else '0';
|
2749 |
|
|
sreg_bop_wr_en(6) <= '1' when (dex_bitnum_sreg=6 and (idc_bclr or idc_bset)='1') else '0';
|
2750 |
|
|
sreg_bop_wr_en(7) <= '1' when (dex_bitnum_sreg=7 and (idc_bclr or idc_bset)='1') else '0';
|
2751 |
|
|
|
2752 |
|
|
-- SynEDA CoreMultiplier
|
2753 |
|
|
-- assignment(s): sreg_c_wr_en
|
2754 |
|
|
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_adiw, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_lsr, idc_neg, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi
|
2755 |
|
|
|
2756 |
|
|
sreg_c_wr_en <= idc_add_cml_3 or idc_adc_cml_3 or (idc_adiw_cml_3 or adiw_st_cml_3) or idc_sub_cml_3 or idc_subi_cml_3 or
|
2757 |
|
|
idc_sbc_cml_3 or idc_sbci_cml_3 or (idc_sbiw_cml_3 or sbiw_st_cml_3) or idc_com_cml_3 or idc_neg_cml_3 or
|
2758 |
|
|
idc_cp_cml_3 or idc_cpc_cml_3 or idc_cpi_cml_3 or
|
2759 |
|
|
idc_lsr_cml_3 or idc_ror_cml_3 or idc_asr_cml_3 or sreg_bop_wr_en(0);
|
2760 |
|
|
|
2761 |
|
|
-- SynEDA CoreMultiplier
|
2762 |
|
|
-- assignment(s): sreg_z_wr_en
|
2763 |
|
|
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_adiw, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi
|
2764 |
|
|
|
2765 |
|
|
sreg_z_wr_en <= idc_add_cml_3 or idc_adc_cml_3 or (idc_adiw_cml_3 or adiw_st_cml_3) or idc_sub_cml_3 or idc_subi_cml_3 or
|
2766 |
|
|
idc_sbc_cml_3 or idc_sbci_cml_3 or (idc_sbiw_cml_3 or sbiw_st_cml_3) or
|
2767 |
|
|
idc_cp_cml_3 or idc_cpc_cml_3 or idc_cpi_cml_3 or
|
2768 |
|
|
idc_and_cml_3 or idc_andi_cml_3 or idc_or_cml_3 or idc_ori_cml_3 or idc_eor_cml_3 or idc_com_cml_3 or idc_neg_cml_3 or
|
2769 |
|
|
idc_inc_cml_3 or idc_dec_cml_3 or idc_lsr_cml_3 or idc_ror_cml_3 or idc_asr_cml_3 or sreg_bop_wr_en(1);
|
2770 |
|
|
|
2771 |
|
|
|
2772 |
|
|
-- SynEDA CoreMultiplier
|
2773 |
|
|
-- assignment(s): sreg_n_wr_en
|
2774 |
|
|
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi
|
2775 |
|
|
|
2776 |
|
|
sreg_n_wr_en <= idc_add_cml_3 or idc_adc_cml_3 or adiw_st_cml_3 or idc_sub_cml_3 or idc_subi_cml_3 or
|
2777 |
|
|
idc_sbc_cml_3 or idc_sbci_cml_3 or sbiw_st_cml_3 or
|
2778 |
|
|
idc_cp_cml_3 or idc_cpc_cml_3 or idc_cpi_cml_3 or
|
2779 |
|
|
idc_and_cml_3 or idc_andi_cml_3 or idc_or_cml_3 or idc_ori_cml_3 or idc_eor_cml_3 or idc_com_cml_3 or idc_neg_cml_3 or
|
2780 |
|
|
idc_inc_cml_3 or idc_dec_cml_3 or idc_lsr_cml_3 or idc_ror_cml_3 or idc_asr_cml_3 or sreg_bop_wr_en(2);
|
2781 |
|
|
|
2782 |
|
|
-- SynEDA CoreMultiplier
|
2783 |
|
|
-- assignment(s): sreg_v_wr_en
|
2784 |
|
|
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi
|
2785 |
|
|
|
2786 |
|
|
sreg_v_wr_en <= idc_add_cml_3 or idc_adc_cml_3 or adiw_st_cml_3 or idc_sub_cml_3 or idc_subi_cml_3 or -- idc_adiw
|
2787 |
|
|
idc_sbc_cml_3 or idc_sbci_cml_3 or sbiw_st_cml_3 or idc_neg_cml_3 or idc_com_cml_3 or -- idc_sbiw
|
2788 |
|
|
idc_inc_cml_3 or idc_dec_cml_3 or
|
2789 |
|
|
idc_cp_cml_3 or idc_cpc_cml_3 or idc_cpi_cml_3 or
|
2790 |
|
|
idc_lsr_cml_3 or idc_ror_cml_3 or idc_asr_cml_3 or sreg_bop_wr_en(3) or
|
2791 |
|
|
idc_and_cml_3 or idc_andi_cml_3 or idc_or_cml_3 or idc_ori_cml_3 or idc_eor_cml_3; -- V-flag bug fixing
|
2792 |
|
|
|
2793 |
|
|
-- SynEDA CoreMultiplier
|
2794 |
|
|
-- assignment(s): sreg_s_wr_en
|
2795 |
|
|
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi
|
2796 |
|
|
|
2797 |
|
|
sreg_s_wr_en <= idc_add_cml_3 or idc_adc_cml_3 or adiw_st_cml_3 or idc_sub_cml_3 or idc_subi_cml_3 or
|
2798 |
|
|
idc_sbc_cml_3 or idc_sbci_cml_3 or sbiw_st_cml_3 or
|
2799 |
|
|
idc_cp_cml_3 or idc_cpc_cml_3 or idc_cpi_cml_3 or
|
2800 |
|
|
idc_and_cml_3 or idc_andi_cml_3 or idc_or_cml_3 or idc_ori_cml_3 or idc_eor_cml_3 or idc_com_cml_3 or idc_neg_cml_3 or
|
2801 |
|
|
idc_inc_cml_3 or idc_dec_cml_3 or idc_lsr_cml_3 or idc_ror_cml_3 or idc_asr_cml_3 or sreg_bop_wr_en(4);
|
2802 |
|
|
|
2803 |
|
|
-- SynEDA CoreMultiplier
|
2804 |
|
|
-- assignment(s): sreg_h_wr_en
|
2805 |
|
|
-- replace(s): idc_adc, idc_add, idc_cp, idc_cpc, idc_cpi, idc_neg, idc_sbc, idc_sbci, idc_sub, idc_subi
|
2806 |
|
|
|
2807 |
|
|
sreg_h_wr_en <= idc_add_cml_3 or idc_adc_cml_3 or idc_sub_cml_3 or idc_subi_cml_3 or
|
2808 |
|
|
idc_cp_cml_3 or idc_cpc_cml_3 or idc_cpi_cml_3 or
|
2809 |
|
|
idc_sbc_cml_3 or idc_sbci_cml_3 or idc_neg_cml_3 or sreg_bop_wr_en(5);
|
2810 |
|
|
|
2811 |
|
|
sreg_t_wr_en <= idc_bst or sreg_bop_wr_en(6);
|
2812 |
|
|
|
2813 |
|
|
-- SynEDA CoreMultiplier
|
2814 |
|
|
-- assignment(s): sreg_i_wr_en
|
2815 |
|
|
-- replace(s): irq_st1, reti_st3
|
2816 |
|
|
|
2817 |
|
|
sreg_i_wr_en <= irq_st1_cml_3 or reti_st3_cml_3 or sreg_bop_wr_en(7); -- WAS "irq_start"
|
2818 |
|
|
|
2819 |
|
|
-- SynEDA CoreMultiplier
|
2820 |
|
|
-- assignment(s): sreg_fl_in
|
2821 |
|
|
-- replace(s): reti_st3
|
2822 |
|
|
|
2823 |
|
|
sreg_fl_in_cml_out <= bit_pr_sreg_out when (idc_bst or idc_bclr or idc_bset)='1' else -- TO THE SREG
|
2824 |
|
|
reti_st3_cml_3&'0'&alu_h_flag_out&alu_s_flag_out&alu_v_flag_out&alu_n_flag_out&alu_z_flag_out&alu_c_flag_out;
|
2825 |
|
|
|
2826 |
|
|
-- #################################################################################################################
|
2827 |
|
|
|
2828 |
|
|
-- *********************************************************************************************
|
2829 |
|
|
-- ************** INSTRUCTION DECODER OUTPUTS FOR THE OTHER BLOCKS ****************************
|
2830 |
|
|
-- *********************************************************************************************
|
2831 |
|
|
|
2832 |
|
|
-- FOR ALU
|
2833 |
|
|
|
2834 |
|
|
idc_add_out <= idc_add;
|
2835 |
|
|
idc_adc_out <= idc_adc;
|
2836 |
|
|
-- SynEDA CoreMultiplier
|
2837 |
|
|
-- assignment(s): idc_adiw_out
|
2838 |
|
|
-- replace(s): idc_adiw
|
2839 |
|
|
|
2840 |
|
|
idc_adiw_out_cml_out <= idc_adiw_cml_2;
|
2841 |
|
|
idc_sub_out <= idc_sub;
|
2842 |
|
|
idc_subi_out <= idc_subi;
|
2843 |
|
|
idc_sbc_out <= idc_sbc;
|
2844 |
|
|
idc_sbci_out <= idc_sbci;
|
2845 |
|
|
idc_sbiw_out <= idc_sbiw;
|
2846 |
|
|
adiw_st_out <= adiw_st;
|
2847 |
|
|
sbiw_st_out <= sbiw_st;
|
2848 |
|
|
idc_and_out <= idc_and;
|
2849 |
|
|
-- SynEDA CoreMultiplier
|
2850 |
|
|
-- assignment(s): idc_andi_out
|
2851 |
|
|
-- replace(s): idc_andi
|
2852 |
|
|
|
2853 |
|
|
idc_andi_out_cml_out <= idc_andi_cml_2;
|
2854 |
|
|
idc_or_out <= idc_or;
|
2855 |
|
|
-- SynEDA CoreMultiplier
|
2856 |
|
|
-- assignment(s): idc_ori_out
|
2857 |
|
|
-- replace(s): idc_ori
|
2858 |
|
|
|
2859 |
|
|
idc_ori_out_cml_out <= idc_ori_cml_2;
|
2860 |
|
|
idc_eor_out <= idc_eor;
|
2861 |
|
|
idc_com_out <= idc_com;
|
2862 |
|
|
idc_neg_out <= idc_neg;
|
2863 |
|
|
idc_inc_out <= idc_inc;
|
2864 |
|
|
idc_dec_out <= idc_dec;
|
2865 |
|
|
idc_cp_out <= idc_cp;
|
2866 |
|
|
idc_cpc_out <= idc_cpc;
|
2867 |
|
|
idc_cpi_out <= idc_cpi;
|
2868 |
|
|
idc_cpse_out <= idc_cpse;
|
2869 |
|
|
idc_lsr_out <= idc_lsr;
|
2870 |
|
|
idc_ror_out <= idc_ror;
|
2871 |
|
|
idc_asr_out <= idc_asr;
|
2872 |
|
|
idc_swap_out <= idc_swap;
|
2873 |
|
|
|
2874 |
|
|
-- FOR THE BIT PROCESSOR
|
2875 |
|
|
sbi_st_out <= sbi_st;
|
2876 |
|
|
cbi_st_out <= cbi_st;
|
2877 |
|
|
idc_bst_out <= idc_bst;
|
2878 |
|
|
idc_bset_out <= idc_bset;
|
2879 |
|
|
idc_bclr_out <= idc_bclr;
|
2880 |
|
|
-- SynEDA CoreMultiplier
|
2881 |
|
|
-- assignment(s): idc_sbic_out
|
2882 |
|
|
-- replace(s): idc_sbic
|
2883 |
|
|
|
2884 |
|
|
idc_sbic_out_cml_out <= idc_sbic_cml_2;
|
2885 |
|
|
-- SynEDA CoreMultiplier
|
2886 |
|
|
-- assignment(s): idc_sbis_out
|
2887 |
|
|
-- replace(s): idc_sbis
|
2888 |
|
|
|
2889 |
|
|
idc_sbis_out_cml_out <= idc_sbis_cml_2;
|
2890 |
|
|
-- SynEDA CoreMultiplier
|
2891 |
|
|
-- assignment(s): idc_sbrs_out
|
2892 |
|
|
-- replace(s): idc_sbrs
|
2893 |
|
|
|
2894 |
|
|
idc_sbrs_out_cml_out <= idc_sbrs_cml_3;
|
2895 |
|
|
-- SynEDA CoreMultiplier
|
2896 |
|
|
-- assignment(s): idc_sbrc_out
|
2897 |
|
|
-- replace(s): idc_sbrc
|
2898 |
|
|
|
2899 |
|
|
idc_sbrc_out_cml_out <= idc_sbrc_cml_3;
|
2900 |
|
|
idc_brbs_out <= idc_brbs;
|
2901 |
|
|
idc_brbc_out <= idc_brbc;
|
2902 |
|
|
-- SynEDA CoreMultiplier
|
2903 |
|
|
-- assignment(s): idc_reti_out
|
2904 |
|
|
-- replace(s): idc_reti
|
2905 |
|
|
|
2906 |
|
|
idc_reti_out_cml_out <= idc_reti_cml_3;
|
2907 |
|
|
|
2908 |
|
|
-- POST INCREMENT/PRE DECREMENT FOR THE X,Y,Z REGISTERS
|
2909 |
|
|
post_inc <= idc_psinc;
|
2910 |
|
|
-- SynEDA CoreMultiplier
|
2911 |
|
|
-- assignment(s): pre_dec
|
2912 |
|
|
-- replace(s): idc_prdec
|
2913 |
|
|
|
2914 |
|
|
pre_dec_cml_out <= idc_prdec_cml_1;
|
2915 |
|
|
-- SynEDA CoreMultiplier
|
2916 |
|
|
-- assignment(s): reg_h_wr
|
2917 |
|
|
-- replace(s): idc_ld_x, idc_ld_y, idc_ld_z, idc_st_x, idc_st_y, idc_st_z, idc_prdec
|
2918 |
|
|
|
2919 |
|
|
reg_h_wr_cml_out <= (idc_st_x_cml_3 or idc_st_y_cml_3 or idc_st_z_cml_3 or idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ld_z_cml_3) and (idc_psinc or idc_prdec_cml_3);
|
2920 |
|
|
|
2921 |
|
|
reg_h_adr(0)<= idc_st_x or idc_ld_x;
|
2922 |
|
|
reg_h_adr(1)<= idc_st_y or idc_std_y or idc_ld_y or idc_ldd_y;
|
2923 |
|
|
reg_h_adr(2)<= idc_st_z or idc_std_z or idc_ld_z or idc_ldd_z;
|
2924 |
|
|
|
2925 |
|
|
-- SynEDA CoreMultiplier
|
2926 |
|
|
-- assignment(s): sp_en
|
2927 |
|
|
-- replace(s): cpuwait, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti
|
2928 |
|
|
|
2929 |
|
|
-- SynEDA CoreMultiplier
|
2930 |
|
|
-- assignment(s): sp_ndown_up
|
2931 |
|
|
-- replace(s): cpuwait, ret_st1, reti_st1, idc_pop, idc_ret, idc_reti
|
2932 |
|
|
|
2933 |
|
|
-- STACK POINTER CONTROL
|
2934 |
|
|
sp_ndown_up_cml_out <= idc_pop_cml_3 or idc_ret_cml_3 or (ret_st1_cml_3 and not cpuwait_cml_3) or idc_reti_cml_3 or (reti_st1_cml_3 and not cpuwait_cml_3); -- ?????????
|
2935 |
|
|
sp_en_cml_out <= idc_push_cml_3 or idc_pop_cml_3 or idc_rcall_cml_3 or (rcall_st1_cml_3 and not cpuwait_cml_3) or idc_icall_cml_3 or (icall_st1_cml_3 and not cpuwait_cml_3) or
|
2936 |
|
|
idc_ret_cml_3 or (ret_st1_cml_3 and not cpuwait_cml_3) or idc_reti_cml_3 or (reti_st1_cml_3 and not cpuwait_cml_3) or
|
2937 |
|
|
call_st1_cml_3 or (call_st2_cml_3 and not cpuwait_cml_3) or irq_st1_cml_3 or (irq_st2_cml_3 and not cpuwait_cml_3); --????????
|
2938 |
|
|
|
2939 |
|
|
|
2940 |
|
|
branch <= dex_condition;
|
2941 |
|
|
bit_num_r_io <= cbi_sbi_bit_num_tmp when (cbi_st or sbi_st)='1' else dex_bitop_bitnum;
|
2942 |
|
|
|
2943 |
|
|
-- SynEDA CoreMultiplier
|
2944 |
|
|
-- assignment(s): adr
|
2945 |
|
|
-- replace(s): adr_int
|
2946 |
|
|
|
2947 |
|
|
adr_cml_out <= adr_int_cml_2;
|
2948 |
|
|
|
2949 |
|
|
ramre <= ramre_int;
|
2950 |
|
|
ramwe <= ramwe_int;
|
2951 |
|
|
|
2952 |
|
|
-- SynEDA CoreMultiplier
|
2953 |
|
|
-- assignment(s): iore
|
2954 |
|
|
-- replace(s): iore_int
|
2955 |
|
|
|
2956 |
|
|
iore_cml_out <= iore_int_cml_2;
|
2957 |
|
|
iowe <= iowe_int;
|
2958 |
|
|
|
2959 |
|
|
--dbusout <= dbusout_int;
|
2960 |
|
|
|
2961 |
|
|
-- Sleep Control
|
2962 |
|
|
sleepi <= idc_sleep;
|
2963 |
|
|
irqok <= irq_int;
|
2964 |
|
|
|
2965 |
|
|
-- Watchdog
|
2966 |
|
|
wdri <= idc_wdr;
|
2967 |
|
|
|
2968 |
|
|
-- ************************** JTAG OCD support ************************************
|
2969 |
|
|
|
2970 |
|
|
-- Change of flow
|
2971 |
|
|
change_flow <= '0';
|
2972 |
|
|
valid_instr <= '0';
|
2973 |
|
|
|
2974 |
|
|
|
2975 |
|
|
end RTL;
|