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tobil |
--************************************************************************************************
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-- "Bit processor" for AVR core
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-- Version 1.3(Special version for the JTAG OCD)
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-- Designed by Ruslan Lepetenok
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-- Modified 29.08.2003
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-- Unused inputs(sreg_bit_num[2..0],idc_sbi,idc_cbi,idc_bld) was removed.
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--************************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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entity bit_processor_cm3 is port(
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cp2_cml_1 : in std_logic;
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cp2_cml_2 : in std_logic;
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--Clock and reset
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cp2 : in std_logic;
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cp2en : in std_logic;
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ireset : in std_logic;
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bit_num_r_io : in std_logic_vector(2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS
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dbusin : in std_logic_vector(7 downto 0); -- SBI/CBI/SBIS/SBIC IN
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bitpr_io_out : out std_logic_vector(7 downto 0); -- SBI/CBI OUT
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sreg_out : in std_logic_vector(7 downto 0); -- BRBS/BRBC/BLD IN
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branch : in std_logic_vector(2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION
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bit_pr_sreg_out : out std_logic_vector(7 downto 0); -- BCLR/BSET/BST(T-FLAG ONLY)
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bld_op_out : out std_logic_vector(7 downto 0); -- BLD OUT (T FLAG)
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reg_rd_out : in std_logic_vector(7 downto 0); -- BST/SBRS/SBRC IN
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bit_test_op_out : out std_logic; -- OUTPUT OF SBIC/SBIS/SBRS/SBRC/BRBC/BRBS
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-- Instructions and states
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sbi_st : in std_logic;
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cbi_st : in std_logic;
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idc_bst : in std_logic;
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idc_bset : in std_logic;
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idc_bclr : in std_logic;
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idc_sbic : in std_logic;
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idc_sbis : in std_logic;
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idc_sbrs : in std_logic;
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idc_sbrc : in std_logic;
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idc_brbs : in std_logic;
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idc_brbc : in std_logic;
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idc_reti : in std_logic
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);
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end bit_processor_cm3;
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architecture RTL of bit_processor_cm3 is
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signal sreg_t_flag : std_logic; -- FOR BLD INSTRUCTION
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signal temp_in_data : std_logic_vector(7 downto 0);
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signal sreg_t_temp : std_logic_vector(7 downto 0);
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signal bit_num_decode : std_logic_vector(7 downto 0);
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signal bit_pr_sreg_out_int : std_logic_vector(7 downto 0);
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-- SBIS/SBIC/SBRS/SBRC SIGNALS
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signal bit_test_in : std_logic_vector(7 downto 0);
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signal bit_test_mux_out : std_logic_vector(7 downto 0);
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-- BRBS/BRBC SIGNALS
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signal branch_decode : std_logic_vector(7 downto 0);
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signal branch_mux : std_logic_vector(7 downto 0);
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signal bld_op_out_cml_out : std_logic_vector ( 7 downto 0 );
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signal bit_num_r_io_cml_1 : std_logic_vector ( 2 downto 0 );
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signal dbusin_cml_2 : std_logic_vector ( 7 downto 0 );
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signal sreg_out_cml_2 : std_logic_vector ( 7 downto 0 );
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signal sreg_out_cml_1 : std_logic_vector ( 7 downto 0 );
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signal reg_rd_out_cml_2 : std_logic_vector ( 7 downto 0 );
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signal bit_test_op_out_cml_out : std_logic;
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signal idc_sbic_cml_2 : std_logic;
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signal idc_sbis_cml_2 : std_logic;
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signal temp_in_data_cml_2 : std_logic_vector ( 7 downto 0 );
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signal temp_in_data_cml_1 : std_logic_vector ( 7 downto 0 );
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signal bit_num_decode_cml_2 : std_logic_vector ( 7 downto 0 );
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signal bit_num_decode_cml_1 : std_logic_vector ( 7 downto 0 );
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signal bit_test_in_cml_2 : std_logic_vector ( 7 downto 0 );
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begin
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process(cp2_cml_1) begin
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if (cp2_cml_1 = '1' and cp2_cml_1'event) then
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bit_num_r_io_cml_1 <= bit_num_r_io;
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sreg_out_cml_1 <= sreg_out;
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temp_in_data_cml_1 <= temp_in_data;
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bit_num_decode_cml_1 <= bit_num_decode;
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end if;
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end process;
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process(cp2_cml_2) begin
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if (cp2_cml_2 = '1' and cp2_cml_2'event) then
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dbusin_cml_2 <= dbusin;
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sreg_out_cml_2 <= sreg_out_cml_1;
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reg_rd_out_cml_2 <= reg_rd_out;
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idc_sbic_cml_2 <= idc_sbic;
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idc_sbis_cml_2 <= idc_sbis;
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temp_in_data_cml_2 <= temp_in_data_cml_1;
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bit_num_decode_cml_2 <= bit_num_decode_cml_1;
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bit_test_in_cml_2 <= bit_test_in;
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end if;
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end process;
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bld_op_out <= bld_op_out_cml_out;
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bit_test_op_out <= bit_test_op_out_cml_out;
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-- SynEDA CoreMultiplier
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-- assignment(s): sreg_t_flag
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-- replace(s): sreg_out
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sreg_t_flag <= sreg_out_cml_1(6);
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-- SynEDA CoreMultiplier
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-- assignment(s): temp_in_data
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-- replace(s): dbusin, temp_in_data
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-- SBI/CBI STORE REGISTER
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sbi_cbi:process(cp2,ireset)
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begin
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if ireset='0' then
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temp_in_data <= (others =>'0');
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elsif (cp2='1' and cp2'event) then temp_in_data <= temp_in_data_cml_2;
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if (cp2en='1') then -- Clock enable
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temp_in_data <= dbusin_cml_2;
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end if;
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end if;
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end process;
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sbi_cbi_logic:for i in dbusin'range generate
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bitpr_io_out(i) <= '1' when (sbi_st='1' and bit_num_decode(i)='1') else -- SBI
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'0' when (cbi_st='1' and bit_num_decode(i)='1') else -- CBI
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temp_in_data(i); -- ???
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end generate;
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-- ########################################################################################
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-- BST PART (LOAD T BIT OF SREG FROM THE GENERAL PURPOSE REGISTER)
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bit_num_decode_logic:for i in bit_num_decode'range generate
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bit_num_decode(i) <= '1' when (i=bit_num_r_io) else '0';
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end generate;
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sreg_t_temp(0) <= reg_rd_out_cml_2(0) when bit_num_decode_cml_2(0)='1' else '0';
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bld_logic:for i in 1 to 7 generate
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-- SynEDA CoreMultiplier
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-- assignment(s): sreg_t_temp
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-- replace(s): reg_rd_out, bit_num_decode
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sreg_t_temp(i)<= reg_rd_out_cml_2(i) when bit_num_decode_cml_2(i)='1' else sreg_t_temp(i-1);
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end generate;
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-- BLD LOGIC
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bld_inst:for i in reg_rd_out'range generate
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-- SynEDA CoreMultiplier
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-- assignment(s): bld_op_out
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-- replace(s): bit_num_r_io
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bld_op_out_cml_out(i) <= sreg_t_flag when (i=bit_num_r_io_cml_1) else reg_rd_out(i);
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end generate;
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-- ########################################################################################
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-- BCLR/BSET/BST/RETI LOGIC
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bclr_bset_logic:for i in 0 to 6 generate
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bit_pr_sreg_out_int(i) <= (idc_bset and not reg_rd_out_cml_2(i)) or (not idc_bclr and reg_rd_out_cml_2(i));
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end generate;
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-- SynEDA CoreMultiplier
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-- assignment(s): bit_pr_sreg_out_int
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-- replace(s): reg_rd_out
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-- SREG REGISTER BIT 7 - INTERRUPT ENABLE FLAG
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bit_pr_sreg_out_int(7) <= (idc_bset and not reg_rd_out_cml_2(7)) or (not idc_bclr and reg_rd_out_cml_2(7)) or idc_reti;
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bit_pr_sreg_out <= bit_pr_sreg_out_int(7)&sreg_t_temp(7)&bit_pr_sreg_out_int(5 downto 0) when (idc_bst='1')
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else bit_pr_sreg_out_int;
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-- SBIC/SBIS/SBRS/SBRC LOGIC
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bit_test_in <= dbusin when (idc_sbis='1' or idc_sbic='1') else reg_rd_out;
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bit_test_mux_out(0) <= bit_test_in_cml_2(0) when bit_num_decode_cml_2(0)='1' else '0';
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it_test_mux:for i in 1 to 7 generate
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-- SynEDA CoreMultiplier
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-- assignment(s): bit_test_mux_out
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-- replace(s): bit_num_decode, bit_test_in
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bit_test_mux_out(i)<= bit_test_in_cml_2(i) when bit_num_decode_cml_2(i)='1' else bit_test_mux_out(i-1);
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end generate;
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-- SynEDA CoreMultiplier
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-- assignment(s): bit_test_op_out
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-- replace(s): idc_sbic, idc_sbis
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bit_test_op_out_cml_out <= (bit_test_mux_out(7) and (idc_sbis_cml_2 or idc_sbrs)) or
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(not bit_test_mux_out(7) and (idc_sbic_cml_2 or idc_sbrc)) or
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(branch_mux(7) and idc_brbs) or
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(not branch_mux(7) and idc_brbc);
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-- BRBS/BRBC LOGIC
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branch_decode_logic:for i in branch_decode'range generate
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branch_decode(i) <= '1' when (i=branch) else '0';
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end generate;
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branch_mux(0) <= sreg_out_cml_2(0) when branch_decode(0)='1' else '0';
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branch_mux_logic:for i in 1 to 7 generate
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-- SynEDA CoreMultiplier
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-- assignment(s): branch_mux
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-- replace(s): sreg_out
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branch_mux(i)<= sreg_out_cml_2(i) when branch_decode(i)='1' else branch_mux(i-1);
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end generate;
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end RTL;
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