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tobil |
--************************************************************************************************
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-- ALU(internal module) for AVR core
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-- Version 1.2
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-- Designed by Ruslan Lepetenok
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-- Modified 02.08.2003
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-- (CPC/SBC/SBCI Z-flag bug found)
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-- H-flag with NEG instruction found
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--************************************************************************************************
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity alu_avr_cm4 is port(
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cp2_cml_1 : in std_logic;
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cp2_cml_2 : in std_logic;
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cp2_cml_3 : in std_logic;
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alu_data_r_in : in std_logic_vector(7 downto 0);
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alu_data_d_in : in std_logic_vector(7 downto 0);
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alu_c_flag_in : in std_logic;
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alu_z_flag_in : in std_logic;
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-- OPERATION SIGNALS INPUTS
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idc_add :in std_logic;
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idc_adc :in std_logic;
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idc_adiw :in std_logic;
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idc_sub :in std_logic;
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idc_subi :in std_logic;
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idc_sbc :in std_logic;
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idc_sbci :in std_logic;
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idc_sbiw :in std_logic;
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adiw_st : in std_logic;
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sbiw_st : in std_logic;
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idc_and :in std_logic;
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idc_andi :in std_logic;
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idc_or :in std_logic;
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idc_ori :in std_logic;
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idc_eor :in std_logic;
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idc_com :in std_logic;
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idc_neg :in std_logic;
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idc_inc :in std_logic;
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idc_dec :in std_logic;
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idc_cp :in std_logic;
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idc_cpc :in std_logic;
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idc_cpi :in std_logic;
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idc_cpse :in std_logic;
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idc_lsr :in std_logic;
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idc_ror :in std_logic;
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idc_asr :in std_logic;
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idc_swap :in std_logic;
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-- DATA OUTPUT
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alu_data_out : out std_logic_vector(7 downto 0);
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-- FLAGS OUTPUT
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alu_c_flag_out : out std_logic;
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alu_z_flag_out : out std_logic;
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alu_n_flag_out : out std_logic;
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alu_v_flag_out : out std_logic;
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alu_s_flag_out : out std_logic;
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alu_h_flag_out : out std_logic
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);
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end alu_avr_cm4;
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architecture rtl of alu_avr_cm4 is
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-- ####################################################
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-- INTERNAL SIGNALS
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-- ####################################################
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signal alu_data_out_int : std_logic_vector (7 downto 0);
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-- ALU FLAGS (INTERNAL)
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signal alu_z_flag_out_int : std_logic;
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signal alu_c_flag_in_int : std_logic; -- INTERNAL CARRY FLAG
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signal alu_n_flag_out_int : std_logic;
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signal alu_v_flag_out_int : std_logic;
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signal alu_c_flag_out_int : std_logic;
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-- ADDER SIGNALS --
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signal adder_nadd_sub : std_logic; -- 0 -> ADD ,1 -> SUB
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signal adder_v_flag_out : std_logic;
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signal adder_carry : std_logic_vector(8 downto 0);
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signal adder_d_in : std_logic_vector(8 downto 0);
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signal adder_r_in : std_logic_vector(8 downto 0);
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signal adder_out : std_logic_vector(8 downto 0);
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-- NEG OPERATOR SIGNALS
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signal neg_op_in : std_logic_vector(7 downto 0);
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signal neg_op_carry : std_logic_vector(8 downto 0);
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signal neg_op_out : std_logic_vector(8 downto 0);
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-- INC, DEC OPERATOR SIGNALS
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signal incdec_op_in : std_logic_vector (7 downto 0);
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signal incdec_op_carry : std_logic_vector(7 downto 0);
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signal incdec_op_out : std_logic_vector(7 downto 0);
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signal com_op_out : std_logic_vector(7 downto 0);
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signal and_op_out : std_logic_vector(7 downto 0);
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signal or_op_out : std_logic_vector(7 downto 0);
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signal eor_op_out : std_logic_vector(7 downto 0);
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-- SHIFT SIGNALS
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signal right_shift_out : std_logic_vector(7 downto 0);
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-- SWAP SIGNALS
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signal swap_out : std_logic_vector(7 downto 0);
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signal alu_data_r_in_cml_2 : std_logic_vector ( 7 downto 0 );
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signal alu_data_r_in_cml_1 : std_logic_vector ( 7 downto 0 );
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signal alu_data_d_in_cml_3 : std_logic_vector ( 7 downto 0 );
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signal alu_data_d_in_cml_2 : std_logic_vector ( 7 downto 0 );
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signal alu_h_flag_out_cml_out : std_logic;
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signal idc_add_cml_3 : std_logic;
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signal idc_add_cml_2 : std_logic;
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signal idc_adc_cml_3 : std_logic;
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signal idc_adc_cml_2 : std_logic;
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signal idc_adc_cml_1 : std_logic;
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signal idc_adiw_cml_2 : std_logic;
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signal idc_sub_cml_3 : std_logic;
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signal idc_sub_cml_2 : std_logic;
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signal idc_sub_cml_1 : std_logic;
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signal idc_subi_cml_3 : std_logic;
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signal idc_subi_cml_2 : std_logic;
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signal idc_subi_cml_1 : std_logic;
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signal alu_z_flag_out_cml_out : std_logic;
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signal idc_sbc_cml_3 : std_logic;
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signal idc_sbc_cml_2 : std_logic;
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signal idc_sbc_cml_1 : std_logic;
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signal idc_sbci_cml_3 : std_logic;
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signal idc_sbci_cml_2 : std_logic;
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signal idc_sbci_cml_1 : std_logic;
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signal idc_sbiw_cml_2 : std_logic;
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signal idc_sbiw_cml_1 : std_logic;
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signal adiw_st_cml_3 : std_logic;
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signal adiw_st_cml_2 : std_logic;
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signal adiw_st_cml_1 : std_logic;
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signal sbiw_st_cml_3 : std_logic;
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signal sbiw_st_cml_2 : std_logic;
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signal sbiw_st_cml_1 : std_logic;
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signal idc_and_cml_2 : std_logic;
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signal idc_andi_cml_2 : std_logic;
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signal idc_or_cml_2 : std_logic;
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signal idc_ori_cml_2 : std_logic;
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signal idc_eor_cml_2 : std_logic;
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signal idc_com_cml_2 : std_logic;
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signal idc_neg_cml_3 : std_logic;
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signal idc_neg_cml_2 : std_logic;
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signal idc_inc_cml_3 : std_logic;
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signal idc_inc_cml_2 : std_logic;
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signal idc_dec_cml_3 : std_logic;
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signal idc_dec_cml_2 : std_logic;
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signal idc_cp_cml_3 : std_logic;
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signal idc_cp_cml_2 : std_logic;
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signal idc_cp_cml_1 : std_logic;
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signal idc_cpc_cml_3 : std_logic;
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signal idc_cpc_cml_2 : std_logic;
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signal idc_cpc_cml_1 : std_logic;
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signal idc_cpi_cml_3 : std_logic;
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signal idc_cpi_cml_2 : std_logic;
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signal idc_cpi_cml_1 : std_logic;
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signal idc_cpse_cml_2 : std_logic;
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signal idc_cpse_cml_1 : std_logic;
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signal idc_lsr_cml_3 : std_logic;
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signal idc_lsr_cml_2 : std_logic;
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signal idc_ror_cml_3 : std_logic;
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signal idc_ror_cml_2 : std_logic;
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signal idc_ror_cml_1 : std_logic;
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signal idc_asr_cml_3 : std_logic;
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signal idc_asr_cml_2 : std_logic;
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signal idc_swap_cml_2 : std_logic;
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signal alu_data_out_int_cml_3 : std_logic_vector ( 7 downto 0 );
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signal alu_c_flag_in_int_cml_2 : std_logic;
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signal alu_c_flag_in_int_cml_1 : std_logic;
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signal alu_c_flag_out_cml_out : std_logic;
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signal alu_c_flag_out_int_cml_3 : std_logic;
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signal adder_nadd_sub_cml_3 : std_logic;
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signal adder_nadd_sub_cml_2 : std_logic;
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signal adder_carry_cml_3 : std_logic_vector ( 8 downto 0 );
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signal adder_d_in_cml_3 : std_logic_vector ( 8 downto 0 );
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signal adder_d_in_cml_2 : std_logic_vector ( 8 downto 0 );
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signal adder_r_in_cml_3 : std_logic_vector ( 8 downto 0 );
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signal adder_r_in_cml_2 : std_logic_vector ( 8 downto 0 );
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signal adder_out_cml_3 : std_logic_vector ( 8 downto 0 );
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signal neg_op_carry_cml_3 : std_logic_vector ( 8 downto 0 );
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signal incdec_op_carry_cml_3 : std_logic_vector ( 7 downto 0 );
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signal right_shift_out_cml_2 : std_logic_vector ( 7 downto 0 );
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signal swap_out_cml_2 : std_logic_vector ( 7 downto 0 );
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begin
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process(cp2_cml_1) begin
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if (cp2_cml_1 = '1' and cp2_cml_1'event) then
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alu_data_r_in_cml_1 <= alu_data_r_in;
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idc_adc_cml_1 <= idc_adc;
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idc_sub_cml_1 <= idc_sub;
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idc_subi_cml_1 <= idc_subi;
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idc_sbc_cml_1 <= idc_sbc;
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idc_sbci_cml_1 <= idc_sbci;
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idc_sbiw_cml_1 <= idc_sbiw;
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adiw_st_cml_1 <= adiw_st;
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sbiw_st_cml_1 <= sbiw_st;
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idc_cp_cml_1 <= idc_cp;
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idc_cpc_cml_1 <= idc_cpc;
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idc_cpi_cml_1 <= idc_cpi;
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idc_cpse_cml_1 <= idc_cpse;
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idc_ror_cml_1 <= idc_ror;
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alu_c_flag_in_int_cml_1 <= alu_c_flag_in_int;
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end if;
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end process;
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process(cp2_cml_2) begin
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if (cp2_cml_2 = '1' and cp2_cml_2'event) then
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alu_data_r_in_cml_2 <= alu_data_r_in_cml_1;
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alu_data_d_in_cml_2 <= alu_data_d_in;
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idc_add_cml_2 <= idc_add;
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idc_adc_cml_2 <= idc_adc_cml_1;
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idc_adiw_cml_2 <= idc_adiw;
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idc_sub_cml_2 <= idc_sub_cml_1;
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idc_subi_cml_2 <= idc_subi_cml_1;
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idc_sbc_cml_2 <= idc_sbc_cml_1;
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idc_sbci_cml_2 <= idc_sbci_cml_1;
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idc_sbiw_cml_2 <= idc_sbiw_cml_1;
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adiw_st_cml_2 <= adiw_st_cml_1;
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sbiw_st_cml_2 <= sbiw_st_cml_1;
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idc_and_cml_2 <= idc_and;
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idc_andi_cml_2 <= idc_andi;
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idc_or_cml_2 <= idc_or;
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idc_ori_cml_2 <= idc_ori;
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idc_eor_cml_2 <= idc_eor;
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idc_com_cml_2 <= idc_com;
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idc_neg_cml_2 <= idc_neg;
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idc_inc_cml_2 <= idc_inc;
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idc_dec_cml_2 <= idc_dec;
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idc_cp_cml_2 <= idc_cp_cml_1;
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idc_cpc_cml_2 <= idc_cpc_cml_1;
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idc_cpi_cml_2 <= idc_cpi_cml_1;
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idc_cpse_cml_2 <= idc_cpse_cml_1;
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idc_lsr_cml_2 <= idc_lsr;
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idc_ror_cml_2 <= idc_ror_cml_1;
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idc_asr_cml_2 <= idc_asr;
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idc_swap_cml_2 <= idc_swap;
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alu_c_flag_in_int_cml_2 <= alu_c_flag_in_int_cml_1;
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adder_nadd_sub_cml_2 <= adder_nadd_sub;
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adder_d_in_cml_2 <= adder_d_in;
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adder_r_in_cml_2 <= adder_r_in;
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right_shift_out_cml_2 <= right_shift_out;
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swap_out_cml_2 <= swap_out;
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end if;
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end process;
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process(cp2_cml_3) begin
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if (cp2_cml_3 = '1' and cp2_cml_3'event) then
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alu_data_d_in_cml_3 <= alu_data_d_in_cml_2;
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idc_add_cml_3 <= idc_add_cml_2;
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idc_adc_cml_3 <= idc_adc_cml_2;
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idc_sub_cml_3 <= idc_sub_cml_2;
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idc_subi_cml_3 <= idc_subi_cml_2;
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idc_sbc_cml_3 <= idc_sbc_cml_2;
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idc_sbci_cml_3 <= idc_sbci_cml_2;
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adiw_st_cml_3 <= adiw_st_cml_2;
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sbiw_st_cml_3 <= sbiw_st_cml_2;
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idc_neg_cml_3 <= idc_neg_cml_2;
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idc_inc_cml_3 <= idc_inc_cml_2;
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idc_dec_cml_3 <= idc_dec_cml_2;
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idc_cp_cml_3 <= idc_cp_cml_2;
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idc_cpc_cml_3 <= idc_cpc_cml_2;
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idc_cpi_cml_3 <= idc_cpi_cml_2;
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idc_lsr_cml_3 <= idc_lsr_cml_2;
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idc_ror_cml_3 <= idc_ror_cml_2;
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idc_asr_cml_3 <= idc_asr_cml_2;
|
288 |
|
|
alu_data_out_int_cml_3 <= alu_data_out_int;
|
289 |
|
|
alu_c_flag_out_int_cml_3 <= alu_c_flag_out_int;
|
290 |
|
|
adder_nadd_sub_cml_3 <= adder_nadd_sub_cml_2;
|
291 |
|
|
adder_carry_cml_3 <= adder_carry;
|
292 |
|
|
adder_d_in_cml_3 <= adder_d_in_cml_2;
|
293 |
|
|
adder_r_in_cml_3 <= adder_r_in_cml_2;
|
294 |
|
|
adder_out_cml_3 <= adder_out;
|
295 |
|
|
neg_op_carry_cml_3 <= neg_op_carry;
|
296 |
|
|
incdec_op_carry_cml_3 <= incdec_op_carry;
|
297 |
|
|
end if;
|
298 |
|
|
end process;
|
299 |
|
|
alu_h_flag_out <= alu_h_flag_out_cml_out;
|
300 |
|
|
alu_z_flag_out <= alu_z_flag_out_cml_out;
|
301 |
|
|
alu_c_flag_out <= alu_c_flag_out_cml_out;
|
302 |
|
|
|
303 |
|
|
|
304 |
|
|
|
305 |
|
|
-- ########################################################################
|
306 |
|
|
-- ############### ALU
|
307 |
|
|
-- ########################################################################
|
308 |
|
|
|
309 |
|
|
-- SynEDA CoreMultiplier
|
310 |
|
|
-- assignment(s): adder_nadd_sub
|
311 |
|
|
-- replace(s): idc_sub, idc_subi, idc_sbc, idc_sbci, idc_sbiw, sbiw_st, idc_cp, idc_cpc, idc_cpi, idc_cpse
|
312 |
|
|
|
313 |
|
|
adder_nadd_sub <=(idc_sub_cml_1 or idc_subi_cml_1 or idc_sbc_cml_1 or idc_sbci_cml_1 or idc_sbiw_cml_1 or sbiw_st_cml_1 or
|
314 |
|
|
idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1 or idc_cpse_cml_1 ); -- '0' -> '+'; '1' -> '-'
|
315 |
|
|
|
316 |
|
|
-- SREG C FLAG (ALU INPUT)
|
317 |
|
|
alu_c_flag_in_int <= alu_c_flag_in and
|
318 |
|
|
(idc_adc or adiw_st or idc_sbc or idc_sbci or sbiw_st or
|
319 |
|
|
idc_cpc or
|
320 |
|
|
idc_ror);
|
321 |
|
|
|
322 |
|
|
-- SynEDA CoreMultiplier
|
323 |
|
|
-- assignment(s): alu_z_flag_out
|
324 |
|
|
-- replace(s): idc_sbc, idc_sbci, adiw_st, sbiw_st, idc_cpc
|
325 |
|
|
|
326 |
|
|
-- SREG Z FLAG ()
|
327 |
|
|
-- alu_z_flag_out <= (alu_z_flag_out_int and not(adiw_st or sbiw_st)) or
|
328 |
|
|
-- ((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st or sbiw_st));
|
329 |
|
|
alu_z_flag_out_cml_out <= (alu_z_flag_out_int and not(adiw_st_cml_2 or sbiw_st_cml_2 or idc_cpc_cml_2 or idc_sbc_cml_2 or idc_sbci_cml_2)) or
|
330 |
|
|
((alu_z_flag_in and alu_z_flag_out_int) and (adiw_st_cml_2 or sbiw_st_cml_2))or
|
331 |
|
|
(alu_z_flag_in and alu_z_flag_out_int and(idc_cpc_cml_2 or idc_sbc_cml_2 or idc_sbci_cml_2)); -- Previous value (for CPC/SBC/SBCI instructions)
|
332 |
|
|
|
333 |
|
|
-- SREG N FLAG
|
334 |
|
|
alu_n_flag_out <= alu_n_flag_out_int;
|
335 |
|
|
|
336 |
|
|
-- SREG V FLAG
|
337 |
|
|
alu_v_flag_out <= alu_v_flag_out_int;
|
338 |
|
|
|
339 |
|
|
|
340 |
|
|
-- SynEDA CoreMultiplier
|
341 |
|
|
-- assignment(s): alu_c_flag_out
|
342 |
|
|
-- replace(s): alu_c_flag_out_int
|
343 |
|
|
|
344 |
|
|
alu_c_flag_out_cml_out <= alu_c_flag_out_int_cml_3;
|
345 |
|
|
|
346 |
|
|
alu_data_out <= alu_data_out_int;
|
347 |
|
|
|
348 |
|
|
-- #########################################################################################
|
349 |
|
|
|
350 |
|
|
adder_d_in <= '0'&alu_data_d_in;
|
351 |
|
|
-- SynEDA CoreMultiplier
|
352 |
|
|
-- assignment(s): adder_r_in
|
353 |
|
|
-- replace(s): alu_data_r_in
|
354 |
|
|
|
355 |
|
|
adder_r_in <= '0'&alu_data_r_in_cml_1;
|
356 |
|
|
|
357 |
|
|
--########################## ADDEER ###################################
|
358 |
|
|
|
359 |
|
|
adder_out(0) <= adder_d_in_cml_2(0) xor adder_r_in_cml_2(0) xor alu_c_flag_in_int_cml_2;
|
360 |
|
|
|
361 |
|
|
summator:for i in 1 to 8 generate
|
362 |
|
|
-- SynEDA CoreMultiplier
|
363 |
|
|
-- assignment(s): adder_out
|
364 |
|
|
-- replace(s): alu_c_flag_in_int, adder_d_in, adder_r_in
|
365 |
|
|
|
366 |
|
|
adder_out(i) <= adder_d_in_cml_2(i) xor adder_r_in_cml_2(i) xor adder_carry(i-1);
|
367 |
|
|
end generate;
|
368 |
|
|
|
369 |
|
|
|
370 |
|
|
adder_carry(0) <= ((adder_d_in_cml_2(0) xor adder_nadd_sub_cml_2) and adder_r_in_cml_2(0)) or
|
371 |
|
|
(((adder_d_in_cml_2(0) xor adder_nadd_sub_cml_2) or adder_r_in_cml_2(0)) and alu_c_flag_in_int_cml_2);
|
372 |
|
|
|
373 |
|
|
summator2:for i in 1 to 8 generate
|
374 |
|
|
-- SynEDA CoreMultiplier
|
375 |
|
|
-- assignment(s): adder_carry
|
376 |
|
|
-- replace(s): alu_c_flag_in_int, adder_nadd_sub, adder_d_in, adder_r_in
|
377 |
|
|
|
378 |
|
|
adder_carry(i) <= ((adder_d_in_cml_2(i) xor adder_nadd_sub_cml_2) and adder_r_in_cml_2(i)) or
|
379 |
|
|
(((adder_d_in_cml_2(i) xor adder_nadd_sub_cml_2) or adder_r_in_cml_2(i)) and adder_carry(i-1));
|
380 |
|
|
end generate;
|
381 |
|
|
|
382 |
|
|
-- FLAGS FOR ADDER INSTRUCTIONS:
|
383 |
|
|
-- CARRY FLAG (C) -> adder_out(8)
|
384 |
|
|
-- HALF CARRY FLAG (H) -> adder_carry(3)
|
385 |
|
|
-- TOW'S COMPLEMENT OVERFLOW (V) ->
|
386 |
|
|
|
387 |
|
|
-- SynEDA CoreMultiplier
|
388 |
|
|
-- assignment(s): adder_v_flag_out
|
389 |
|
|
-- replace(s): adder_nadd_sub, adder_d_in, adder_r_in, adder_out
|
390 |
|
|
|
391 |
|
|
adder_v_flag_out <= (((adder_d_in_cml_3(7) and adder_r_in_cml_3(7) and not adder_out_cml_3(7)) or
|
392 |
|
|
(not adder_d_in_cml_3(7) and not adder_r_in_cml_3(7) and adder_out_cml_3(7))) and not adder_nadd_sub_cml_3) or -- ADD
|
393 |
|
|
(((adder_d_in_cml_3(7) and not adder_r_in_cml_3(7) and not adder_out_cml_3(7)) or
|
394 |
|
|
(not adder_d_in_cml_3(7) and adder_r_in_cml_3(7) and adder_out_cml_3(7))) and adder_nadd_sub_cml_3);
|
395 |
|
|
-- SUB
|
396 |
|
|
--#####################################################################
|
397 |
|
|
|
398 |
|
|
|
399 |
|
|
-- LOGICAL OPERATIONS FOR ONE OPERAND
|
400 |
|
|
|
401 |
|
|
--########################## NEG OPERATION ####################
|
402 |
|
|
|
403 |
|
|
neg_op_out(0) <= not alu_data_d_in_cml_2(0) xor '1';
|
404 |
|
|
neg_op:for i in 1 to 7 generate
|
405 |
|
|
neg_op_out(i) <= not alu_data_d_in_cml_2(i) xor neg_op_carry(i-1);
|
406 |
|
|
end generate;
|
407 |
|
|
-- SynEDA CoreMultiplier
|
408 |
|
|
-- assignment(s): neg_op_out
|
409 |
|
|
-- replace(s): alu_data_d_in
|
410 |
|
|
|
411 |
|
|
neg_op_out(8) <= neg_op_carry(7) xor '1';
|
412 |
|
|
|
413 |
|
|
|
414 |
|
|
neg_op_carry(0) <= not alu_data_d_in_cml_2(0) and '1';
|
415 |
|
|
neg_op2:for i in 1 to 7 generate
|
416 |
|
|
neg_op_carry(i) <= not alu_data_d_in_cml_2(i) and neg_op_carry(i-1);
|
417 |
|
|
end generate;
|
418 |
|
|
-- SynEDA CoreMultiplier
|
419 |
|
|
-- assignment(s): neg_op_carry
|
420 |
|
|
-- replace(s): alu_data_d_in
|
421 |
|
|
|
422 |
|
|
neg_op_carry(8) <= neg_op_carry(7); -- ??!!
|
423 |
|
|
|
424 |
|
|
|
425 |
|
|
-- CARRY FLAGS FOR NEG INSTRUCTION:
|
426 |
|
|
-- CARRY FLAG -> neg_op_out(8)
|
427 |
|
|
-- HALF CARRY FLAG -> neg_op_carry(3)
|
428 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG -> alu_data_d_in(7) and neg_op_carry(6)
|
429 |
|
|
--############################################################################
|
430 |
|
|
|
431 |
|
|
|
432 |
|
|
--########################## INC, DEC OPERATIONS ####################
|
433 |
|
|
|
434 |
|
|
incdec_op_out(0) <= alu_data_d_in_cml_2(0) xor '1';
|
435 |
|
|
inc_dec:for i in 1 to 7 generate
|
436 |
|
|
-- SynEDA CoreMultiplier
|
437 |
|
|
-- assignment(s): incdec_op_out
|
438 |
|
|
-- replace(s): alu_data_d_in
|
439 |
|
|
|
440 |
|
|
incdec_op_out(i) <= alu_data_d_in_cml_2(i) xor incdec_op_carry(i-1);
|
441 |
|
|
end generate;
|
442 |
|
|
|
443 |
|
|
|
444 |
|
|
incdec_op_carry(0) <= alu_data_d_in_cml_2(0) xor idc_dec_cml_2;
|
445 |
|
|
inc_dec2:for i in 1 to 7 generate
|
446 |
|
|
-- SynEDA CoreMultiplier
|
447 |
|
|
-- assignment(s): incdec_op_carry
|
448 |
|
|
-- replace(s): alu_data_d_in, idc_dec
|
449 |
|
|
|
450 |
|
|
incdec_op_carry(i) <= (alu_data_d_in_cml_2(i) xor idc_dec_cml_2) and incdec_op_carry(i-1);
|
451 |
|
|
end generate;
|
452 |
|
|
|
453 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG -> (alu_data_d_in(7) xor idc_dec) and incdec_op_carry(6)
|
454 |
|
|
--####################################################################
|
455 |
|
|
|
456 |
|
|
|
457 |
|
|
-- SynEDA CoreMultiplier
|
458 |
|
|
-- assignment(s): com_op_out
|
459 |
|
|
-- replace(s): alu_data_d_in
|
460 |
|
|
|
461 |
|
|
--########################## COM OPERATION ###################################
|
462 |
|
|
com_op_out <= not alu_data_d_in_cml_2;
|
463 |
|
|
-- FLAGS
|
464 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
|
465 |
|
|
-- CARRY FLAG (C) -> '1'
|
466 |
|
|
--############################################################################
|
467 |
|
|
|
468 |
|
|
-- LOGICAL OPERATIONS FOR TWO OPERANDS
|
469 |
|
|
|
470 |
|
|
-- SynEDA CoreMultiplier
|
471 |
|
|
-- assignment(s): and_op_out
|
472 |
|
|
-- replace(s): alu_data_r_in, alu_data_d_in
|
473 |
|
|
|
474 |
|
|
--########################## AND OPERATION ###################################
|
475 |
|
|
and_op_out <= alu_data_d_in_cml_2 and alu_data_r_in_cml_2;
|
476 |
|
|
-- FLAGS
|
477 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
|
478 |
|
|
--############################################################################
|
479 |
|
|
|
480 |
|
|
-- SynEDA CoreMultiplier
|
481 |
|
|
-- assignment(s): or_op_out
|
482 |
|
|
-- replace(s): alu_data_r_in, alu_data_d_in
|
483 |
|
|
|
484 |
|
|
--########################## OR OPERATION ###################################
|
485 |
|
|
or_op_out <= alu_data_d_in_cml_2 or alu_data_r_in_cml_2;
|
486 |
|
|
-- FLAGS
|
487 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
|
488 |
|
|
--############################################################################
|
489 |
|
|
|
490 |
|
|
-- SynEDA CoreMultiplier
|
491 |
|
|
-- assignment(s): eor_op_out
|
492 |
|
|
-- replace(s): alu_data_r_in, alu_data_d_in
|
493 |
|
|
|
494 |
|
|
--########################## EOR OPERATION ###################################
|
495 |
|
|
eor_op_out <= alu_data_d_in_cml_2 xor alu_data_r_in_cml_2;
|
496 |
|
|
-- FLAGS
|
497 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> '0'
|
498 |
|
|
--############################################################################
|
499 |
|
|
|
500 |
|
|
-- SHIFT OPERATIONS
|
501 |
|
|
|
502 |
|
|
-- ########################## RIGHT(LSR, ROR, ASR) #######################
|
503 |
|
|
|
504 |
|
|
right_shift_out(7) <= (idc_ror_cml_1 and alu_c_flag_in_int_cml_1) or (idc_asr and alu_data_d_in(7)); -- right_shift_out(7)
|
505 |
|
|
shift_right:for i in 6 downto 0 generate
|
506 |
|
|
-- SynEDA CoreMultiplier
|
507 |
|
|
-- assignment(s): right_shift_out
|
508 |
|
|
-- replace(s): idc_ror, alu_c_flag_in_int
|
509 |
|
|
|
510 |
|
|
right_shift_out(i) <= alu_data_d_in(i+1);
|
511 |
|
|
end generate;
|
512 |
|
|
|
513 |
|
|
-- FLAGS
|
514 |
|
|
-- CARRY FLAG (C) -> alu_data_d_in(0)
|
515 |
|
|
-- NEGATIVE FLAG (N) -> right_shift_out(7)
|
516 |
|
|
-- TOW's COMPLEMENT OVERFLOW FLAG (V) -> N xor C (left_shift_out(7) xor alu_data_d_in(0))
|
517 |
|
|
|
518 |
|
|
-- #######################################################################
|
519 |
|
|
|
520 |
|
|
|
521 |
|
|
-- ################################## SWAP ###############################
|
522 |
|
|
|
523 |
|
|
swap_h:for i in 7 downto 4 generate
|
524 |
|
|
swap_out(i) <= alu_data_d_in(i-4);
|
525 |
|
|
end generate;
|
526 |
|
|
swap_l:for i in 3 downto 0 generate
|
527 |
|
|
swap_out(i) <= alu_data_d_in(i+4);
|
528 |
|
|
end generate;
|
529 |
|
|
-- #######################################################################
|
530 |
|
|
|
531 |
|
|
-- ALU OUTPUT MUX
|
532 |
|
|
|
533 |
|
|
alu_data_out_mux:for i in alu_data_out_int'range generate
|
534 |
|
|
-- SynEDA CoreMultiplier
|
535 |
|
|
-- assignment(s): alu_data_out_int
|
536 |
|
|
-- replace(s): idc_add, idc_adc, idc_adiw, idc_sub, idc_subi, idc_sbc, idc_sbci, idc_sbiw, adiw_st, sbiw_st, idc_and, idc_andi, idc_or, idc_ori, idc_eor, idc_com, idc_neg, idc_inc, idc_dec, idc_cp, idc_cpc, idc_cpi, idc_cpse, idc_lsr, idc_ror, idc_asr, idc_swap, right_shift_out, swap_out
|
537 |
|
|
|
538 |
|
|
alu_data_out_int(i) <= (adder_out(i) and (idc_add_cml_2 or idc_adc_cml_2 or (idc_adiw_cml_2 or adiw_st_cml_2) or -- !!!!!
|
539 |
|
|
idc_sub_cml_2 or idc_subi_cml_2 or idc_sbc_cml_2 or idc_sbci_cml_2 or
|
540 |
|
|
(idc_sbiw_cml_2 or sbiw_st_cml_2) or -- !!!!!
|
541 |
|
|
idc_cpse_cml_2 or idc_cp_cml_2 or idc_cpc_cml_2 or idc_cpi_cml_2)) or
|
542 |
|
|
(neg_op_out(i) and idc_neg_cml_2) or -- NEG
|
543 |
|
|
(incdec_op_out(i) and (idc_inc_cml_2 or idc_dec_cml_2)) or -- INC/DEC
|
544 |
|
|
(com_op_out(i) and idc_com_cml_2) or -- COM
|
545 |
|
|
(and_op_out(i) and (idc_and_cml_2 or idc_andi_cml_2)) or -- AND/ANDI
|
546 |
|
|
(or_op_out(i) and (idc_or_cml_2 or idc_ori_cml_2)) or -- OR/ORI
|
547 |
|
|
(eor_op_out(i) and idc_eor_cml_2) or -- EOR
|
548 |
|
|
(right_shift_out_cml_2(i) and (idc_lsr_cml_2 or idc_ror_cml_2 or idc_asr_cml_2)) or -- LSR/ROR/ASR
|
549 |
|
|
(swap_out_cml_2(i) and idc_swap_cml_2); -- SWAP
|
550 |
|
|
|
551 |
|
|
|
552 |
|
|
end generate;
|
553 |
|
|
|
554 |
|
|
--@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ALU FLAGS OUTPUTS @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
|
555 |
|
|
|
556 |
|
|
-- SynEDA CoreMultiplier
|
557 |
|
|
-- assignment(s): alu_h_flag_out
|
558 |
|
|
-- replace(s): idc_add, idc_adc, idc_sub, idc_subi, idc_sbc, idc_sbci, idc_neg, idc_cp, idc_cpc, idc_cpi, adder_carry, neg_op_carry
|
559 |
|
|
|
560 |
|
|
alu_h_flag_out_cml_out <= (adder_carry_cml_3(3) and -- ADDER INSTRUCTIONS
|
561 |
|
|
(idc_add_cml_3 or idc_adc_cml_3 or idc_sub_cml_3 or idc_subi_cml_3 or idc_sbc_cml_3 or idc_sbci_cml_3 or idc_cp_cml_3 or idc_cpc_cml_3 or idc_cpi_cml_3)) or
|
562 |
|
|
(not neg_op_carry_cml_3(3) and idc_neg_cml_3); -- H-flag problem with NEG instruction fixing -- NEG
|
563 |
|
|
|
564 |
|
|
|
565 |
|
|
alu_s_flag_out <= alu_n_flag_out_int xor alu_v_flag_out_int;
|
566 |
|
|
|
567 |
|
|
-- SynEDA CoreMultiplier
|
568 |
|
|
-- assignment(s): alu_v_flag_out_int
|
569 |
|
|
-- replace(s): alu_data_d_in, idc_add, idc_adc, idc_sub, idc_subi, idc_sbc, idc_sbci, adiw_st, sbiw_st, idc_neg, idc_inc, idc_dec, idc_cp, idc_cpc, idc_cpi, idc_lsr, idc_ror, idc_asr, alu_c_flag_out_int, neg_op_carry, incdec_op_carry
|
570 |
|
|
|
571 |
|
|
alu_v_flag_out_int <= (adder_v_flag_out and
|
572 |
|
|
(idc_add_cml_3 or idc_adc_cml_3 or idc_sub_cml_3 or idc_subi_cml_3 or idc_sbc_cml_3 or idc_sbci_cml_3 or adiw_st_cml_3 or sbiw_st_cml_3 or idc_cp_cml_3 or idc_cpi_cml_3 or idc_cpc_cml_3)) or
|
573 |
|
|
((alu_data_d_in_cml_3(7) and neg_op_carry_cml_3(6)) and idc_neg_cml_3) or -- NEG
|
574 |
|
|
(not alu_data_d_in_cml_3(7) and incdec_op_carry_cml_3(6) and idc_inc_cml_3) or -- INC
|
575 |
|
|
(alu_data_d_in_cml_3(7) and incdec_op_carry_cml_3(6) and idc_dec_cml_3) or -- DEC
|
576 |
|
|
((alu_n_flag_out_int xor alu_c_flag_out_int_cml_3) and (idc_lsr_cml_3 or idc_ror_cml_3 or idc_asr_cml_3)); -- LSR,ROR,ASR
|
577 |
|
|
|
578 |
|
|
|
579 |
|
|
-- SynEDA CoreMultiplier
|
580 |
|
|
-- assignment(s): alu_n_flag_out_int
|
581 |
|
|
-- replace(s): alu_data_out_int
|
582 |
|
|
|
583 |
|
|
alu_n_flag_out_int <= alu_data_out_int_cml_3(7);
|
584 |
|
|
|
585 |
|
|
alu_z_flag_out_int <= '1' when alu_data_out_int="00000000" else '0';
|
586 |
|
|
|
587 |
|
|
-- SynEDA CoreMultiplier
|
588 |
|
|
-- assignment(s): alu_c_flag_out_int
|
589 |
|
|
-- replace(s): alu_data_d_in, idc_add, idc_adc, idc_adiw, idc_sub, idc_subi, idc_sbc, idc_sbci, idc_sbiw, adiw_st, sbiw_st, idc_com, idc_neg, idc_cp, idc_cpc, idc_cpi, idc_lsr, idc_ror, idc_asr
|
590 |
|
|
|
591 |
|
|
alu_c_flag_out_int <= (adder_out(8) and
|
592 |
|
|
(idc_add_cml_2 or idc_adc_cml_2 or (idc_adiw_cml_2 or adiw_st_cml_2) or idc_sub_cml_2 or idc_subi_cml_2 or idc_sbc_cml_2 or idc_sbci_cml_2 or (idc_sbiw_cml_2 or sbiw_st_cml_2) or idc_cp_cml_2 or idc_cpc_cml_2 or idc_cpi_cml_2)) or -- ADDER
|
593 |
|
|
(not alu_z_flag_out_int and idc_neg_cml_2) or -- NEG
|
594 |
|
|
(alu_data_d_in_cml_2(0) and (idc_lsr_cml_2 or idc_ror_cml_2 or idc_asr_cml_2)) or idc_com_cml_2;
|
595 |
|
|
|
596 |
|
|
-- @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
|
597 |
|
|
|
598 |
|
|
|
599 |
|
|
end rtl;
|