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[/] [avr_hp/] [trunk/] [rtl/] [rtl_v5_cm4/] [pm_fetch_dec.vhd] - Blame information for rev 2

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1 2 tobil 
--************************************************************************************************
2 
--  PM_FETCH_DEC(internal module) for AVR core
3 
--      Version 2.6! (Special version for the JTAG OCD)
4 
--  Designed by Ruslan Lepetenok 14.11.2001
5 
--  Modified 31.05.06
6 
--  Modification:
7 
--  Registered ramre/ramwe outputs
8 
--  cpu_busy logic modified(affects RCALL/ICALL/CALL instruction interract with interrupt)
9 
--  SLEEP and CLRWDT instructions support was added
10 
--  V-flag bug fixed (AND/ANDI/OR/ORI/EOR)
11 
--  V-flag bug fixed (ADIW/SBIW)
12 
--  Unused outputs(sreg_bit_num[2..0],idc_sbi_out,idc_cbi_out,idc_bld_out) were removed.
13 
--  Output alu_data_d_in[7..0] was removed.
14 
--  Gloabal clock enable(cp2en) was added
15 
--  cpu_busy(push/pop) + irq bug was fixed 14.07.05
16 
--  BRXX+IRQ interaction was modified -> cpu_busy
17 
--  LDS/STS now requires only two cycles for execution (13.01.06 -> last modificatioon)
18 
--************************************************************************************************
19 
 
20 
library IEEE;
21 
use IEEE.std_logic_1164.all;
22 
use IEEE.std_logic_unsigned.all;
23 
 
24 
use WORK.AVRuCPackage.all;
25 
 
26 
entity pm_fetch_dec_cm4 is port(
27 
                cp2_cml_1 : in std_logic;
28 
                cp2_cml_2 : in std_logic;
29 
                cp2_cml_3 : in std_logic;
30 
 
31 
                              -- Clock and reset
32 
                              cp2              : in  std_logic;
33 
                                                          cp2en            : in  std_logic;
34 
                              ireset           : in  std_logic;
35 
                                                          -- JTAG OCD support
36 
                                                          valid_instr      : out  std_logic;
37 
                                                      insert_nop       : in   std_logic;
38 
                                                      block_irq        : in   std_logic;
39 
                                                      change_flow      : out  std_logic;
40 
                                                          -- Program memory
41 
                              pc               : out std_logic_vector (15 downto 0);
42 
                              inst             : in  std_logic_vector (15 downto 0);
43 
                              -- I/O control
44 
                              adr              : out std_logic_vector (5 downto 0);
45 
                              iore             : out std_logic;
46 
                              iowe             : out std_logic;
47 
                              -- Data memory control
48 
                              ramadr           : out std_logic_vector (15 downto 0);
49 
                              ramre            : out std_logic;
50 
                              ramwe            : out std_logic;
51 
                              cpuwait          : in  std_logic;
52 
                                                          -- Data paths
53 
                              dbusin           : in  std_logic_vector (7 downto 0);
54 
                              dbusout          : out std_logic_vector (7 downto 0);
55 
                              dbusout_int_route : out std_logic_vector (7 downto 0);
56 
                              -- Interrupt
57 
                              irqlines         : in  std_logic_vector (22 downto 0);
58 
                              irqack           : out std_logic;
59 
                              irqackad         : out std_logic_vector(4 downto 0);
60 
                                                      --Sleep
61 
                              sleepi           : out std_logic;
62 
                              irqok                : out std_logic;
63 
                              --Watchdog
64 
                              wdri                 : out std_logic;
65 
                                                          -- ALU interface(Data inputs)
66 
                              alu_data_r_in    : out std_logic_vector(7 downto 0);
67 
                                                          -- ALU interface(Instruction inputs)
68 
                                                          idc_add_out      : out std_logic;
69 
                              idc_adc_out      : out std_logic;
70 
                              idc_adiw_out     : out std_logic;
71 
                              idc_sub_out      : out std_logic;
72 
                              idc_subi_out     : out std_logic;
73 
                              idc_sbc_out      : out std_logic;
74 
                              idc_sbci_out     : out std_logic;
75 
                              idc_sbiw_out     : out std_logic;
76 
 
77 
                              adiw_st_out      : out std_logic;
78 
                              sbiw_st_out      : out std_logic;
79 
 
80 
                              idc_and_out      : out std_logic;
81 
                              idc_andi_out     : out std_logic;
82 
                              idc_or_out       : out std_logic;
83 
                              idc_ori_out      : out std_logic;
84 
                              idc_eor_out      : out std_logic;
85 
                              idc_com_out      : out std_logic;
86 
                              idc_neg_out      : out std_logic;
87 
 
88 
                              idc_inc_out      : out std_logic;
89 
                              idc_dec_out      : out std_logic;
90 
 
91 
                              idc_cp_out       : out std_logic;
92 
                              idc_cpc_out      : out std_logic;
93 
                              idc_cpi_out      : out std_logic;
94 
                              idc_cpse_out     : out std_logic;
95 
 
96 
                              idc_lsr_out      : out std_logic;
97 
                              idc_ror_out      : out std_logic;
98 
                              idc_asr_out      : out std_logic;
99 
                              idc_swap_out     : out std_logic;
100 
 
101 
                               -- ALU interface(Data output)
102 
                               alu_data_out    : in std_logic_vector(7 downto 0);
103 
 
104 
                               -- ALU interface(Flag outputs)
105 
                               alu_c_flag_out  : in std_logic;
106 
                               alu_z_flag_out  : in std_logic;
107 
                               alu_n_flag_out  : in std_logic;
108 
                               alu_v_flag_out  : in std_logic;
109 
                               alu_s_flag_out  : in std_logic;
110 
                               alu_h_flag_out  : in std_logic;
111 
 
112 
                                                           -- General purpose register file interface
113 
                               reg_rd_in       : out std_logic_vector  (7 downto 0);
114 
                               reg_rd_out      : in  std_logic_vector  (7 downto 0);
115 
                               reg_rd_out_int  : in std_logic_vector(7 downto 0);
116 
                               reg_rd_adr      : out std_logic_vector  (4 downto 0);
117 
                               reg_rd_adr_int      : out std_logic_vector  (4 downto 0);
118 
                               reg_rr_out      : in  std_logic_vector  (7 downto 0);
119 
                               reg_rr_adr      : out std_logic_vector  (4 downto 0);
120 
                               reg_rd_wr       : out std_logic;
121 
 
122 
                               post_inc        : out std_logic;                       -- POST INCREMENT FOR LD/ST INSTRUCTIONS
123 
                               pre_dec         : out std_logic;                        -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
124 
                               reg_h_wr        : out std_logic;
125 
                               reg_h_out       : in  std_logic_vector (15 downto 0);
126 
                               reg_h_adr       : out std_logic_vector (2 downto 0);    -- x,y,z
127 
                                       reg_z_out       : in  std_logic_vector (15 downto 0);  -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
128 
 
129 
                               -- I/O register file interface
130 
                               sreg_fl_in      : out std_logic_vector(7 downto 0);
131 
                               globint         : in  std_logic; -- SREG I flag
132 
 
133 
                               sreg_fl_wr_en   : out std_logic_vector(7 downto 0);   --FLAGS WRITE ENABLE SIGNALS
134 
 
135 
                               spl_out         : in  std_logic_vector(7 downto 0);
136 
                               sph_out         : in  std_logic_vector(7 downto 0);
137 
                               sp_ndown_up     : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
138 
                               sp_en           : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
139 
 
140 
                               rampz_out       : in  std_logic_vector(7 downto 0);
141 
 
142 
                                                           -- Bit processor interface
143 
                               bit_num_r_io    : out std_logic_vector (2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS
144 
                               bitpr_io_out    : in  std_logic_vector(7 downto 0);  -- SBI/CBI OUT
145 
                               branch          : out std_logic_vector (2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION
146 
                               bit_pr_sreg_out : in  std_logic_vector(7 downto 0);  -- BCLR/BSET/BST(T-FLAG ONLY)
147 
                               bld_op_out      : in  std_logic_vector(7 downto 0);  -- BLD OUT (T FLAG)
148 
                               bit_test_op_out : in  std_logic;                     -- OUTPUT OF SBIC/SBIS/SBRS/SBRC
149 
 
150 
                               sbi_st_out      : out std_logic;
151 
                               cbi_st_out      : out std_logic;
152 
 
153 
                               idc_bst_out     : out std_logic;
154 
                               idc_bset_out    : out std_logic;
155 
                               idc_bclr_out    : out std_logic;
156 
 
157 
                               idc_sbic_out    : out std_logic;
158 
                               idc_sbis_out    : out std_logic;
159 
 
160 
                               idc_sbrs_out    : out std_logic;
161 
                               idc_sbrc_out    : out std_logic;
162 
 
163 
                               idc_brbs_out    : out std_logic;
164 
                               idc_brbc_out    : out std_logic;
165 
 
166 
                               idc_reti_out    : out std_logic);
167 
end pm_fetch_dec_cm4;
168 
 
169 
architecture RTL of pm_fetch_dec_cm4 is
170 
 
171 
-- COPIES OF OUTPUTS
172 
signal ramadr_reg_in  : std_logic_vector(15 downto 0); -- INPUT OF THE ADDRESS REGISTER
173 
signal ramadr_reg_en  : std_logic;                     -- ADRESS REGISTER CLOCK ENABLE SIGNAL
174 
 
175 
signal irqack_int     : std_logic;
176 
signal irqackad_int   : std_logic_vector(irqackad'range);
177 
 
178 
-- ####################################################
179 
-- INTERNAL SIGNALS
180 
-- ####################################################
181 
 
182 
-- NEW SIGNALS
183 
signal   two_word_inst       : std_logic;                    -- CALL/JMP/STS/LDS INSTRUCTION INDICATOR
184 
 
185 
signal   ram_adr_int         : std_logic_vector (15 downto 0);
186 
constant const_ram_to_reg    : std_logic_vector := "00000000000";  -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19
187 
constant const_ram_to_io_a   : std_logic_vector := "00000000001";  -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
188 
constant const_ram_to_io_b   : std_logic_vector := "00000000010";  -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
189 
 
190 
-- LD/LDD/ST/STD SIGNALS
191 
signal adiw_sbiw_encoder_out : std_logic_vector (4 downto 0);
192 
signal adiw_sbiw_encoder_mux_out : std_logic_vector (4 downto 0);
193 
 
194 
 
195 
-- PROGRAM COUNTER SIGNALS
196 
signal program_counter_tmp : std_logic_vector (15 downto 0); -- TO STORE PC DURING LPM/ELPM INSTRUCTIONS
197 
signal program_counter     : std_logic_vector (15 downto 0);
198 
signal program_counter_in  : std_logic_vector (15 downto 0);
199 
signal program_counter_high_fr  : std_logic_vector (7 downto 0); -- TO STORE PC FOR CALL,IRQ,RCALL,ICALL
200 
 
201 
signal pc_low       : std_logic_vector (7 downto 0);
202 
signal pc_high      : std_logic_vector (7 downto 0);
203 
 
204 
 
205 
signal pc_low_en       : std_logic;
206 
signal pc_high_en      : std_logic;
207 
 
208 
signal offset_brbx     : std_logic_vector (15 downto 0);    -- OFFSET FOR BRCS/BRCC   INSTRUCTION  !!CHECKED
209 
signal offset_rxx      : std_logic_vector (15 downto 0);    -- OFFSET FOR RJMP/RCALL  INSTRUCTION  !!CHECKED
210 
 
211 
signal pa15_pm         : std_logic; -- ADDRESS LINE 15 FOR LPM/ELPM INSTRUCTIONS ('0' FOR LPM,RAMPZ(0) FOR ELPM)
212 
 
213 
signal alu_reg_wr      : std_logic; -- ALU INSTRUCTIONS PRODUCING WRITE TO THE GENERAL PURPOSE REGISTER FILE
214 
 
215 
-- DATA MEMORY,GENERAL PURPOSE REGISTERS AND I/O REGISTERS LOGIC
216 
 
217 
--! IMPORTANT NOTICE : OPERATIONS WHICH USE STACK POINTER (SPH:SPL) CAN NOT ACCCSESS GENERAL
218 
-- PURPOSE REGISTER FILE AND INPUT/OUTPUT REGISTER FILE !
219 
-- THESE OPERATIONS ARE : RCALL/ICALL/CALL/RET/RETI/PUSH/POP INSTRUCTIONS  AND INTERRUPT
220 
 
221 
signal reg_file_adr_space  : std_logic; -- ACCSESS TO THE REGISTER FILE
222 
signal io_file_adr_space   : std_logic; -- ACCSESS TO THE I/O FILE
223 
 
224 
-- STATE MACHINES SIGNALS
225 
signal irq_start      : std_logic;
226 
 
227 
signal nirq_st0       : std_logic;
228 
signal irq_st1        : std_logic;
229 
signal irq_st2        : std_logic;
230 
signal irq_st3        : std_logic;
231 
 
232 
signal ncall_st0      : std_logic;
233 
signal call_st1       : std_logic;
234 
signal call_st2       : std_logic;
235 
signal call_st3       : std_logic;
236 
 
237 
signal nrcall_st0     : std_logic;
238 
signal rcall_st1      : std_logic;
239 
signal rcall_st2      : std_logic;
240 
 
241 
signal nicall_st0     : std_logic;
242 
signal icall_st1      : std_logic;
243 
signal icall_st2      : std_logic;
244 
 
245 
signal njmp_st0       : std_logic;
246 
signal jmp_st1        : std_logic;
247 
signal jmp_st2        : std_logic;
248 
 
249 
signal ijmp_st        : std_logic;
250 
 
251 
signal rjmp_st        : std_logic;
252 
 
253 
signal nret_st0       : std_logic;
254 
signal ret_st1        : std_logic;
255 
signal ret_st2        : std_logic;
256 
signal ret_st3        : std_logic;
257 
 
258 
signal nreti_st0      : std_logic;
259 
signal reti_st1       : std_logic;
260 
signal reti_st2       : std_logic;
261 
signal reti_st3       : std_logic;
262 
 
263 
signal brxx_st        : std_logic;  -- BRANCHES
264 
 
265 
signal adiw_st        : std_logic;
266 
signal sbiw_st        : std_logic;
267 
 
268 
signal nskip_inst_st0 : std_logic;
269 
signal skip_inst_st1  : std_logic;
270 
signal skip_inst_st2  : std_logic;  -- ALL SKIP INSTRUCTIONS SBRS/SBRC/SBIS/SBIC/CPSE
271 
 
272 
signal skip_inst_start  : std_logic;
273 
 
274 
signal nlpm_st0       : std_logic;
275 
signal lpm_st1        : std_logic;
276 
signal lpm_st2        : std_logic;
277 
 
278 
signal nelpm_st0      : std_logic;
279 
signal elpm_st1       : std_logic;
280 
signal elpm_st2       : std_logic;
281 
 
282 
--signal nsts_st0       : std_logic;
283 
--signal sts_st1        : std_logic;
284 
--signal sts_st2        : std_logic;
285 
 
286 
signal sts_st         : std_logic;
287 
 
288 
--signal nlds_st0       : std_logic;
289 
--signal lds_st1        : std_logic;
290 
--signal lds_st2        : std_logic;
291 
 
292 
signal lds_st           : std_logic;
293 
 
294 
signal st_st          : std_logic;
295 
signal ld_st          : std_logic;
296 
 
297 
signal sbi_st         : std_logic;
298 
signal cbi_st         : std_logic;
299 
 
300 
signal push_st        : std_logic;
301 
signal pop_st         : std_logic;
302 
 
303 
-- INTERNAL STATE MACHINES
304 
signal nop_insert_st  : std_logic;
305 
signal cpu_busy       : std_logic;
306 
 
307 
-- INTERNAL COPIES OF OUTPUTS
308 
signal pc_int              : std_logic_vector (15 downto 0);
309 
signal adr_int             : std_logic_vector (5 downto 0);
310 
signal iore_int                    : std_logic;
311 
signal iowe_int            : std_logic;
312 
signal ramadr_int          : std_logic_vector (15 downto 0);
313 
signal ramre_int           : std_logic;
314 
signal ramwe_int           : std_logic;
315 
signal dbusout_int         : std_logic_vector (7 downto 0);
316 
 
317 
-- COMMAND REGISTER
318 
signal instruction_reg      : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER
319 
signal instruction_code_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER WITH NOP INSERTION
320 
signal instruction_reg_ena  : std_logic;                               -- CLOCK ENABLE
321 
 
322 
 
323 
-- IRQ INTERNAL LOGIC
324 
signal irq_int              : std_logic;
325 
signal irq_vector_adr       : std_logic_vector(15 downto 0);
326 
 
327 
-- INTERRUPT RELATING REGISTERS
328 
signal pc_for_interrupt : std_logic_vector(15 downto 0);
329 
 
330 
-- DATA EXTRACTOR SIGNALS
331 
signal dex_dat8_immed  : std_logic_vector (7 downto 0);  -- IMMEDIATE CONSTANT (DATA) -> ANDI,ORI,SUBI,SBCI,CPI,LDI
332 
signal dex_dat6_immed  : std_logic_vector (5 downto 0);  -- IMMEDIATE CONSTANT (DATA) -> ADIW,SBIW
333 
signal dex_adr12mem_s  : std_logic_vector (11 downto 0); -- RELATIVE ADDRESS (SIGNED) -> RCALL,RJMP
334 
signal dex_adr6port    : std_logic_vector (5 downto 0);  -- I/O PORT ADDRESS -> IN,OUT
335 
signal dex_adr5port    : std_logic_vector (4 downto 0);  -- I/O PORT ADDRESS -> CBI,SBI,SBIC,SBIS
336 
signal dex_adr_disp    : std_logic_vector (5 downto 0);  -- DISPLACEMENT FO ADDDRESS -> STD,LDD
337 
signal dex_condition   : std_logic_vector (2 downto 0);  -- CONDITION -> BRBC,BRBS
338 
signal dex_bitnum_sreg : std_logic_vector (2 downto 0);  -- NUMBER OF BIT IN SREG -> BCLR,BSET
339 
signal dex_adrreg_r    : std_logic_vector (4 downto 0);  -- SOURCE REGISTER ADDRESS -> .......
340 
signal dex_adrreg_d    : std_logic_vector (4 downto 0);  -- DESTINATION REGISTER ADDRESS -> ......
341 
signal dex_bitop_bitnum : std_logic_vector(2 downto 0);  -- NUMBER OF BIT FOR BIT ORIENTEDE OPERATION -> BST/BLD+SBI/CBI+SBIC/SBIS+SBRC/SBRS !! CHECKED
342 
signal dex_brxx_offset : std_logic_vector (6 downto 0);  -- RELATIVE ADDRESS (SIGNED) -> BRBC,BRBS !! CHECKED
343 
signal dex_adiw_sbiw_reg_adr  : std_logic_vector (1 downto 0);  -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS
344 
 
345 
signal dex_adrreg_d_latched : std_logic_vector (4 downto 0);   --  STORE ADDRESS OF DESTINATION REGISTER FOR LDS/STS/POP INSTRUCTIONS
346 
signal gp_reg_tmp           : std_logic_vector (7 downto 0);   --  STORE DATA FROM THE REGISTERS FOR STS,ST INSTRUCTIONS
347 
signal cbi_sbi_io_adr_tmp   : std_logic_vector (4 downto 0);   --  STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION
348 
signal cbi_sbi_bit_num_tmp  : std_logic_vector (2 downto 0);   --  STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION
349 
 
350 
-- INSTRUCTIONS DECODER SIGNALS
351 
 
352 
signal idc_adc     : std_logic; -- INSTRUCTION ADC
353 
signal idc_add     : std_logic; -- INSTRUCTION ADD
354 
signal idc_adiw    : std_logic; -- INSTRUCTION ADIW
355 
signal idc_and     : std_logic; -- INSTRUCTION AND
356 
signal idc_andi    : std_logic; -- INSTRUCTION ANDI
357 
signal idc_asr     : std_logic; -- INSTRUCTION ASR
358 
 
359 
signal idc_bclr    : std_logic; -- INSTRUCTION BCLR
360 
signal idc_bld     : std_logic; -- INSTRUCTION BLD
361 
signal idc_brbc    : std_logic; -- INSTRUCTION BRBC
362 
signal idc_brbs    : std_logic; -- INSTRUCTION BRBS
363 
signal idc_bset    : std_logic; -- INSTRUCTION BSET
364 
signal idc_bst     : std_logic; -- INSTRUCTION BST
365 
 
366 
signal idc_call    : std_logic; -- INSTRUCTION CALL
367 
signal idc_cbi     : std_logic; -- INSTRUCTION CBI
368 
signal idc_com     : std_logic; -- INSTRUCTION COM
369 
signal idc_cp      : std_logic; -- INSTRUCTION CP
370 
signal idc_cpc     : std_logic; -- INSTRUCTION CPC
371 
signal idc_cpi     : std_logic; -- INSTRUCTION CPI
372 
signal idc_cpse    : std_logic; -- INSTRUCTION CPSE
373 
 
374 
signal idc_dec     : std_logic; -- INSTRUCTION DEC
375 
 
376 
signal idc_elpm    : std_logic; -- INSTRUCTION ELPM
377 
signal idc_eor     : std_logic; -- INSTRUCTION EOR
378 
 
379 
signal idc_icall   : std_logic; -- INSTRUCTION ICALL
380 
signal idc_ijmp    : std_logic; -- INSTRUCTION IJMP
381 
 
382 
signal idc_in      : std_logic; -- INSTRUCTION IN
383 
signal idc_inc     : std_logic; -- INSTRUCTION INC
384 
 
385 
signal idc_jmp     : std_logic; -- INSTRUCTION JMP
386 
 
387 
signal idc_ld_x    : std_logic; -- INSTRUCTION LD Rx,X ; LD Rx,X+ ;LD Rx,-X
388 
signal idc_ld_y    : std_logic; -- INSTRUCTION LD Rx,Y ; LD Rx,Y+ ;LD Rx,-Y
389 
signal idc_ldd_y   : std_logic; -- INSTRUCTION LDD Rx,Y+q
390 
signal idc_ld_z    : std_logic; -- INSTRUCTION LD Rx,Z ; LD Rx,Z+ ;LD Rx,-Z
391 
signal idc_ldd_z   : std_logic; -- INSTRUCTION LDD Rx,Z+q
392 
 
393 
signal idc_ldi     : std_logic; -- INSTRUCTION LDI
394 
signal idc_lds     : std_logic; -- INSTRUCTION LDS
395 
signal idc_lpm     : std_logic; -- INSTRUCTION LPM
396 
signal idc_lsr     : std_logic; -- INSTRUCTION LSR
397 
 
398 
signal idc_mov     : std_logic; -- INSTRUCTION MOV
399 
signal idc_mul     : std_logic; -- INSTRUCTION MUL
400 
 
401 
signal idc_neg     : std_logic; -- INSTRUCTION NEG
402 
signal idc_nop     : std_logic; -- INSTRUCTION NOP
403 
 
404 
signal idc_or      : std_logic; -- INSTRUCTION OR
405 
signal idc_ori     : std_logic; -- INSTRUCTION ORI
406 
signal idc_out     : std_logic; -- INSTRUCTION OUT
407 
 
408 
signal idc_pop     : std_logic; -- INSTRUCTION POP
409 
signal idc_push    : std_logic; -- INSTRUCTION PUSH
410 
 
411 
signal idc_rcall   : std_logic; -- INSTRUCTION RCALL
412 
signal idc_ret     : std_logic; -- INSTRUCTION RET
413 
signal idc_reti    : std_logic; -- INSTRUCTION RETI
414 
signal idc_rjmp    : std_logic; -- INSTRUCTION RJMP
415 
signal idc_ror     : std_logic; -- INSTRUCTION ROR
416 
 
417 
signal idc_sbc     : std_logic; -- INSTRUCTION SBC
418 
signal idc_sbci    : std_logic; -- INSTRUCTION SBCI
419 
signal idc_sbi     : std_logic; -- INSTRUCTION SBI
420 
signal idc_sbic    : std_logic; -- INSTRUCTION SBIC
421 
signal idc_sbis    : std_logic; -- INSTRUCTION SBIS
422 
signal idc_sbiw    : std_logic; -- INSTRUCTION SBIW
423 
signal idc_sbrc    : std_logic; -- INSTRUCTION SBRC
424 
signal idc_sbrs    : std_logic; -- INSTRUCTION SBRS
425 
signal idc_sleep   : std_logic; -- INSTRUCTION SLEEP
426 
 
427 
signal idc_st_x    : std_logic; -- INSTRUCTION LD X,Rx ; LD X+,Rx ;LD -X,Rx
428 
signal idc_st_y    : std_logic; -- INSTRUCTION LD Y,Rx ; LD Y+,Rx ;LD -Y,Rx
429 
signal idc_std_y   : std_logic; -- INSTRUCTION LDD Y+q,Rx
430 
signal idc_st_z    : std_logic; -- INSTRUCTION LD Z,Rx ; LD Z+,Rx ;LD -Z,Rx
431 
signal idc_std_z   : std_logic; -- INSTRUCTION LDD Z+q,Rx
432 
 
433 
signal idc_sts     : std_logic; -- INSTRUCTION STS
434 
signal idc_sub     : std_logic; -- INSTRUCTION SUB
435 
signal idc_subi    : std_logic; -- INSTRUCTION SUBI
436 
signal idc_swap    : std_logic; -- INSTRUCTION SWAP
437 
 
438 
signal idc_wdr     : std_logic; -- INSTRUCTION WDR
439 
 
440 
-- ADDITIONAL SIGNALS
441 
signal idc_psinc   :  std_logic; -- POST INCREMENT FLAG FOR LD,ST INSTRUCTIONS
442 
signal idc_prdec   :  std_logic; -- PRE DECREMENT  FLAG FOR LD,ST INSTRUCTIONS
443 
 
444 
-- ##################################################
445 
 
446 
-- SREG FLAGS WRITE ENABLE SIGNALS
447 
 
448 
--alias sreg_c_wr_en  : std_logic is sreg_fl_wr_en(0);
449 
--alias sreg_z_wr_en  : std_logic is sreg_fl_wr_en(1);
450 
--alias sreg_n_wr_en  : std_logic is sreg_fl_wr_en(2);
451 
--alias sreg_v_wr_en  : std_logic is sreg_fl_wr_en(3);
452 
--alias sreg_s_wr_en  : std_logic is sreg_fl_wr_en(4);
453 
--alias sreg_h_wr_en  : std_logic is sreg_fl_wr_en(5);
454 
--alias sreg_t_wr_en  : std_logic is sreg_fl_wr_en(6);
455 
--alias sreg_i_wr_en  : std_logic is sreg_fl_wr_en(7);
456 
 
457 
signal sreg_c_wr_en  : std_logic; --  is sreg_fl_wr_en(0);
458 
signal sreg_z_wr_en  : std_logic; --  is sreg_fl_wr_en(1);
459 
signal sreg_n_wr_en  : std_logic; --  is sreg_fl_wr_en(2);
460 
signal sreg_v_wr_en  : std_logic; --  is sreg_fl_wr_en(3);
461 
signal sreg_s_wr_en  : std_logic; --  is sreg_fl_wr_en(4);
462 
signal sreg_h_wr_en  : std_logic; --  is sreg_fl_wr_en(5);
463 
signal sreg_t_wr_en  : std_logic; --  is sreg_fl_wr_en(6);
464 
signal sreg_i_wr_en  : std_logic; --  is sreg_fl_wr_en(7);
465 
 
466 
signal sreg_bop_wr_en : std_logic_vector (7 downto 0);
467 
 
468 
signal sreg_adr_eq  : std_logic;
469 
-- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
470 
 
471 
signal inst_cml_3 :  std_logic_vector ( 15 downto 0 );
472 
signal inst_cml_2 :  std_logic_vector ( 15 downto 0 );
473 
signal inst_cml_1 :  std_logic_vector ( 15 downto 0 );
474 
signal sp_ndown_up_cml_out :  std_logic;
475 
signal sp_en_cml_out :  std_logic;
476 
signal cpuwait_cml_3 :  std_logic;
477 
signal cpuwait_cml_2 :  std_logic;
478 
signal cpuwait_cml_1 :  std_logic;
479 
signal reg_rd_in_cml_out :  std_logic_vector ( 7 downto 0 );
480 
signal dbusin_cml_3 :  std_logic_vector ( 7 downto 0 );
481 
signal dbusin_cml_2 :  std_logic_vector ( 7 downto 0 );
482 
signal irqlines_cml_2 :  std_logic_vector ( 22 downto 0 );
483 
signal irqlines_cml_1 :  std_logic_vector ( 22 downto 0 );
484 
signal sreg_fl_in_cml_out :  std_logic_vector ( 7 downto 0 );
485 
signal alu_z_flag_out_cml_3 :  std_logic;
486 
signal reg_rd_out_cml_3 :  std_logic_vector ( 7 downto 0 );
487 
signal reg_rd_out_cml_2 :  std_logic_vector ( 7 downto 0 );
488 
signal reg_rr_out_cml_2 :  std_logic_vector ( 7 downto 0 );
489 
signal reg_rr_out_cml_1 :  std_logic_vector ( 7 downto 0 );
490 
signal reg_h_out_cml_2 :  std_logic_vector ( 15 downto 0 );
491 
signal reg_z_out_cml_3 :  std_logic_vector ( 15 downto 0 );
492 
signal reg_z_out_cml_2 :  std_logic_vector ( 15 downto 0 );
493 
signal spl_out_cml_2 :  std_logic_vector ( 7 downto 0 );
494 
signal sph_out_cml_2 :  std_logic_vector ( 7 downto 0 );
495 
signal rampz_out_cml_3 :  std_logic_vector ( 7 downto 0 );
496 
signal rampz_out_cml_2 :  std_logic_vector ( 7 downto 0 );
497 
signal bitpr_io_out_cml_2 :  std_logic_vector ( 7 downto 0 );
498 
signal bitpr_io_out_cml_1 :  std_logic_vector ( 7 downto 0 );
499 
signal bit_test_op_out_cml_3 :  std_logic;
500 
signal ramadr_reg_in_cml_3 :  std_logic_vector ( 15 downto 0 );
501 
signal irqack_cml_out :  std_logic;
502 
signal irqack_int_cml_3 :  std_logic;
503 
signal irqack_int_cml_2 :  std_logic;
504 
signal irqack_int_cml_1 :  std_logic;
505 
signal irqackad_cml_out :  std_logic_vector ( 4 downto 0 );
506 
signal irqackad_int_cml_3 :  std_logic_vector ( irqackad 'range);
507 
signal irqackad_int_cml_2 :  std_logic_vector ( irqackad 'range);
508 
signal irqackad_int_cml_1 :  std_logic_vector ( irqackad 'range);
509 
signal two_word_inst_cml_3 :  std_logic;
510 
signal reg_rd_adr_cml_out :  std_logic_vector ( 4 downto 0 );
511 
signal adiw_sbiw_encoder_out_cml_3 :  std_logic_vector ( 4 downto 0 );
512 
signal adiw_sbiw_encoder_out_cml_2 :  std_logic_vector ( 4 downto 0 );
513 
signal adiw_sbiw_encoder_out_cml_1 :  std_logic_vector ( 4 downto 0 );
514 
signal adiw_sbiw_encoder_mux_out_cml_3 :  std_logic_vector ( 4 downto 0 );
515 
signal adiw_sbiw_encoder_mux_out_cml_2 :  std_logic_vector ( 4 downto 0 );
516 
signal adiw_sbiw_encoder_mux_out_cml_1 :  std_logic_vector ( 4 downto 0 );
517 
signal program_counter_tmp_cml_3 :  std_logic_vector ( 15 downto 0 );
518 
signal program_counter_tmp_cml_2 :  std_logic_vector ( 15 downto 0 );
519 
signal program_counter_tmp_cml_1 :  std_logic_vector ( 15 downto 0 );
520 
signal program_counter_cml_3 :  std_logic_vector ( 15 downto 0 );
521 
signal program_counter_cml_2 :  std_logic_vector ( 15 downto 0 );
522 
signal program_counter_cml_1 :  std_logic_vector ( 15 downto 0 );
523 
signal program_counter_high_fr_cml_3 :  std_logic_vector ( 7 downto 0 );
524 
signal program_counter_high_fr_cml_2 :  std_logic_vector ( 7 downto 0 );
525 
signal program_counter_high_fr_cml_1 :  std_logic_vector ( 7 downto 0 );
526 
signal pc_low_cml_3 :  std_logic_vector ( 7 downto 0 );
527 
signal pc_low_cml_2 :  std_logic_vector ( 7 downto 0 );
528 
signal pc_low_cml_1 :  std_logic_vector ( 7 downto 0 );
529 
signal pc_high_cml_3 :  std_logic_vector ( 7 downto 0 );
530 
signal pc_high_cml_2 :  std_logic_vector ( 7 downto 0 );
531 
signal pc_high_cml_1 :  std_logic_vector ( 7 downto 0 );
532 
signal reg_rd_wr_cml_out :  std_logic;
533 
signal reg_file_adr_space_cml_3 :  std_logic;
534 
signal reg_file_adr_space_cml_2 :  std_logic;
535 
signal reg_file_adr_space_cml_1 :  std_logic;
536 
signal io_file_adr_space_cml_3 :  std_logic;
537 
signal io_file_adr_space_cml_2 :  std_logic;
538 
signal io_file_adr_space_cml_1 :  std_logic;
539 
signal nirq_st0_cml_3 :  std_logic;
540 
signal nirq_st0_cml_2 :  std_logic;
541 
signal nirq_st0_cml_1 :  std_logic;
542 
signal irq_st1_cml_3 :  std_logic;
543 
signal irq_st1_cml_2 :  std_logic;
544 
signal irq_st1_cml_1 :  std_logic;
545 
signal irq_st2_cml_3 :  std_logic;
546 
signal irq_st2_cml_2 :  std_logic;
547 
signal irq_st2_cml_1 :  std_logic;
548 
signal irq_st3_cml_3 :  std_logic;
549 
signal irq_st3_cml_2 :  std_logic;
550 
signal irq_st3_cml_1 :  std_logic;
551 
signal ncall_st0_cml_3 :  std_logic;
552 
signal ncall_st0_cml_2 :  std_logic;
553 
signal ncall_st0_cml_1 :  std_logic;
554 
signal call_st1_cml_3 :  std_logic;
555 
signal call_st1_cml_2 :  std_logic;
556 
signal call_st1_cml_1 :  std_logic;
557 
signal call_st2_cml_3 :  std_logic;
558 
signal call_st2_cml_2 :  std_logic;
559 
signal call_st2_cml_1 :  std_logic;
560 
signal call_st3_cml_3 :  std_logic;
561 
signal call_st3_cml_2 :  std_logic;
562 
signal call_st3_cml_1 :  std_logic;
563 
signal nrcall_st0_cml_3 :  std_logic;
564 
signal nrcall_st0_cml_2 :  std_logic;
565 
signal nrcall_st0_cml_1 :  std_logic;
566 
signal rcall_st1_cml_3 :  std_logic;
567 
signal rcall_st1_cml_2 :  std_logic;
568 
signal rcall_st1_cml_1 :  std_logic;
569 
signal rcall_st2_cml_3 :  std_logic;
570 
signal rcall_st2_cml_2 :  std_logic;
571 
signal rcall_st2_cml_1 :  std_logic;
572 
signal nicall_st0_cml_3 :  std_logic;
573 
signal nicall_st0_cml_2 :  std_logic;
574 
signal nicall_st0_cml_1 :  std_logic;
575 
signal icall_st1_cml_3 :  std_logic;
576 
signal icall_st1_cml_2 :  std_logic;
577 
signal icall_st1_cml_1 :  std_logic;
578 
signal icall_st2_cml_3 :  std_logic;
579 
signal icall_st2_cml_2 :  std_logic;
580 
signal icall_st2_cml_1 :  std_logic;
581 
signal njmp_st0_cml_3 :  std_logic;
582 
signal njmp_st0_cml_2 :  std_logic;
583 
signal njmp_st0_cml_1 :  std_logic;
584 
signal jmp_st1_cml_3 :  std_logic;
585 
signal jmp_st1_cml_2 :  std_logic;
586 
signal jmp_st1_cml_1 :  std_logic;
587 
signal jmp_st2_cml_3 :  std_logic;
588 
signal jmp_st2_cml_2 :  std_logic;
589 
signal jmp_st2_cml_1 :  std_logic;
590 
signal ijmp_st_cml_3 :  std_logic;
591 
signal ijmp_st_cml_2 :  std_logic;
592 
signal ijmp_st_cml_1 :  std_logic;
593 
signal rjmp_st_cml_3 :  std_logic;
594 
signal rjmp_st_cml_2 :  std_logic;
595 
signal rjmp_st_cml_1 :  std_logic;
596 
signal nret_st0_cml_3 :  std_logic;
597 
signal nret_st0_cml_2 :  std_logic;
598 
signal nret_st0_cml_1 :  std_logic;
599 
signal ret_st1_cml_3 :  std_logic;
600 
signal ret_st1_cml_2 :  std_logic;
601 
signal ret_st1_cml_1 :  std_logic;
602 
signal ret_st2_cml_3 :  std_logic;
603 
signal ret_st2_cml_2 :  std_logic;
604 
signal ret_st2_cml_1 :  std_logic;
605 
signal ret_st3_cml_3 :  std_logic;
606 
signal ret_st3_cml_2 :  std_logic;
607 
signal ret_st3_cml_1 :  std_logic;
608 
signal nreti_st0_cml_3 :  std_logic;
609 
signal nreti_st0_cml_2 :  std_logic;
610 
signal nreti_st0_cml_1 :  std_logic;
611 
signal reti_st1_cml_3 :  std_logic;
612 
signal reti_st1_cml_2 :  std_logic;
613 
signal reti_st1_cml_1 :  std_logic;
614 
signal reti_st2_cml_3 :  std_logic;
615 
signal reti_st2_cml_2 :  std_logic;
616 
signal reti_st2_cml_1 :  std_logic;
617 
signal reti_st3_cml_3 :  std_logic;
618 
signal reti_st3_cml_2 :  std_logic;
619 
signal reti_st3_cml_1 :  std_logic;
620 
signal brxx_st_cml_3 :  std_logic;
621 
signal brxx_st_cml_2 :  std_logic;
622 
signal brxx_st_cml_1 :  std_logic;
623 
signal adiw_st_cml_3 :  std_logic;
624 
signal adiw_st_cml_2 :  std_logic;
625 
signal adiw_st_cml_1 :  std_logic;
626 
signal sbiw_st_cml_3 :  std_logic;
627 
signal sbiw_st_cml_2 :  std_logic;
628 
signal sbiw_st_cml_1 :  std_logic;
629 
signal nskip_inst_st0_cml_3 :  std_logic;
630 
signal nskip_inst_st0_cml_2 :  std_logic;
631 
signal nskip_inst_st0_cml_1 :  std_logic;
632 
signal skip_inst_st1_cml_3 :  std_logic;
633 
signal skip_inst_st1_cml_2 :  std_logic;
634 
signal skip_inst_st1_cml_1 :  std_logic;
635 
signal skip_inst_st2_cml_3 :  std_logic;
636 
signal skip_inst_st2_cml_2 :  std_logic;
637 
signal skip_inst_st2_cml_1 :  std_logic;
638 
signal nlpm_st0_cml_3 :  std_logic;
639 
signal nlpm_st0_cml_2 :  std_logic;
640 
signal nlpm_st0_cml_1 :  std_logic;
641 
signal lpm_st1_cml_3 :  std_logic;
642 
signal lpm_st1_cml_2 :  std_logic;
643 
signal lpm_st1_cml_1 :  std_logic;
644 
signal lpm_st2_cml_3 :  std_logic;
645 
signal lpm_st2_cml_2 :  std_logic;
646 
signal lpm_st2_cml_1 :  std_logic;
647 
signal sts_st_cml_3 :  std_logic;
648 
signal sts_st_cml_2 :  std_logic;
649 
signal sts_st_cml_1 :  std_logic;
650 
signal lds_st_cml_3 :  std_logic;
651 
signal lds_st_cml_2 :  std_logic;
652 
signal lds_st_cml_1 :  std_logic;
653 
signal st_st_cml_3 :  std_logic;
654 
signal st_st_cml_2 :  std_logic;
655 
signal st_st_cml_1 :  std_logic;
656 
signal ld_st_cml_3 :  std_logic;
657 
signal ld_st_cml_2 :  std_logic;
658 
signal ld_st_cml_1 :  std_logic;
659 
signal sbi_st_cml_3 :  std_logic;
660 
signal sbi_st_cml_2 :  std_logic;
661 
signal sbi_st_cml_1 :  std_logic;
662 
signal cbi_st_cml_3 :  std_logic;
663 
signal cbi_st_cml_2 :  std_logic;
664 
signal cbi_st_cml_1 :  std_logic;
665 
signal push_st_cml_3 :  std_logic;
666 
signal push_st_cml_2 :  std_logic;
667 
signal push_st_cml_1 :  std_logic;
668 
signal pop_st_cml_3 :  std_logic;
669 
signal pop_st_cml_2 :  std_logic;
670 
signal pop_st_cml_1 :  std_logic;
671 
signal adr_int_cml_2 :  std_logic_vector ( 5 downto 0 );
672 
signal iowe_cml_out :  std_logic;
673 
signal iowe_int_cml_3 :  std_logic;
674 
signal ramadr_int_cml_3 :  std_logic_vector ( 15 downto 0 );
675 
signal ramadr_int_cml_2 :  std_logic_vector ( 15 downto 0 );
676 
signal ramadr_int_cml_1 :  std_logic_vector ( 15 downto 0 );
677 
signal ramre_int_cml_3 :  std_logic;
678 
signal ramre_int_cml_2 :  std_logic;
679 
signal ramre_int_cml_1 :  std_logic;
680 
signal ramwe_int_cml_3 :  std_logic;
681 
signal ramwe_int_cml_2 :  std_logic;
682 
signal ramwe_int_cml_1 :  std_logic;
683 
signal dbusout_int_route_cml_out :  std_logic_vector ( 7 downto 0 );
684 
signal dbusout_int_cml_3 :  std_logic_vector ( 7 downto 0 );
685 
signal instruction_reg_cml_3 :  std_logic_vector ( 15 downto 0 );
686 
signal instruction_reg_cml_2 :  std_logic_vector ( 15 downto 0 );
687 
signal instruction_reg_cml_1 :  std_logic_vector ( 15 downto 0 );
688 
signal instruction_code_reg_cml_3 :  std_logic_vector ( 15 downto 0 );
689 
signal instruction_code_reg_cml_2 :  std_logic_vector ( 15 downto 0 );
690 
signal instruction_code_reg_cml_1 :  std_logic_vector ( 15 downto 0 );
691 
signal irqok_cml_out :  std_logic;
692 
signal irq_int_cml_3 :  std_logic;
693 
signal irq_vector_adr_cml_3 :  std_logic_vector ( 15 downto 0 );
694 
signal irq_vector_adr_cml_2 :  std_logic_vector ( 15 downto 0 );
695 
signal irq_vector_adr_cml_1 :  std_logic_vector ( 15 downto 0 );
696 
signal pc_for_interrupt_cml_3 :  std_logic_vector ( 15 downto 0 );
697 
signal pc_for_interrupt_cml_2 :  std_logic_vector ( 15 downto 0 );
698 
signal pc_for_interrupt_cml_1 :  std_logic_vector ( 15 downto 0 );
699 
signal dex_dat8_immed_cml_2 :  std_logic_vector ( 7 downto 0 );
700 
signal dex_dat8_immed_cml_1 :  std_logic_vector ( 7 downto 0 );
701 
signal dex_adr5port_cml_3 :  std_logic_vector ( 4 downto 0 );
702 
signal dex_adr5port_cml_2 :  std_logic_vector ( 4 downto 0 );
703 
signal dex_adr_disp_cml_2 :  std_logic_vector ( 5 downto 0 );
704 
signal dex_adrreg_d_cml_3 :  std_logic_vector ( 4 downto 0 );
705 
signal dex_adrreg_d_cml_2 :  std_logic_vector ( 4 downto 0 );
706 
signal dex_adrreg_d_cml_1 :  std_logic_vector ( 4 downto 0 );
707 
signal dex_bitop_bitnum_cml_3 :  std_logic_vector ( 2 downto 0 );
708 
signal dex_bitop_bitnum_cml_2 :  std_logic_vector ( 2 downto 0 );
709 
signal dex_bitop_bitnum_cml_1 :  std_logic_vector ( 2 downto 0 );
710 
signal dex_adrreg_d_latched_cml_3 :  std_logic_vector ( 4 downto 0 );
711 
signal dex_adrreg_d_latched_cml_2 :  std_logic_vector ( 4 downto 0 );
712 
signal dex_adrreg_d_latched_cml_1 :  std_logic_vector ( 4 downto 0 );
713 
signal gp_reg_tmp_cml_3 :  std_logic_vector ( 7 downto 0 );
714 
signal gp_reg_tmp_cml_2 :  std_logic_vector ( 7 downto 0 );
715 
signal gp_reg_tmp_cml_1 :  std_logic_vector ( 7 downto 0 );
716 
signal cbi_sbi_io_adr_tmp_cml_3 :  std_logic_vector ( 4 downto 0 );
717 
signal cbi_sbi_io_adr_tmp_cml_2 :  std_logic_vector ( 4 downto 0 );
718 
signal cbi_sbi_io_adr_tmp_cml_1 :  std_logic_vector ( 4 downto 0 );
719 
signal cbi_sbi_bit_num_tmp_cml_3 :  std_logic_vector ( 2 downto 0 );
720 
signal cbi_sbi_bit_num_tmp_cml_2 :  std_logic_vector ( 2 downto 0 );
721 
signal cbi_sbi_bit_num_tmp_cml_1 :  std_logic_vector ( 2 downto 0 );
722 
signal idc_adc_cml_3 :  std_logic;
723 
signal idc_adc_cml_2 :  std_logic;
724 
signal idc_adc_cml_1 :  std_logic;
725 
signal idc_add_cml_3 :  std_logic;
726 
signal idc_add_cml_2 :  std_logic;
727 
signal idc_adiw_out_cml_out :  std_logic;
728 
signal idc_adiw_cml_3 :  std_logic;
729 
signal idc_adiw_cml_2 :  std_logic;
730 
signal idc_adiw_cml_1 :  std_logic;
731 
signal idc_and_cml_3 :  std_logic;
732 
signal idc_and_cml_2 :  std_logic;
733 
signal idc_andi_out_cml_out :  std_logic;
734 
signal idc_andi_cml_3 :  std_logic;
735 
signal idc_andi_cml_2 :  std_logic;
736 
signal idc_andi_cml_1 :  std_logic;
737 
signal idc_asr_cml_3 :  std_logic;
738 
signal idc_asr_cml_2 :  std_logic;
739 
signal idc_bclr_out_cml_out :  std_logic;
740 
signal idc_bclr_cml_3 :  std_logic;
741 
signal idc_bld_cml_2 :  std_logic;
742 
signal idc_brbc_cml_3 :  std_logic;
743 
signal idc_brbs_cml_3 :  std_logic;
744 
signal idc_bset_out_cml_out :  std_logic;
745 
signal idc_bset_cml_3 :  std_logic;
746 
signal idc_bst_out_cml_out :  std_logic;
747 
signal idc_bst_cml_3 :  std_logic;
748 
signal idc_call_cml_3 :  std_logic;
749 
signal idc_cbi_cml_3 :  std_logic;
750 
signal idc_cbi_cml_2 :  std_logic;
751 
signal idc_com_cml_3 :  std_logic;
752 
signal idc_com_cml_2 :  std_logic;
753 
signal idc_cp_cml_3 :  std_logic;
754 
signal idc_cp_cml_2 :  std_logic;
755 
signal idc_cp_cml_1 :  std_logic;
756 
signal idc_cpc_cml_3 :  std_logic;
757 
signal idc_cpc_cml_2 :  std_logic;
758 
signal idc_cpc_cml_1 :  std_logic;
759 
signal idc_cpi_cml_3 :  std_logic;
760 
signal idc_cpi_cml_2 :  std_logic;
761 
signal idc_cpi_cml_1 :  std_logic;
762 
signal idc_cpse_cml_3 :  std_logic;
763 
signal idc_cpse_cml_2 :  std_logic;
764 
signal idc_cpse_cml_1 :  std_logic;
765 
signal idc_dec_cml_3 :  std_logic;
766 
signal idc_dec_cml_2 :  std_logic;
767 
signal idc_eor_cml_3 :  std_logic;
768 
signal idc_eor_cml_2 :  std_logic;
769 
signal idc_icall_cml_3 :  std_logic;
770 
signal idc_icall_cml_2 :  std_logic;
771 
signal idc_icall_cml_1 :  std_logic;
772 
signal idc_ijmp_cml_3 :  std_logic;
773 
signal idc_in_cml_2 :  std_logic;
774 
signal idc_inc_cml_3 :  std_logic;
775 
signal idc_inc_cml_2 :  std_logic;
776 
signal idc_jmp_cml_3 :  std_logic;
777 
signal reg_h_wr_cml_out :  std_logic;
778 
signal reg_h_adr_cml_out :  std_logic_vector ( 2 downto 0 );
779 
signal idc_ld_x_cml_3 :  std_logic;
780 
signal idc_ld_x_cml_2 :  std_logic;
781 
signal idc_ld_x_cml_1 :  std_logic;
782 
signal idc_ld_y_cml_3 :  std_logic;
783 
signal idc_ld_y_cml_2 :  std_logic;
784 
signal idc_ld_y_cml_1 :  std_logic;
785 
signal idc_ldd_y_cml_3 :  std_logic;
786 
signal idc_ldd_y_cml_2 :  std_logic;
787 
signal idc_ldd_y_cml_1 :  std_logic;
788 
signal idc_ld_z_cml_3 :  std_logic;
789 
signal idc_ld_z_cml_2 :  std_logic;
790 
signal idc_ld_z_cml_1 :  std_logic;
791 
signal idc_ldd_z_cml_3 :  std_logic;
792 
signal idc_ldd_z_cml_2 :  std_logic;
793 
signal idc_ldd_z_cml_1 :  std_logic;
794 
signal idc_ldi_cml_2 :  std_logic;
795 
signal idc_ldi_cml_1 :  std_logic;
796 
signal idc_lds_cml_3 :  std_logic;
797 
signal idc_lds_cml_2 :  std_logic;
798 
signal idc_lds_cml_1 :  std_logic;
799 
signal idc_lpm_cml_3 :  std_logic;
800 
signal idc_lsr_cml_3 :  std_logic;
801 
signal idc_lsr_cml_2 :  std_logic;
802 
signal idc_mov_cml_2 :  std_logic;
803 
signal idc_neg_cml_3 :  std_logic;
804 
signal idc_neg_cml_2 :  std_logic;
805 
signal idc_or_cml_3 :  std_logic;
806 
signal idc_or_cml_2 :  std_logic;
807 
signal idc_ori_out_cml_out :  std_logic;
808 
signal idc_ori_cml_3 :  std_logic;
809 
signal idc_ori_cml_2 :  std_logic;
810 
signal idc_ori_cml_1 :  std_logic;
811 
signal idc_out_cml_2 :  std_logic;
812 
signal idc_out_cml_1 :  std_logic;
813 
signal idc_pop_cml_3 :  std_logic;
814 
signal idc_pop_cml_2 :  std_logic;
815 
signal idc_pop_cml_1 :  std_logic;
816 
signal idc_push_cml_3 :  std_logic;
817 
signal idc_push_cml_2 :  std_logic;
818 
signal idc_push_cml_1 :  std_logic;
819 
signal idc_rcall_cml_3 :  std_logic;
820 
signal idc_rcall_cml_2 :  std_logic;
821 
signal idc_rcall_cml_1 :  std_logic;
822 
signal idc_ret_cml_3 :  std_logic;
823 
signal idc_ret_cml_2 :  std_logic;
824 
signal idc_ret_cml_1 :  std_logic;
825 
signal idc_reti_out_cml_out :  std_logic;
826 
signal idc_reti_cml_3 :  std_logic;
827 
signal idc_reti_cml_2 :  std_logic;
828 
signal idc_reti_cml_1 :  std_logic;
829 
signal idc_rjmp_cml_3 :  std_logic;
830 
signal idc_ror_cml_3 :  std_logic;
831 
signal idc_ror_cml_2 :  std_logic;
832 
signal idc_ror_cml_1 :  std_logic;
833 
signal idc_sbc_cml_3 :  std_logic;
834 
signal idc_sbc_cml_2 :  std_logic;
835 
signal idc_sbc_cml_1 :  std_logic;
836 
signal idc_sbci_cml_3 :  std_logic;
837 
signal idc_sbci_cml_2 :  std_logic;
838 
signal idc_sbci_cml_1 :  std_logic;
839 
signal idc_sbi_cml_3 :  std_logic;
840 
signal idc_sbi_cml_2 :  std_logic;
841 
signal idc_sbic_out_cml_out :  std_logic;
842 
signal idc_sbic_cml_3 :  std_logic;
843 
signal idc_sbic_cml_2 :  std_logic;
844 
signal idc_sbis_out_cml_out :  std_logic;
845 
signal idc_sbis_cml_3 :  std_logic;
846 
signal idc_sbis_cml_2 :  std_logic;
847 
signal idc_sbiw_cml_3 :  std_logic;
848 
signal idc_sbiw_cml_2 :  std_logic;
849 
signal idc_sbiw_cml_1 :  std_logic;
850 
signal idc_sbrc_cml_3 :  std_logic;
851 
signal idc_sbrs_cml_3 :  std_logic;
852 
signal idc_st_x_cml_3 :  std_logic;
853 
signal idc_st_x_cml_2 :  std_logic;
854 
signal idc_st_x_cml_1 :  std_logic;
855 
signal idc_st_y_cml_3 :  std_logic;
856 
signal idc_st_y_cml_2 :  std_logic;
857 
signal idc_st_y_cml_1 :  std_logic;
858 
signal idc_std_y_cml_3 :  std_logic;
859 
signal idc_std_y_cml_2 :  std_logic;
860 
signal idc_std_y_cml_1 :  std_logic;
861 
signal idc_st_z_cml_3 :  std_logic;
862 
signal idc_st_z_cml_2 :  std_logic;
863 
signal idc_st_z_cml_1 :  std_logic;
864 
signal idc_std_z_cml_3 :  std_logic;
865 
signal idc_std_z_cml_2 :  std_logic;
866 
signal idc_std_z_cml_1 :  std_logic;
867 
signal idc_sts_cml_3 :  std_logic;
868 
signal idc_sts_cml_2 :  std_logic;
869 
signal idc_sts_cml_1 :  std_logic;
870 
signal idc_sub_cml_3 :  std_logic;
871 
signal idc_sub_cml_2 :  std_logic;
872 
signal idc_sub_cml_1 :  std_logic;
873 
signal idc_subi_cml_3 :  std_logic;
874 
signal idc_subi_cml_2 :  std_logic;
875 
signal idc_subi_cml_1 :  std_logic;
876 
signal idc_swap_cml_2 :  std_logic;
877 
signal pre_dec_cml_out :  std_logic;
878 
signal idc_prdec_cml_3 :  std_logic;
879 
signal idc_prdec_cml_2 :  std_logic;
880 
signal idc_prdec_cml_1 :  std_logic;
881 
signal sreg_bop_wr_en_cml_3 :  std_logic_vector ( 7 downto 0 );
882 
signal sreg_adr_eq_cml_3 :  std_logic;
883 
 
884 
begin
885 
 
886 
 
887 
 
888 
process(cp2_cml_1) begin
889 
if (cp2_cml_1 = '1' and cp2_cml_1'event) then
890 
        inst_cml_1 <= inst;
891 
        cpuwait_cml_1 <= cpuwait;
892 
        irqlines_cml_1 <= irqlines;
893 
        reg_rr_out_cml_1 <= reg_rr_out;
894 
        bitpr_io_out_cml_1 <= bitpr_io_out;
895 
        irqack_int_cml_1 <= irqack_int;
896 
        irqackad_int_cml_1 <= irqackad_int;
897 
        adiw_sbiw_encoder_out_cml_1 <= adiw_sbiw_encoder_out;
898 
        adiw_sbiw_encoder_mux_out_cml_1 <= adiw_sbiw_encoder_mux_out;
899 
        program_counter_tmp_cml_1 <= program_counter_tmp;
900 
        program_counter_cml_1 <= program_counter;
901 
        program_counter_high_fr_cml_1 <= program_counter_high_fr;
902 
        pc_low_cml_1 <= pc_low;
903 
        pc_high_cml_1 <= pc_high;
904 
        reg_file_adr_space_cml_1 <= reg_file_adr_space;
905 
        io_file_adr_space_cml_1 <= io_file_adr_space;
906 
        nirq_st0_cml_1 <= nirq_st0;
907 
        irq_st1_cml_1 <= irq_st1;
908 
        irq_st2_cml_1 <= irq_st2;
909 
        irq_st3_cml_1 <= irq_st3;
910 
        ncall_st0_cml_1 <= ncall_st0;
911 
        call_st1_cml_1 <= call_st1;
912 
        call_st2_cml_1 <= call_st2;
913 
        call_st3_cml_1 <= call_st3;
914 
        nrcall_st0_cml_1 <= nrcall_st0;
915 
        rcall_st1_cml_1 <= rcall_st1;
916 
        rcall_st2_cml_1 <= rcall_st2;
917 
        nicall_st0_cml_1 <= nicall_st0;
918 
        icall_st1_cml_1 <= icall_st1;
919 
        icall_st2_cml_1 <= icall_st2;
920 
        njmp_st0_cml_1 <= njmp_st0;
921 
        jmp_st1_cml_1 <= jmp_st1;
922 
        jmp_st2_cml_1 <= jmp_st2;
923 
        ijmp_st_cml_1 <= ijmp_st;
924 
        rjmp_st_cml_1 <= rjmp_st;
925 
        nret_st0_cml_1 <= nret_st0;
926 
        ret_st1_cml_1 <= ret_st1;
927 
        ret_st2_cml_1 <= ret_st2;
928 
        ret_st3_cml_1 <= ret_st3;
929 
        nreti_st0_cml_1 <= nreti_st0;
930 
        reti_st1_cml_1 <= reti_st1;
931 
        reti_st2_cml_1 <= reti_st2;
932 
        reti_st3_cml_1 <= reti_st3;
933 
        brxx_st_cml_1 <= brxx_st;
934 
        adiw_st_cml_1 <= adiw_st;
935 
        sbiw_st_cml_1 <= sbiw_st;
936 
        nskip_inst_st0_cml_1 <= nskip_inst_st0;
937 
        skip_inst_st1_cml_1 <= skip_inst_st1;
938 
        skip_inst_st2_cml_1 <= skip_inst_st2;
939 
        nlpm_st0_cml_1 <= nlpm_st0;
940 
        lpm_st1_cml_1 <= lpm_st1;
941 
        lpm_st2_cml_1 <= lpm_st2;
942 
        sts_st_cml_1 <= sts_st;
943 
        lds_st_cml_1 <= lds_st;
944 
        st_st_cml_1 <= st_st;
945 
        ld_st_cml_1 <= ld_st;
946 
        sbi_st_cml_1 <= sbi_st;
947 
        cbi_st_cml_1 <= cbi_st;
948 
        push_st_cml_1 <= push_st;
949 
        pop_st_cml_1 <= pop_st;
950 
        ramadr_int_cml_1 <= ramadr_int;
951 
        ramre_int_cml_1 <= ramre_int;
952 
        ramwe_int_cml_1 <= ramwe_int;
953 
        instruction_reg_cml_1 <= instruction_reg;
954 
        instruction_code_reg_cml_1 <= instruction_code_reg;
955 
        irq_vector_adr_cml_1 <= irq_vector_adr;
956 
        pc_for_interrupt_cml_1 <= pc_for_interrupt;
957 
        dex_dat8_immed_cml_1 <= dex_dat8_immed;
958 
        dex_adrreg_d_cml_1 <= dex_adrreg_d;
959 
        dex_bitop_bitnum_cml_1 <= dex_bitop_bitnum;
960 
        dex_adrreg_d_latched_cml_1 <= dex_adrreg_d_latched;
961 
        gp_reg_tmp_cml_1 <= gp_reg_tmp;
962 
        cbi_sbi_io_adr_tmp_cml_1 <= cbi_sbi_io_adr_tmp;
963 
        cbi_sbi_bit_num_tmp_cml_1 <= cbi_sbi_bit_num_tmp;
964 
        idc_adc_cml_1 <= idc_adc;
965 
        idc_adiw_cml_1 <= idc_adiw;
966 
        idc_andi_cml_1 <= idc_andi;
967 
        idc_cp_cml_1 <= idc_cp;
968 
        idc_cpc_cml_1 <= idc_cpc;
969 
        idc_cpi_cml_1 <= idc_cpi;
970 
        idc_cpse_cml_1 <= idc_cpse;
971 
        idc_icall_cml_1 <= idc_icall;
972 
        idc_ld_x_cml_1 <= idc_ld_x;
973 
        idc_ld_y_cml_1 <= idc_ld_y;
974 
        idc_ldd_y_cml_1 <= idc_ldd_y;
975 
        idc_ld_z_cml_1 <= idc_ld_z;
976 
        idc_ldd_z_cml_1 <= idc_ldd_z;
977 
        idc_ldi_cml_1 <= idc_ldi;
978 
        idc_lds_cml_1 <= idc_lds;
979 
        idc_ori_cml_1 <= idc_ori;
980 
        idc_out_cml_1 <= idc_out;
981 
        idc_pop_cml_1 <= idc_pop;
982 
        idc_push_cml_1 <= idc_push;
983 
        idc_rcall_cml_1 <= idc_rcall;
984 
        idc_ret_cml_1 <= idc_ret;
985 
        idc_reti_cml_1 <= idc_reti;
986 
        idc_ror_cml_1 <= idc_ror;
987 
        idc_sbc_cml_1 <= idc_sbc;
988 
        idc_sbci_cml_1 <= idc_sbci;
989 
        idc_sbiw_cml_1 <= idc_sbiw;
990 
        idc_st_x_cml_1 <= idc_st_x;
991 
        idc_st_y_cml_1 <= idc_st_y;
992 
        idc_std_y_cml_1 <= idc_std_y;
993 
        idc_st_z_cml_1 <= idc_st_z;
994 
        idc_std_z_cml_1 <= idc_std_z;
995 
        idc_sts_cml_1 <= idc_sts;
996 
        idc_sub_cml_1 <= idc_sub;
997 
        idc_subi_cml_1 <= idc_subi;
998 
        idc_prdec_cml_1 <= idc_prdec;
999 
end if;
1000 
end process;
1001 
 
1002 
process(cp2_cml_2) begin
1003 
if (cp2_cml_2 = '1' and cp2_cml_2'event) then
1004 
        inst_cml_2 <= inst_cml_1;
1005 
        cpuwait_cml_2 <= cpuwait_cml_1;
1006 
        dbusin_cml_2 <= dbusin;
1007 
        irqlines_cml_2 <= irqlines_cml_1;
1008 
        reg_rd_out_cml_2 <= reg_rd_out;
1009 
        reg_rr_out_cml_2 <= reg_rr_out_cml_1;
1010 
        reg_h_out_cml_2 <= reg_h_out;
1011 
        reg_z_out_cml_2 <= reg_z_out;
1012 
        spl_out_cml_2 <= spl_out;
1013 
        sph_out_cml_2 <= sph_out;
1014 
        rampz_out_cml_2 <= rampz_out;
1015 
        bitpr_io_out_cml_2 <= bitpr_io_out_cml_1;
1016 
        irqack_int_cml_2 <= irqack_int_cml_1;
1017 
        irqackad_int_cml_2 <= irqackad_int_cml_1;
1018 
        adiw_sbiw_encoder_out_cml_2 <= adiw_sbiw_encoder_out_cml_1;
1019 
        adiw_sbiw_encoder_mux_out_cml_2 <= adiw_sbiw_encoder_mux_out_cml_1;
1020 
        program_counter_tmp_cml_2 <= program_counter_tmp_cml_1;
1021 
        program_counter_cml_2 <= program_counter_cml_1;
1022 
        program_counter_high_fr_cml_2 <= program_counter_high_fr_cml_1;
1023 
        pc_low_cml_2 <= pc_low_cml_1;
1024 
        pc_high_cml_2 <= pc_high_cml_1;
1025 
        reg_file_adr_space_cml_2 <= reg_file_adr_space_cml_1;
1026 
        io_file_adr_space_cml_2 <= io_file_adr_space_cml_1;
1027 
        nirq_st0_cml_2 <= nirq_st0_cml_1;
1028 
        irq_st1_cml_2 <= irq_st1_cml_1;
1029 
        irq_st2_cml_2 <= irq_st2_cml_1;
1030 
        irq_st3_cml_2 <= irq_st3_cml_1;
1031 
        ncall_st0_cml_2 <= ncall_st0_cml_1;
1032 
        call_st1_cml_2 <= call_st1_cml_1;
1033 
        call_st2_cml_2 <= call_st2_cml_1;
1034 
        call_st3_cml_2 <= call_st3_cml_1;
1035 
        nrcall_st0_cml_2 <= nrcall_st0_cml_1;
1036 
        rcall_st1_cml_2 <= rcall_st1_cml_1;
1037 
        rcall_st2_cml_2 <= rcall_st2_cml_1;
1038 
        nicall_st0_cml_2 <= nicall_st0_cml_1;
1039 
        icall_st1_cml_2 <= icall_st1_cml_1;
1040 
        icall_st2_cml_2 <= icall_st2_cml_1;
1041 
        njmp_st0_cml_2 <= njmp_st0_cml_1;
1042 
        jmp_st1_cml_2 <= jmp_st1_cml_1;
1043 
        jmp_st2_cml_2 <= jmp_st2_cml_1;
1044 
        ijmp_st_cml_2 <= ijmp_st_cml_1;
1045 
        rjmp_st_cml_2 <= rjmp_st_cml_1;
1046 
        nret_st0_cml_2 <= nret_st0_cml_1;
1047 
        ret_st1_cml_2 <= ret_st1_cml_1;
1048 
        ret_st2_cml_2 <= ret_st2_cml_1;
1049 
        ret_st3_cml_2 <= ret_st3_cml_1;
1050 
        nreti_st0_cml_2 <= nreti_st0_cml_1;
1051 
        reti_st1_cml_2 <= reti_st1_cml_1;
1052 
        reti_st2_cml_2 <= reti_st2_cml_1;
1053 
        reti_st3_cml_2 <= reti_st3_cml_1;
1054 
        brxx_st_cml_2 <= brxx_st_cml_1;
1055 
        adiw_st_cml_2 <= adiw_st_cml_1;
1056 
        sbiw_st_cml_2 <= sbiw_st_cml_1;
1057 
        nskip_inst_st0_cml_2 <= nskip_inst_st0_cml_1;
1058 
        skip_inst_st1_cml_2 <= skip_inst_st1_cml_1;
1059 
        skip_inst_st2_cml_2 <= skip_inst_st2_cml_1;
1060 
        nlpm_st0_cml_2 <= nlpm_st0_cml_1;
1061 
        lpm_st1_cml_2 <= lpm_st1_cml_1;
1062 
        lpm_st2_cml_2 <= lpm_st2_cml_1;
1063 
        sts_st_cml_2 <= sts_st_cml_1;
1064 
        lds_st_cml_2 <= lds_st_cml_1;
1065 
        st_st_cml_2 <= st_st_cml_1;
1066 
        ld_st_cml_2 <= ld_st_cml_1;
1067 
        sbi_st_cml_2 <= sbi_st_cml_1;
1068 
        cbi_st_cml_2 <= cbi_st_cml_1;
1069 
        push_st_cml_2 <= push_st_cml_1;
1070 
        pop_st_cml_2 <= pop_st_cml_1;
1071 
        adr_int_cml_2 <= adr_int;
1072 
        ramadr_int_cml_2 <= ramadr_int_cml_1;
1073 
        ramre_int_cml_2 <= ramre_int_cml_1;
1074 
        ramwe_int_cml_2 <= ramwe_int_cml_1;
1075 
        instruction_reg_cml_2 <= instruction_reg_cml_1;
1076 
        instruction_code_reg_cml_2 <= instruction_code_reg_cml_1;
1077 
        irq_vector_adr_cml_2 <= irq_vector_adr_cml_1;
1078 
        pc_for_interrupt_cml_2 <= pc_for_interrupt_cml_1;
1079 
        dex_dat8_immed_cml_2 <= dex_dat8_immed_cml_1;
1080 
        dex_adr5port_cml_2 <= dex_adr5port;
1081 
        dex_adr_disp_cml_2 <= dex_adr_disp;
1082 
        dex_adrreg_d_cml_2 <= dex_adrreg_d_cml_1;
1083 
        dex_bitop_bitnum_cml_2 <= dex_bitop_bitnum_cml_1;
1084 
        dex_adrreg_d_latched_cml_2 <= dex_adrreg_d_latched_cml_1;
1085 
        gp_reg_tmp_cml_2 <= gp_reg_tmp_cml_1;
1086 
        cbi_sbi_io_adr_tmp_cml_2 <= cbi_sbi_io_adr_tmp_cml_1;
1087 
        cbi_sbi_bit_num_tmp_cml_2 <= cbi_sbi_bit_num_tmp_cml_1;
1088 
        idc_adc_cml_2 <= idc_adc_cml_1;
1089 
        idc_add_cml_2 <= idc_add;
1090 
        idc_adiw_cml_2 <= idc_adiw_cml_1;
1091 
        idc_and_cml_2 <= idc_and;
1092 
        idc_andi_cml_2 <= idc_andi_cml_1;
1093 
        idc_asr_cml_2 <= idc_asr;
1094 
        idc_bld_cml_2 <= idc_bld;
1095 
        idc_cbi_cml_2 <= idc_cbi;
1096 
        idc_com_cml_2 <= idc_com;
1097 
        idc_cp_cml_2 <= idc_cp_cml_1;
1098 
        idc_cpc_cml_2 <= idc_cpc_cml_1;
1099 
        idc_cpi_cml_2 <= idc_cpi_cml_1;
1100 
        idc_cpse_cml_2 <= idc_cpse_cml_1;
1101 
        idc_dec_cml_2 <= idc_dec;
1102 
        idc_eor_cml_2 <= idc_eor;
1103 
        idc_icall_cml_2 <= idc_icall_cml_1;
1104 
        idc_in_cml_2 <= idc_in;
1105 
        idc_inc_cml_2 <= idc_inc;
1106 
        idc_ld_x_cml_2 <= idc_ld_x_cml_1;
1107 
        idc_ld_y_cml_2 <= idc_ld_y_cml_1;
1108 
        idc_ldd_y_cml_2 <= idc_ldd_y_cml_1;
1109 
        idc_ld_z_cml_2 <= idc_ld_z_cml_1;
1110 
        idc_ldd_z_cml_2 <= idc_ldd_z_cml_1;
1111 
        idc_ldi_cml_2 <= idc_ldi_cml_1;
1112 
        idc_lds_cml_2 <= idc_lds_cml_1;
1113 
        idc_lsr_cml_2 <= idc_lsr;
1114 
        idc_mov_cml_2 <= idc_mov;
1115 
        idc_neg_cml_2 <= idc_neg;
1116 
        idc_or_cml_2 <= idc_or;
1117 
        idc_ori_cml_2 <= idc_ori_cml_1;
1118 
        idc_out_cml_2 <= idc_out_cml_1;
1119 
        idc_pop_cml_2 <= idc_pop_cml_1;
1120 
        idc_push_cml_2 <= idc_push_cml_1;
1121 
        idc_rcall_cml_2 <= idc_rcall_cml_1;
1122 
        idc_ret_cml_2 <= idc_ret_cml_1;
1123 
        idc_reti_cml_2 <= idc_reti_cml_1;
1124 
        idc_ror_cml_2 <= idc_ror_cml_1;
1125 
        idc_sbc_cml_2 <= idc_sbc_cml_1;
1126 
        idc_sbci_cml_2 <= idc_sbci_cml_1;
1127 
        idc_sbi_cml_2 <= idc_sbi;
1128 
        idc_sbic_cml_2 <= idc_sbic;
1129 
        idc_sbis_cml_2 <= idc_sbis;
1130 
        idc_sbiw_cml_2 <= idc_sbiw_cml_1;
1131 
        idc_st_x_cml_2 <= idc_st_x_cml_1;
1132 
        idc_st_y_cml_2 <= idc_st_y_cml_1;
1133 
        idc_std_y_cml_2 <= idc_std_y_cml_1;
1134 
        idc_st_z_cml_2 <= idc_st_z_cml_1;
1135 
        idc_std_z_cml_2 <= idc_std_z_cml_1;
1136 
        idc_sts_cml_2 <= idc_sts_cml_1;
1137 
        idc_sub_cml_2 <= idc_sub_cml_1;
1138 
        idc_subi_cml_2 <= idc_subi_cml_1;
1139 
        idc_swap_cml_2 <= idc_swap;
1140 
        idc_prdec_cml_2 <= idc_prdec_cml_1;
1141 
end if;
1142 
end process;
1143 
 
1144 
process(cp2_cml_3) begin
1145 
if (cp2_cml_3 = '1' and cp2_cml_3'event) then
1146 
        inst_cml_3 <= inst_cml_2;
1147 
        cpuwait_cml_3 <= cpuwait_cml_2;
1148 
        dbusin_cml_3 <= dbusin_cml_2;
1149 
        alu_z_flag_out_cml_3 <= alu_z_flag_out;
1150 
        reg_rd_out_cml_3 <= reg_rd_out_cml_2;
1151 
        reg_z_out_cml_3 <= reg_z_out_cml_2;
1152 
        rampz_out_cml_3 <= rampz_out_cml_2;
1153 
        bit_test_op_out_cml_3 <= bit_test_op_out;
1154 
        ramadr_reg_in_cml_3 <= ramadr_reg_in;
1155 
        irqack_int_cml_3 <= irqack_int_cml_2;
1156 
        irqackad_int_cml_3 <= irqackad_int_cml_2;
1157 
        two_word_inst_cml_3 <= two_word_inst;
1158 
        adiw_sbiw_encoder_out_cml_3 <= adiw_sbiw_encoder_out_cml_2;
1159 
        adiw_sbiw_encoder_mux_out_cml_3 <= adiw_sbiw_encoder_mux_out_cml_2;
1160 
        program_counter_tmp_cml_3 <= program_counter_tmp_cml_2;
1161 
        program_counter_cml_3 <= program_counter_cml_2;
1162 
        program_counter_high_fr_cml_3 <= program_counter_high_fr_cml_2;
1163 
        pc_low_cml_3 <= pc_low_cml_2;
1164 
        pc_high_cml_3 <= pc_high_cml_2;
1165 
        reg_file_adr_space_cml_3 <= reg_file_adr_space_cml_2;
1166 
        io_file_adr_space_cml_3 <= io_file_adr_space_cml_2;
1167 
        nirq_st0_cml_3 <= nirq_st0_cml_2;
1168 
        irq_st1_cml_3 <= irq_st1_cml_2;
1169 
        irq_st2_cml_3 <= irq_st2_cml_2;
1170 
        irq_st3_cml_3 <= irq_st3_cml_2;
1171 
        ncall_st0_cml_3 <= ncall_st0_cml_2;
1172 
        call_st1_cml_3 <= call_st1_cml_2;
1173 
        call_st2_cml_3 <= call_st2_cml_2;
1174 
        call_st3_cml_3 <= call_st3_cml_2;
1175 
        nrcall_st0_cml_3 <= nrcall_st0_cml_2;
1176 
        rcall_st1_cml_3 <= rcall_st1_cml_2;
1177 
        rcall_st2_cml_3 <= rcall_st2_cml_2;
1178 
        nicall_st0_cml_3 <= nicall_st0_cml_2;
1179 
        icall_st1_cml_3 <= icall_st1_cml_2;
1180 
        icall_st2_cml_3 <= icall_st2_cml_2;
1181 
        njmp_st0_cml_3 <= njmp_st0_cml_2;
1182 
        jmp_st1_cml_3 <= jmp_st1_cml_2;
1183 
        jmp_st2_cml_3 <= jmp_st2_cml_2;
1184 
        ijmp_st_cml_3 <= ijmp_st_cml_2;
1185 
        rjmp_st_cml_3 <= rjmp_st_cml_2;
1186 
        nret_st0_cml_3 <= nret_st0_cml_2;
1187 
        ret_st1_cml_3 <= ret_st1_cml_2;
1188 
        ret_st2_cml_3 <= ret_st2_cml_2;
1189 
        ret_st3_cml_3 <= ret_st3_cml_2;
1190 
        nreti_st0_cml_3 <= nreti_st0_cml_2;
1191 
        reti_st1_cml_3 <= reti_st1_cml_2;
1192 
        reti_st2_cml_3 <= reti_st2_cml_2;
1193 
        reti_st3_cml_3 <= reti_st3_cml_2;
1194 
        brxx_st_cml_3 <= brxx_st_cml_2;
1195 
        adiw_st_cml_3 <= adiw_st_cml_2;
1196 
        sbiw_st_cml_3 <= sbiw_st_cml_2;
1197 
        nskip_inst_st0_cml_3 <= nskip_inst_st0_cml_2;
1198 
        skip_inst_st1_cml_3 <= skip_inst_st1_cml_2;
1199 
        skip_inst_st2_cml_3 <= skip_inst_st2_cml_2;
1200 
        nlpm_st0_cml_3 <= nlpm_st0_cml_2;
1201 
        lpm_st1_cml_3 <= lpm_st1_cml_2;
1202 
        lpm_st2_cml_3 <= lpm_st2_cml_2;
1203 
        sts_st_cml_3 <= sts_st_cml_2;
1204 
        lds_st_cml_3 <= lds_st_cml_2;
1205 
        st_st_cml_3 <= st_st_cml_2;
1206 
        ld_st_cml_3 <= ld_st_cml_2;
1207 
        sbi_st_cml_3 <= sbi_st_cml_2;
1208 
        cbi_st_cml_3 <= cbi_st_cml_2;
1209 
        push_st_cml_3 <= push_st_cml_2;
1210 
        pop_st_cml_3 <= pop_st_cml_2;
1211 
        iowe_int_cml_3 <= iowe_int;
1212 
        ramadr_int_cml_3 <= ramadr_int_cml_2;
1213 
        ramre_int_cml_3 <= ramre_int_cml_2;
1214 
        ramwe_int_cml_3 <= ramwe_int_cml_2;
1215 
        dbusout_int_cml_3 <= dbusout_int;
1216 
        instruction_reg_cml_3 <= instruction_reg_cml_2;
1217 
        instruction_code_reg_cml_3 <= instruction_code_reg_cml_2;
1218 
        irq_int_cml_3 <= irq_int;
1219 
        irq_vector_adr_cml_3 <= irq_vector_adr_cml_2;
1220 
        pc_for_interrupt_cml_3 <= pc_for_interrupt_cml_2;
1221 
        dex_adr5port_cml_3 <= dex_adr5port_cml_2;
1222 
        dex_adrreg_d_cml_3 <= dex_adrreg_d_cml_2;
1223 
        dex_bitop_bitnum_cml_3 <= dex_bitop_bitnum_cml_2;
1224 
        dex_adrreg_d_latched_cml_3 <= dex_adrreg_d_latched_cml_2;
1225 
        gp_reg_tmp_cml_3 <= gp_reg_tmp_cml_2;
1226 
        cbi_sbi_io_adr_tmp_cml_3 <= cbi_sbi_io_adr_tmp_cml_2;
1227 
        cbi_sbi_bit_num_tmp_cml_3 <= cbi_sbi_bit_num_tmp_cml_2;
1228 
        idc_adc_cml_3 <= idc_adc_cml_2;
1229 
        idc_add_cml_3 <= idc_add_cml_2;
1230 
        idc_adiw_cml_3 <= idc_adiw_cml_2;
1231 
        idc_and_cml_3 <= idc_and_cml_2;
1232 
        idc_andi_cml_3 <= idc_andi_cml_2;
1233 
        idc_asr_cml_3 <= idc_asr_cml_2;
1234 
        idc_bclr_cml_3 <= idc_bclr;
1235 
        idc_brbc_cml_3 <= idc_brbc;
1236 
        idc_brbs_cml_3 <= idc_brbs;
1237 
        idc_bset_cml_3 <= idc_bset;
1238 
        idc_bst_cml_3 <= idc_bst;
1239 
        idc_call_cml_3 <= idc_call;
1240 
        idc_cbi_cml_3 <= idc_cbi_cml_2;
1241 
        idc_com_cml_3 <= idc_com_cml_2;
1242 
        idc_cp_cml_3 <= idc_cp_cml_2;
1243 
        idc_cpc_cml_3 <= idc_cpc_cml_2;
1244 
        idc_cpi_cml_3 <= idc_cpi_cml_2;
1245 
        idc_cpse_cml_3 <= idc_cpse_cml_2;
1246 
        idc_dec_cml_3 <= idc_dec_cml_2;
1247 
        idc_eor_cml_3 <= idc_eor_cml_2;
1248 
        idc_icall_cml_3 <= idc_icall_cml_2;
1249 
        idc_ijmp_cml_3 <= idc_ijmp;
1250 
        idc_inc_cml_3 <= idc_inc_cml_2;
1251 
        idc_jmp_cml_3 <= idc_jmp;
1252 
        idc_ld_x_cml_3 <= idc_ld_x_cml_2;
1253 
        idc_ld_y_cml_3 <= idc_ld_y_cml_2;
1254 
        idc_ldd_y_cml_3 <= idc_ldd_y_cml_2;
1255 
        idc_ld_z_cml_3 <= idc_ld_z_cml_2;
1256 
        idc_ldd_z_cml_3 <= idc_ldd_z_cml_2;
1257 
        idc_lds_cml_3 <= idc_lds_cml_2;
1258 
        idc_lpm_cml_3 <= idc_lpm;
1259 
        idc_lsr_cml_3 <= idc_lsr_cml_2;
1260 
        idc_neg_cml_3 <= idc_neg_cml_2;
1261 
        idc_or_cml_3 <= idc_or_cml_2;
1262 
        idc_ori_cml_3 <= idc_ori_cml_2;
1263 
        idc_pop_cml_3 <= idc_pop_cml_2;
1264 
        idc_push_cml_3 <= idc_push_cml_2;
1265 
        idc_rcall_cml_3 <= idc_rcall_cml_2;
1266 
        idc_ret_cml_3 <= idc_ret_cml_2;
1267 
        idc_reti_cml_3 <= idc_reti_cml_2;
1268 
        idc_rjmp_cml_3 <= idc_rjmp;
1269 
        idc_ror_cml_3 <= idc_ror_cml_2;
1270 
        idc_sbc_cml_3 <= idc_sbc_cml_2;
1271 
        idc_sbci_cml_3 <= idc_sbci_cml_2;
1272 
        idc_sbi_cml_3 <= idc_sbi_cml_2;
1273 
        idc_sbic_cml_3 <= idc_sbic_cml_2;
1274 
        idc_sbis_cml_3 <= idc_sbis_cml_2;
1275 
        idc_sbiw_cml_3 <= idc_sbiw_cml_2;
1276 
        idc_sbrc_cml_3 <= idc_sbrc;
1277 
        idc_sbrs_cml_3 <= idc_sbrs;
1278 
        idc_st_x_cml_3 <= idc_st_x_cml_2;
1279 
        idc_st_y_cml_3 <= idc_st_y_cml_2;
1280 
        idc_std_y_cml_3 <= idc_std_y_cml_2;
1281 
        idc_st_z_cml_3 <= idc_st_z_cml_2;
1282 
        idc_std_z_cml_3 <= idc_std_z_cml_2;
1283 
        idc_sts_cml_3 <= idc_sts_cml_2;
1284 
        idc_sub_cml_3 <= idc_sub_cml_2;
1285 
        idc_subi_cml_3 <= idc_subi_cml_2;
1286 
        idc_prdec_cml_3 <= idc_prdec_cml_2;
1287 
        sreg_bop_wr_en_cml_3 <= sreg_bop_wr_en;
1288 
        sreg_adr_eq_cml_3 <= sreg_adr_eq;
1289 
end if;
1290 
end process;
1291 
sp_ndown_up <= sp_ndown_up_cml_out;
1292 
sp_en <= sp_en_cml_out;
1293 
reg_rd_in <= reg_rd_in_cml_out;
1294 
sreg_fl_in <= sreg_fl_in_cml_out;
1295 
irqack <= irqack_cml_out;
1296 
irqackad <= irqackad_cml_out;
1297 
reg_rd_adr <= reg_rd_adr_cml_out;
1298 
reg_rd_wr <= reg_rd_wr_cml_out;
1299 
iowe <= iowe_cml_out;
1300 
dbusout_int_route <= dbusout_int_route_cml_out;
1301 
irqok <= irqok_cml_out;
1302 
idc_adiw_out <= idc_adiw_out_cml_out;
1303 
idc_andi_out <= idc_andi_out_cml_out;
1304 
idc_bclr_out <= idc_bclr_out_cml_out;
1305 
idc_bset_out <= idc_bset_out_cml_out;
1306 
idc_bst_out <= idc_bst_out_cml_out;
1307 
reg_h_wr <= reg_h_wr_cml_out;
1308 
reg_h_adr <= reg_h_adr_cml_out;
1309 
idc_ori_out <= idc_ori_out_cml_out;
1310 
idc_reti_out <= idc_reti_out_cml_out;
1311 
idc_sbic_out <= idc_sbic_out_cml_out;
1312 
idc_sbis_out <= idc_sbis_out_cml_out;
1313 
pre_dec <= pre_dec_cml_out;
1314 
 
1315 
 
1316 
sreg_fl_wr_en <= sreg_i_wr_en & sreg_t_wr_en & sreg_h_wr_en & sreg_s_wr_en & sreg_v_wr_en & sreg_n_wr_en & sreg_z_wr_en & sreg_c_wr_en;
1317 
 
1318 
 
1319 
-- INSTRUCTION FETCH
1320 
instruction_reg_ena <= '1'; -- FOR TEST
1321 
 
1322 
-- SynEDA CoreMultiplier
1323 
-- assignment(s): instruction_reg
1324 
-- replace(s): inst, instruction_reg
1325 
 
1326 
instruction_fetch:process(cp2,ireset)
1327 
begin
1328 
if ireset='0' then                              -- RESET
1329 
instruction_reg <= (others => '0');
1330 
elsif (cp2='1' and cp2'event) then instruction_reg <= instruction_reg_cml_3;            -- CLOCK
1331 
 if (cp2en='1') then                                                      -- Clock enable
1332 
  if instruction_reg_ena='1' then
1333 
   instruction_reg <= inst_cml_3;
1334 
  end if;
1335 
 end if;
1336 
end if;
1337 
end process;
1338 
 
1339 
-- SynEDA CoreMultiplier
1340 
-- assignment(s): two_word_inst
1341 
-- replace(s): instruction_reg
1342 
 
1343 
-- TWO WORDS INSTRUCTION DETECTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)
1344 
two_word_inst <= '1' when
1345 
((instruction_reg_cml_2(15 downto 9)&instruction_reg_cml_2(3 downto 1)="1001010111") or    -- CALL
1346 
 (instruction_reg_cml_2(15 downto 9)&instruction_reg_cml_2(3 downto 1)="1001010110")) or   -- JMP
1347 
 (instruction_reg_cml_2(15 downto 9)&instruction_reg_cml_2(3 downto 0) = "10010000000") or -- LDS
1348 
 (instruction_reg_cml_2(15 downto 9)&instruction_reg_cml_2(3 downto 0) = "10010010000")    -- STS
1349 
   else '0';  -- TO DETECT CALL/JMP/LDS/STS INSTRUCTIONS FOR SBRS/SBRC/SBIS/SBIC/CPSE
1350 
 
1351 
 
1352 
 
1353 
-- DATA EXTRACTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)
1354 
dex_dat8_immed <= instruction_reg(11 downto 8) & instruction_reg(3 downto 0);
1355 
dex_dat6_immed <= instruction_reg(7 downto 6) & instruction_reg(3 downto 0);
1356 
-- SynEDA CoreMultiplier
1357 
-- assignment(s): dex_adr12mem_s
1358 
-- replace(s): instruction_reg
1359 
 
1360 
dex_adr12mem_s <= instruction_reg_cml_3(11 downto 0);
1361 
-- SynEDA CoreMultiplier
1362 
-- assignment(s): dex_adr6port
1363 
-- replace(s): instruction_reg
1364 
 
1365 
dex_adr6port <= instruction_reg_cml_1(10 downto 9) & instruction_reg_cml_1(3 downto 0);
1366 
-- SynEDA CoreMultiplier
1367 
-- assignment(s): dex_adr5port
1368 
-- replace(s): instruction_reg
1369 
 
1370 
dex_adr5port <= instruction_reg_cml_1(7 downto 3);
1371 
-- SynEDA CoreMultiplier
1372 
-- assignment(s): dex_adr_disp
1373 
-- replace(s): instruction_reg
1374 
 
1375 
dex_adr_disp <= instruction_reg_cml_1(13) & instruction_reg_cml_1(11 downto 10) & instruction_reg_cml_1(2 downto 0);
1376 
-- SynEDA CoreMultiplier
1377 
-- assignment(s): dex_condition
1378 
-- replace(s): instruction_reg
1379 
 
1380 
dex_condition <= instruction_reg_cml_2(2 downto 0);
1381 
-- SynEDA CoreMultiplier
1382 
-- assignment(s): dex_bitnum_sreg
1383 
-- replace(s): instruction_reg
1384 
 
1385 
dex_bitop_bitnum <= instruction_reg(2 downto 0);      -- NUMBER(POSITION) OF TESTING BIT IN SBRC/SBRS/SBIC/SBIS INSTRUCTION
1386 
dex_bitnum_sreg <= instruction_reg_cml_2(6 downto 4);
1387 
dex_adrreg_r  <=  instruction_reg(9) & instruction_reg(3 downto 0);
1388 
dex_adrreg_d  <= instruction_reg(8 downto 4);
1389 
-- SynEDA CoreMultiplier
1390 
-- assignment(s): dex_brxx_offset
1391 
-- replace(s): instruction_reg
1392 
 
1393 
dex_brxx_offset <= instruction_reg_cml_3(9 downto 3);       -- OFFSET FOR BRBC/BRBS
1394 
dex_adiw_sbiw_reg_adr <= instruction_reg(5 downto 4); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS
1395 
--dex_adrindreg <= instruction_reg(3 downto 2);
1396 
 
1397 
-- SynEDA CoreMultiplier
1398 
-- assignment(s): dex_adrreg_d_latched
1399 
-- replace(s): dex_adrreg_d, dex_adrreg_d_latched, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1400 
 
1401 
-- LATCH Rd ADDDRESS FOR LDS/STS/POP INSTRUCTIONS
1402 
latcht_rd_adr:process(cp2,ireset)
1403 
begin
1404 
if ireset ='0' then
1405 
dex_adrreg_d_latched <= (others => '0');
1406 
elsif (cp2='1' and cp2'event) then dex_adrreg_d_latched <= dex_adrreg_d_latched_cml_3;
1407 
 if (cp2en='1') then                                                      -- Clock enable
1408 
  if ((idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ldd_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_z_cml_3) or idc_sts_cml_3 or
1409 
          (idc_st_x_cml_3  or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3)or idc_lds_cml_3 or
1410 
           idc_pop_cml_3)='1' then
1411 
   dex_adrreg_d_latched <= dex_adrreg_d_cml_3;
1412 
  end if;
1413 
 end if;
1414 
end if;
1415 
end process;
1416 
-- +++++++++++++++++++++++++++++++++++++++++++++++++
1417 
 
1418 
 
1419 
-- R24:R25/R26:R27/R28:R29/R30:R31 ADIW/SBIW  ADDRESS CONTROL LOGIC
1420 
adiw_sbiw_encoder_out <= "11"&dex_adiw_sbiw_reg_adr&'0';
1421 
 
1422 
-- SynEDA CoreMultiplier
1423 
-- assignment(s): adiw_sbiw_encoder_mux_out
1424 
-- replace(s): adiw_sbiw_encoder_out, adiw_sbiw_encoder_mux_out
1425 
 
1426 
adiw_sbiw_high_reg_adr:process(cp2,ireset)
1427 
begin
1428 
if ireset ='0' then
1429 
adiw_sbiw_encoder_mux_out <= (others=>'0');
1430 
elsif(cp2='1' and cp2'event) then adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_mux_out_cml_3;
1431 
 if (cp2en='1') then                                                      -- Clock enable
1432 
  adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_out_cml_3 +1;
1433 
 end if;
1434 
end if;
1435 
end process;
1436 
 
1437 
-- ##########################
1438 
 
1439 
-- NOP INSERTION
1440 
 
1441 
--instruction_code_reg <= instruction_reg when nop_insert_st='0' else (others => '0');
1442 
instruction_code_reg <= (others => '0') when (nop_insert_st='1') else -- NOP
1443 
                        instruction_reg;                                                                                                -- Instruction
1444 
 
1445 
 
1446 
nop_insert_st <= adiw_st or sbiw_st or cbi_st or sbi_st or rjmp_st or ijmp_st or pop_st or push_st or
1447 
              brxx_st or ld_st or st_st or ncall_st0 or nirq_st0 or nret_st0 or nreti_st0 or nlpm_st0 or njmp_st0 or
1448 
              nrcall_st0 or nicall_st0 or sts_st or lds_st or nskip_inst_st0;
1449 
 
1450 
 
1451 
-- INSTRUCTION DECODER (CONNECTED AFTER NOP INSERTION LOGIC)
1452 
 
1453 
-- SynEDA CoreMultiplier
1454 
-- assignment(s): idc_add
1455 
-- replace(s): instruction_code_reg
1456 
 
1457 
idc_adc  <= '1' when instruction_code_reg(15 downto 10) = "000111" else '0'; -- 000111XXXXXXXXXX
1458 
idc_add  <= '1' when instruction_code_reg_cml_1(15 downto 10) = "000011" else '0'; -- 000011XXXXXXXXXX
1459 
 
1460 
idc_adiw <= '1' when instruction_code_reg(15 downto 8) = "10010110" else '0'; -- 10010110XXXXXXXX
1461 
 
1462 
-- SynEDA CoreMultiplier
1463 
-- assignment(s): idc_and
1464 
-- replace(s): instruction_code_reg
1465 
 
1466 
idc_and  <= '1' when instruction_code_reg_cml_1(15 downto 10) = "001000" else '0'; -- 001000XXXXXXXXXX
1467 
idc_andi <= '1' when instruction_code_reg(15 downto 12) = "0111" else '0'; -- 0111XXXXXXXXXXXX
1468 
 
1469 
-- SynEDA CoreMultiplier
1470 
-- assignment(s): idc_asr
1471 
-- replace(s): instruction_code_reg
1472 
 
1473 
idc_asr  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100101" else '0'; -- 1001010XXXXX0101
1474 
 
1475 
-- SynEDA CoreMultiplier
1476 
-- assignment(s): idc_bclr
1477 
-- replace(s): instruction_code_reg
1478 
 
1479 
idc_bclr <= '1' when instruction_code_reg_cml_2(15 downto 7)&instruction_code_reg_cml_2(3 downto 0) = "1001010011000" else '0'; -- 100101001XXX1000
1480 
 
1481 
-- SynEDA CoreMultiplier
1482 
-- assignment(s): idc_bld
1483 
-- replace(s): instruction_code_reg
1484 
 
1485 
idc_bld  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3) = "11111000" else '0'; -- 1111100XXXXX0XXX
1486 
 
1487 
-- SynEDA CoreMultiplier
1488 
-- assignment(s): idc_brbs
1489 
-- replace(s): instruction_code_reg
1490 
 
1491 
-- SynEDA CoreMultiplier
1492 
-- assignment(s): idc_brbc
1493 
-- replace(s): instruction_code_reg
1494 
 
1495 
idc_brbc <= '1' when instruction_code_reg_cml_2(15 downto 10) = "111101" else '0'; -- 111101XXXXXXXXXX
1496 
idc_brbs <= '1' when instruction_code_reg_cml_2(15 downto 10) = "111100" else '0'; -- 111100XXXXXXXXXX
1497 
 
1498 
-- SynEDA CoreMultiplier
1499 
-- assignment(s): idc_bset
1500 
-- replace(s): instruction_code_reg
1501 
 
1502 
idc_bset <= '1' when instruction_code_reg_cml_2(15 downto 7)&instruction_code_reg_cml_2(3 downto 0) = "1001010001000" else '0'; -- 100101000XXX1000
1503 
 
1504 
-- SynEDA CoreMultiplier
1505 
-- assignment(s): idc_bst
1506 
-- replace(s): instruction_code_reg
1507 
 
1508 
idc_bst  <= '1' when instruction_code_reg_cml_2(15 downto 9) = "1111101" else '0'; -- 1111101XXXXXXXXX
1509 
 
1510 
-- SynEDA CoreMultiplier
1511 
-- assignment(s): idc_call
1512 
-- replace(s): instruction_code_reg
1513 
 
1514 
idc_call <= '1' when instruction_code_reg_cml_2(15 downto 9)&instruction_code_reg_cml_2(3 downto 1) = "1001010111" else '0'; -- 1001010XXXXX111X
1515 
 
1516 
-- SynEDA CoreMultiplier
1517 
-- assignment(s): idc_cbi
1518 
-- replace(s): instruction_code_reg
1519 
 
1520 
idc_cbi  <= '1' when instruction_code_reg_cml_1(15 downto 8) = "10011000" else '0'; -- 10011000XXXXXXXX
1521 
 
1522 
-- SynEDA CoreMultiplier
1523 
-- assignment(s): idc_com
1524 
-- replace(s): instruction_code_reg
1525 
 
1526 
idc_com  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100000" else '0'; -- 1001010XXXXX0000
1527 
 
1528 
idc_cp   <= '1' when instruction_code_reg(15 downto 10) = "000101" else '0'; -- 000101XXXXXXXXXX
1529 
 
1530 
idc_cpc  <= '1' when instruction_code_reg(15 downto 10) = "000001" else '0'; -- 000001XXXXXXXXXX
1531 
 
1532 
idc_cpi  <= '1' when instruction_code_reg(15 downto 12) = "0011" else '0'; -- 0011XXXXXXXXXXXX
1533 
 
1534 
idc_cpse <= '1' when instruction_code_reg(15 downto 10) = "000100" else '0'; -- 000100XXXXXXXXXX
1535 
 
1536 
-- SynEDA CoreMultiplier
1537 
-- assignment(s): idc_dec
1538 
-- replace(s): instruction_code_reg
1539 
 
1540 
idc_dec  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010101010" else '0'; -- 1001010XXXXX1010
1541 
 
1542 
-- SynEDA CoreMultiplier
1543 
-- assignment(s): idc_elpm
1544 
-- replace(s): instruction_code_reg
1545 
 
1546 
idc_elpm <= '1' when instruction_code_reg_cml_3 = "1001010111011000" else '0'; -- 1001010111011000
1547 
 
1548 
-- SynEDA CoreMultiplier
1549 
-- assignment(s): idc_eor
1550 
-- replace(s): instruction_code_reg
1551 
 
1552 
idc_eor  <= '1' when instruction_code_reg_cml_1(15 downto 10) = "001001" else '0'; -- 001001XXXXXXXXXX
1553 
 
1554 
idc_icall<= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101011001" else '0'; -- 10010101XXXX1001
1555 
 
1556 
-- SynEDA CoreMultiplier
1557 
-- assignment(s): idc_ijmp
1558 
-- replace(s): instruction_code_reg
1559 
 
1560 
idc_ijmp <= '1' when instruction_code_reg_cml_2(15 downto 8)&instruction_code_reg_cml_2(3 downto 0) = "100101001001" else '0'; -- 10010100XXXX1001
1561 
 
1562 
-- SynEDA CoreMultiplier
1563 
-- assignment(s): idc_in
1564 
-- replace(s): instruction_code_reg
1565 
 
1566 
idc_in   <= '1' when instruction_code_reg_cml_1(15 downto 11) = "10110" else '0'; -- 10110XXXXXXXXXXX
1567 
 
1568 
-- SynEDA CoreMultiplier
1569 
-- assignment(s): idc_inc
1570 
-- replace(s): instruction_code_reg
1571 
 
1572 
idc_inc  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100011" else '0'; -- 1001010XXXXX0011
1573 
 
1574 
-- SynEDA CoreMultiplier
1575 
-- assignment(s): idc_jmp
1576 
-- replace(s): instruction_code_reg
1577 
 
1578 
idc_jmp  <= '1' when instruction_code_reg_cml_2(15 downto 9)&instruction_code_reg_cml_2(3 downto 1) = "1001010110" else '0'; -- 1001010XXXXX110X
1579 
 
1580 
 
1581 
-- LD,LDD
1582 
idc_ld_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001100" or
1583 
                     instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001101"  or
1584 
                                         instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001110" else '0';
1585 
 
1586 
idc_ld_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001001" or
1587 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001010") else '0';
1588 
 
1589 
idc_ldd_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10001" else '0'; -- 10X0XX0XXXXX1XXX
1590 
 
1591 
idc_ld_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000001" or
1592 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000010") else '0';
1593 
 
1594 
idc_ldd_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10000" else '0'; -- 10X0XX0XXXXX0XXX
1595 
-- ######
1596 
 
1597 
 
1598 
idc_ldi <= '1' when instruction_code_reg(15 downto 12) = "1110" else '0'; -- 1110XXXXXXXXXXXX
1599 
 
1600 
idc_lds <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010000000" else '0'; -- 1001000XXXXX0000
1601 
 
1602 
-- SynEDA CoreMultiplier
1603 
-- assignment(s): idc_lpm
1604 
-- replace(s): instruction_code_reg
1605 
 
1606 
idc_lpm <= '1' when instruction_code_reg_cml_2 = "1001010111001000" else '0'; -- 1001010111001000
1607 
 
1608 
-- SynEDA CoreMultiplier
1609 
-- assignment(s): idc_lsr
1610 
-- replace(s): instruction_code_reg
1611 
 
1612 
idc_lsr <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100110" else '0'; -- 1001010XXXXX0110
1613 
 
1614 
-- SynEDA CoreMultiplier
1615 
-- assignment(s): idc_mov
1616 
-- replace(s): instruction_code_reg
1617 
 
1618 
idc_mov <= '1' when instruction_code_reg_cml_1(15 downto 10) = "001011" else '0'; -- 001011XXXXXXXXXX
1619 
 
1620 
idc_mul <= '1' when instruction_code_reg(15 downto 10) = "100111" else '0'; -- 100111XXXXXXXXXX
1621 
 
1622 
-- SynEDA CoreMultiplier
1623 
-- assignment(s): idc_neg
1624 
-- replace(s): instruction_code_reg
1625 
 
1626 
idc_neg <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100001" else '0'; -- 1001010XXXXX0001
1627 
 
1628 
idc_nop <= '1' when instruction_code_reg = "0000000000000000" else '0'; -- 0000000000000000
1629 
 
1630 
-- SynEDA CoreMultiplier
1631 
-- assignment(s): idc_or
1632 
-- replace(s): instruction_code_reg
1633 
 
1634 
idc_or  <= '1' when instruction_code_reg_cml_1(15 downto 10) = "001010" else '0'; -- 001010XXXXXXXXXX
1635 
 
1636 
idc_ori <= '1' when instruction_code_reg(15 downto 12) = "0110" else '0'; -- 0110XXXXXXXXXXXX
1637 
 
1638 
idc_out <= '1' when instruction_code_reg(15 downto 11) = "10111" else '0'; -- 10111XXXXXXXXXXX
1639 
 
1640 
idc_pop <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001111" else '0'; -- 1001000XXXXX1111
1641 
 
1642 
idc_push<= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011111" else '0'; -- 1001001XXXXX1111
1643 
 
1644 
idc_rcall<= '1' when instruction_code_reg(15 downto 12) = "1101" else '0'; -- 1101XXXXXXXXXXXX
1645 
 
1646 
idc_ret  <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101001000" else '0'; -- 100101010XX01000
1647 
 
1648 
idc_reti <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101011000" else '0'; -- 100101010XX11000
1649 
 
1650 
-- SynEDA CoreMultiplier
1651 
-- assignment(s): idc_rjmp
1652 
-- replace(s): instruction_code_reg
1653 
 
1654 
idc_rjmp <= '1' when instruction_code_reg_cml_2(15 downto 12) = "1100" else '0'; -- 1100XXXXXXXXXXXX
1655 
 
1656 
idc_ror  <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100111" else '0'; -- 1001010XXXXX0111
1657 
 
1658 
idc_sbc  <= '1' when instruction_code_reg(15 downto 10) = "000010" else '0'; -- 000010XXXXXXXXXX
1659 
 
1660 
idc_sbci <= '1' when instruction_code_reg(15 downto 12) = "0100" else '0'; -- 0100XXXXXXXXXXXX
1661 
 
1662 
-- SynEDA CoreMultiplier
1663 
-- assignment(s): idc_sbi
1664 
-- replace(s): instruction_code_reg
1665 
 
1666 
idc_sbi  <= '1' when instruction_code_reg_cml_1(15 downto 8) = "10011010" else '0'; -- 10011010XXXXXXXX
1667 
 
1668 
-- SynEDA CoreMultiplier
1669 
-- assignment(s): idc_sbic
1670 
-- replace(s): instruction_code_reg
1671 
 
1672 
idc_sbic <= '1' when instruction_code_reg_cml_1(15 downto 8) = "10011001" else '0'; -- 10011001XXXXXXXX
1673 
 
1674 
-- SynEDA CoreMultiplier
1675 
-- assignment(s): idc_sbis
1676 
-- replace(s): instruction_code_reg
1677 
 
1678 
idc_sbis <= '1' when instruction_code_reg_cml_1(15 downto 8) = "10011011" else '0'; -- 10011011XXXXXXXX
1679 
 
1680 
idc_sbiw <= '1' when instruction_code_reg(15 downto 8) = "10010111" else '0'; -- 10010111XXXXXXXX
1681 
 
1682 
-- SynEDA CoreMultiplier
1683 
-- assignment(s): idc_sbrc
1684 
-- replace(s): instruction_code_reg
1685 
 
1686 
idc_sbrc <= '1' when instruction_code_reg_cml_2(15 downto 9) = "1111110" else '0'; -- 1111110XXXXXXXXX
1687 
 
1688 
-- SynEDA CoreMultiplier
1689 
-- assignment(s): idc_sbrs
1690 
-- replace(s): instruction_code_reg
1691 
 
1692 
idc_sbrs <= '1' when instruction_code_reg_cml_2(15 downto 9) = "1111111" else '0'; -- 1111111XXXXXXXXX
1693 
 
1694 
-- SynEDA CoreMultiplier
1695 
-- assignment(s): idc_sleep
1696 
-- replace(s): instruction_code_reg
1697 
 
1698 
idc_sleep<= '1' when instruction_code_reg_cml_3(15 downto 5)&instruction_code_reg_cml_3(3 downto 0) = "100101011001000" else '0'; -- 10010101100X1000
1699 
 
1700 
 
1701 
-- ST,STD
1702 
idc_st_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011100" or
1703 
                     instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011101" or
1704 
                     instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011110" else '0';
1705 
 
1706 
idc_st_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011001" or
1707 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011010") else '0';
1708 
 
1709 
idc_std_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10011" else '0'; -- 10X0XX1XXXXX1XXX
1710 
 
1711 
idc_st_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010001" or
1712 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010010") else '0';
1713 
 
1714 
idc_std_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10010" else '0'; -- 10X0XX1XXXXX0XXX
1715 
-- ######
1716 
 
1717 
idc_sts  <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010010000" else '0'; -- 1001001XXXXX0000
1718 
 
1719 
idc_sub  <= '1' when instruction_code_reg(15 downto 10) = "000110" else '0'; -- 000110XXXXXXXXXX
1720 
 
1721 
idc_subi <= '1' when instruction_code_reg(15 downto 12) = "0101" else '0'; -- 0101XXXXXXXXXXXX
1722 
 
1723 
-- SynEDA CoreMultiplier
1724 
-- assignment(s): idc_swap
1725 
-- replace(s): instruction_code_reg
1726 
 
1727 
idc_swap <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100010" else '0'; -- 1001010XXXXX0010
1728 
 
1729 
-- SynEDA CoreMultiplier
1730 
-- assignment(s): idc_wdr
1731 
-- replace(s): instruction_code_reg
1732 
 
1733 
idc_wdr  <= '1' when instruction_code_reg_cml_3(15 downto 5)&instruction_code_reg_cml_3(3 downto 0) = "100101011011000" else '0'; -- 10010101101X1000
1734 
 
1735 
-- SynEDA CoreMultiplier
1736 
-- assignment(s): idc_psinc
1737 
-- replace(s): instruction_code_reg, idc_ld_x, idc_ld_y, idc_ld_z, idc_st_x, idc_st_y, idc_st_z
1738 
 
1739 
-- ADDITIONAL SIGNALS
1740 
idc_psinc <= '1' when (instruction_code_reg_cml_3(1 downto 0) = "01" and
1741 
 (idc_st_x_cml_3 or idc_st_y_cml_3 or idc_st_z_cml_3 or idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ld_z_cml_3)='1') else '0';  -- POST INCREMENT FOR LD/ST INSTRUCTIONS
1742 
 
1743 
idc_prdec <= '1' when (instruction_code_reg(1 downto 0)  = "10" and
1744 
 (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0';  -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
1745 
 
1746 
 
1747 
-- ##########################################################################################################
1748 
 
1749 
-- SynEDA CoreMultiplier
1750 
-- assignment(s): ramadr_reg_en
1751 
-- replace(s): cpuwait, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1752 
 
1753 
-- WRITE ENABLE SIGNALS FOR ramadr_reg
1754 
ramadr_reg_en <= idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ldd_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_z_cml_3 or idc_lds_cml_3 or    -- LD/LDD/LDS(two cycle execution)
1755 
                 idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3 or idc_sts_cml_3 or    -- ST/STS/STS(two cycle execution)
1756 
                                 idc_push_cml_3 or idc_pop_cml_3 or
1757 
                                 idc_rcall_cml_3 or (rcall_st1_cml_3 and not cpuwait_cml_3) or idc_icall_cml_3 or (icall_st1_cml_3 and not cpuwait_cml_3) or -- RCALL/ICALL
1758 
                                 call_st1_cml_3 or  (call_st2_cml_3 and not cpuwait_cml_3) or irq_st1_cml_3 or (irq_st2_cml_3 and not cpuwait_cml_3) or      -- CALL/IRQ
1759 
                                 idc_ret_cml_3 or (ret_st1_cml_3 and not cpuwait_cml_3 ) or idc_reti_cml_3 or (reti_st1_cml_3 and not cpuwait_cml_3);            -- RET/RETI  -- ??
1760 
 
1761 
 
1762 
-- SynEDA CoreMultiplier
1763 
-- assignment(s): ramadr_reg_in
1764 
-- replace(s): inst, cpuwait, reg_h_out, spl_out, sph_out, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, dex_adr_disp, idc_icall, idc_ld_x, idc_ld_y, idc_ld_z, idc_lds, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_st_x, idc_st_y, idc_st_z, idc_sts
1765 
 
1766 
-- RAMADR MUX
1767 
ramadr_reg_in <= sph_out_cml_2&spl_out_cml_2 when
1768 
  (idc_rcall_cml_2 or (rcall_st1_cml_2 and not cpuwait_cml_2)or idc_icall_cml_2 or (icall_st1_cml_2 and not cpuwait_cml_2)or  -- RCALL/ICALL
1769 
   call_st1_cml_2  or (call_st2_cml_2 and not cpuwait_cml_2) or irq_st1_cml_2   or (irq_st2_cml_2 and not cpuwait_cml_2)  or  -- CALL/IRQ
1770 
   idc_push_cml_2 )='1' else                                                                      -- PUSH
1771 
   (sph_out_cml_2&spl_out_cml_2)+1 when (idc_ret_cml_2 or (ret_st1_cml_2 and not cpuwait_cml_2)  or idc_reti_cml_2  or (reti_st1_cml_2 and not cpuwait_cml_2) or idc_pop_cml_2)='1' else  -- RET/RETI/POP
1772 
   inst_cml_2 when (idc_lds_cml_2 or idc_sts_cml_2) ='1' else     -- LDS/STS (two cycle execution)
1773 
   reg_h_out_cml_2 when (idc_ld_x_cml_2 or idc_ld_y_cml_2 or idc_ld_z_cml_2 or idc_st_x_cml_2 or idc_st_y_cml_2 or idc_st_z_cml_2)='1' else  -- LD/ST
1774 
   (reg_h_out_cml_2 + ("000000000"&dex_adr_disp_cml_2));                                                       -- LDD/STD
1775 
 
1776 
 
1777 
-- SynEDA CoreMultiplier
1778 
-- assignment(s): ramadr_int
1779 
-- replace(s): ramadr_reg_in, ramadr_int
1780 
 
1781 
-- ADDRESS REGISTER
1782 
ramadr_reg:process(cp2,ireset)
1783 
begin
1784 
if ireset='0' then
1785 
ramadr_int <= (others => '0');
1786 
elsif(cp2='1' and cp2'event) then ramadr_int <= ramadr_int_cml_3;
1787 
 if (cp2en='1') then                                                      -- Clock enable
1788 
  if (ramadr_reg_en='1') then
1789 
   ramadr_int <= ramadr_reg_in_cml_3;
1790 
  end if;
1791 
 end if;
1792 
end if;
1793 
end process;
1794 
 
1795 
ramadr <= ramadr_int;
1796 
 
1797 
-- SynEDA CoreMultiplier
1798 
-- assignment(s): reg_file_adr_space
1799 
-- replace(s): ramadr_reg_in, reg_file_adr_space
1800 
 
1801 
-- GENERAL PURPOSE REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS
1802 
gp_reg_adr:process(cp2,ireset)
1803 
begin
1804 
if ireset='0' then
1805 
reg_file_adr_space <='0';
1806 
elsif(cp2='1' and cp2'event) then reg_file_adr_space <= reg_file_adr_space_cml_3;
1807 
 if (cp2en='1') then                                                      -- Clock enable
1808 
  if (ramadr_reg_en='1') then
1809 
   if (ramadr_reg_in_cml_3(15 downto 5)=const_ram_to_reg) then
1810 
    reg_file_adr_space <= '1';                             -- ADRESS RANGE 0x0000-0x001F -> REGISTERS (R0-R31)
1811 
   else
1812 
    reg_file_adr_space <= '0';
1813 
   end if;
1814 
  end if;
1815 
 end if;
1816 
end if;
1817 
end process;
1818 
 
1819 
-- SynEDA CoreMultiplier
1820 
-- assignment(s): io_file_adr_space
1821 
-- replace(s): ramadr_reg_in, io_file_adr_space
1822 
 
1823 
-- I/O REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS
1824 
io_reg_adr:process(cp2,ireset)
1825 
begin
1826 
if ireset='0' then io_file_adr_space<='0';
1827 
elsif(cp2='1' and cp2'event) then io_file_adr_space <= io_file_adr_space_cml_3;
1828 
 if (cp2en='1') then                                                      -- Clock enable
1829 
  if (ramadr_reg_en='1') then
1830 
   if (ramadr_reg_in_cml_3(15 downto 5)=const_ram_to_io_a or ramadr_reg_in_cml_3(15 downto 5)=const_ram_to_io_b) then
1831 
    io_file_adr_space <= '1';                             -- ADRESS RANGE 0x0020-0x005F -> I/O PORTS (0x00-0x3F)
1832 
   else
1833 
    io_file_adr_space <= '0';
1834 
   end if;
1835 
  end if;
1836 
 end if;
1837 
end if;
1838 
end process;
1839 
 
1840 
 
1841 
 
1842 
-- ##########################################################################################################
1843 
 
1844 
 
1845 
-- REGRE/REGWE LOGIC (5 BIT ADDSRESS BUS (INTERNAL ONLY) 32 LOCATIONS (R0-R31))
1846 
 
1847 
-- SynEDA CoreMultiplier
1848 
-- assignment(s): alu_reg_wr
1849 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_adiw, idc_and, idc_andi, idc_asr, idc_com, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi, idc_swap
1850 
 
1851 
-- WRITE ENABLE FOR Rd REGISTERS
1852 
alu_reg_wr <= idc_adc_cml_2 or idc_add_cml_2 or idc_adiw_cml_2 or adiw_st_cml_2 or idc_sub_cml_2 or idc_subi_cml_2 or idc_sbc_cml_2 or idc_sbci_cml_2 or
1853 
              idc_sbiw_cml_2 or  sbiw_st_cml_2 or idc_and_cml_2 or idc_andi_cml_2 or idc_or_cml_2 or idc_ori_cml_2 or idc_eor_cml_2 or idc_com_cml_2 or
1854 
                          idc_neg_cml_2 or idc_inc_cml_2 or idc_dec_cml_2 or idc_lsr_cml_2 or idc_ror_cml_2 or idc_asr_cml_2 or idc_swap_cml_2;
1855 
 
1856 
 
1857 
-- SynEDA CoreMultiplier
1858 
-- assignment(s): reg_rd_wr
1859 
-- replace(s): reg_file_adr_space, lpm_st2, sts_st, lds_st, st_st, ld_st, pop_st, idc_bld, idc_in, idc_ldi, idc_mov
1860 
 
1861 
reg_rd_wr_cml_out <= idc_in_cml_2 or alu_reg_wr or idc_bld_cml_2 or             -- ALU INSTRUCTIONS + IN/BLD INSRTRUCTION
1862 
 (pop_st_cml_2 or ld_st_cml_2 or lds_st_cml_2)or                                            -- POP/LD/LDD/LDS INSTRUCTIONS
1863 
 ((st_st_cml_2 or sts_st_cml_2) and reg_file_adr_space_cml_2)or              -- ST/STD/STS INSTRUCTION
1864 
  lpm_st2_cml_2 or idc_ldi_cml_2 or idc_mov_cml_2;                            -- LPM/LDI/MOV INSTRUCTION
1865 
 
1866 
 
1867 
-- SynEDA CoreMultiplier
1868 
-- assignment(s): reg_rd_adr
1869 
-- replace(s): adiw_sbiw_encoder_out, adiw_sbiw_encoder_mux_out, reg_file_adr_space, adiw_st, sbiw_st, lpm_st2, sts_st, lds_st, st_st, ld_st, pop_st, ramadr_int, dex_adrreg_d, dex_adrreg_d_latched, idc_adiw, idc_andi, idc_cpi, idc_ldi, idc_ori, idc_sbci, idc_sbiw, idc_subi
1870 
 
1871 
  reg_rd_adr_cml_out <= '1'&dex_adrreg_d_cml_1(3 downto 0) when (idc_subi_cml_1 or idc_sbci_cml_1 or idc_andi_cml_1 or idc_ori_cml_1 or idc_cpi_cml_1 or idc_ldi_cml_1)='1' else
1872 
                           "00000" when lpm_st2_cml_1='1' else
1873 
               adiw_sbiw_encoder_out_cml_1     when (idc_adiw_cml_1 or idc_sbiw_cml_1)='1' else
1874 
               adiw_sbiw_encoder_mux_out_cml_1 when (adiw_st_cml_1 or sbiw_st_cml_1)='1' else
1875 
                           dex_adrreg_d_latched_cml_1      when (((st_st_cml_1 or sts_st_cml_1) and not reg_file_adr_space_cml_1) or ld_st_cml_1 or lds_st_cml_1 or pop_st_cml_1)='1' else
1876 
               ramadr_int_cml_1(4 downto 0)    when ((st_st_cml_1 or sts_st_cml_1) and reg_file_adr_space_cml_1)='1'else --!!??
1877 
                           dex_adrreg_d_cml_1;
1878 
 
1879 
  reg_rd_adr_int <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else
1880 
                           "00000" when lpm_st2='1' else
1881 
               adiw_sbiw_encoder_out     when (idc_adiw or idc_sbiw)='1' else
1882 
               adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else
1883 
                           dex_adrreg_d_latched      when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else
1884 
               ramadr_int(4 downto 0)    when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
1885 
                           dex_adrreg_d;
1886 
 
1887 
reg_rr_adr <= ramadr_int(4 downto 0) when ((ld_st or lds_st) and reg_file_adr_space)='1'else --!!??
1888 
                  dex_adrreg_d_latched   when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
1889 
                  dex_adrreg_r;
1890 
 
1891 
-- SynEDA CoreMultiplier
1892 
-- assignment(s): reg_rd_in
1893 
-- replace(s): dbusin, reg_rr_out, reg_z_out, reg_file_adr_space, lpm_st2, sts_st, lds_st, st_st, ld_st, pop_st, instruction_reg, dex_dat8_immed, gp_reg_tmp, idc_bld, idc_in, idc_ldi, idc_mov
1894 
 
1895 
-- MULTIPLEXER FOR REGISTER FILE Rd INPUT
1896 
reg_rd_in_cml_out <= dbusin_cml_2 when (idc_in_cml_2 or ((lds_st_cml_2 or ld_st_cml_2)and not reg_file_adr_space_cml_2) or pop_st_cml_2)='1' else -- FROM INPUT DATA BUS
1897 
                         reg_rr_out_cml_2 when ((lds_st_cml_2 or ld_st_cml_2)  and reg_file_adr_space_cml_2)='1' else
1898 
             gp_reg_tmp_cml_2 when ((st_st_cml_2 or sts_st_cml_2)  and reg_file_adr_space_cml_2)='1' else -- ST/STD/STS &  ADDRESS FROM 0 TO 31 (REGISTER FILE)
1899 
                         bld_op_out when (idc_bld_cml_2='1')else                                     -- FROM BIT PROCESSOR BLD COMMAND
1900 
             reg_rr_out_cml_2 when (idc_mov_cml_2='1')else                                     -- FOR MOV INSTRUCTION
1901 
                         instruction_reg_cml_2(15 downto 8) when (lpm_st2_cml_2='1' and reg_z_out_cml_2(0)='1') else -- LPM/ELPM
1902 
                         instruction_reg_cml_2(7 downto 0) when  (lpm_st2_cml_2='1' and reg_z_out_cml_2(0)='0') else -- LPM/ELPM
1903 
             dex_dat8_immed_cml_2 when idc_ldi_cml_2='1' else
1904 
                         alu_data_out;                                               -- FROM ALU DATA OUT
1905 
 
1906 
-- SynEDA CoreMultiplier
1907 
-- assignment(s): iowe_int
1908 
-- replace(s): io_file_adr_space, sts_st, st_st, sbi_st, cbi_st, idc_out
1909 
 
1910 
-- SynEDA CoreMultiplier
1911 
-- assignment(s): iore_int
1912 
-- replace(s): io_file_adr_space, lds_st, ld_st
1913 
 
1914 
-- IORE/IOWE LOGIC (6 BIT ADDRESS adr[5..0] FOR I/O PORTS(64 LOCATIONS))
1915 
iore_int <= idc_in or idc_sbi or idc_cbi or idc_sbic or idc_sbis or ((ld_st_cml_1 or lds_st_cml_1) and io_file_adr_space_cml_1);   -- IN/SBI/CBI
1916 
iowe_int <= '1' when ((idc_out_cml_2 or sbi_st_cml_2 or cbi_st_cml_2) or
1917 
                     ((st_st_cml_2 or sts_st_cml_2) and io_file_adr_space_cml_2))='1' else '0'; -- OUT/SBI/CBI + !! ST/STS/STD
1918 
 
1919 
 
1920 
-- SynEDA CoreMultiplier
1921 
-- assignment(s): adr_int
1922 
-- replace(s): sbi_st, cbi_st, ramadr_int, cbi_sbi_io_adr_tmp, idc_out
1923 
 
1924 
-- adr[5..0] BUS MULTIPLEXER
1925 
adr_int <= dex_adr6port when (idc_in or idc_out_cml_1) = '1' else                          -- IN/OUT INSTRUCTIONS
1926 
           '0'&dex_adr5port when (idc_cbi or idc_sbi or idc_sbic or idc_sbis) ='1'    else  -- CBI/SBI (READ PHASE) + SBIS/SBIC
1927 
                   '0'&cbi_sbi_io_adr_tmp_cml_1 when (cbi_st_cml_1 or sbi_st_cml_1)='1' else     -- CBI/SBI (WRITE PHASE)
1928 
                    ramadr_int_cml_1(6)&ramadr_int_cml_1(4 downto 0);                                                   -- LD/LDS/LDD/ST/STS/STD
1929 
 
1930 
-- ramre LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS))
1931 
--ramre_int <= not(reg_file_adr_space or io_file_adr_space) and
1932 
--            (ld_st or lds_st2 or pop_st or                    -- LD/LDD/LDS/POP/
1933 
--             ret_st1 or ret_st2 or reti_st1 or reti_st2);     -- RET/RETI
1934 
 
1935 
-- SynEDA CoreMultiplier
1936 
-- assignment(s): ramre_int
1937 
-- replace(s): cpuwait, ramadr_reg_in, ret_st2, reti_st2, lds_st, ld_st, pop_st, ramre_int, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_ret, idc_reti
1938 
 
1939 
DataMemoryRead:process(cp2,ireset)
1940 
begin
1941 
if ireset='0' then -- Reset
1942 
 ramre_int <= '0';
1943 
elsif (cp2='1' and cp2'event) then ramre_int <= ramre_int_cml_3; -- Clock
1944 
 if (cp2en='1') then                                                      -- Clock enable
1945 
  case ramre_int_cml_3 is
1946 
   when '0' =>
1947 
    if(ramadr_reg_in_cml_3(15 downto 5)/=const_ram_to_io_a and
1948 
           ramadr_reg_in_cml_3(15 downto 5)/=const_ram_to_io_b and
1949 
       ramadr_reg_in_cml_3(15 downto 5)/=const_ram_to_reg  and
1950 
      (idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ldd_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_z_cml_3 or  -- LD/LDD instruction
1951 
           idc_lds_cml_3 or                                                     -- LDS instruction(two cycle execution)
1952 
           idc_pop_cml_3 or                                                     -- POP instruction
1953 
       idc_ret_cml_3 or                                                         -- RET instruction
1954 
           idc_reti_cml_3)='1')                                                                                                     -- RETI instruction
1955 
           then ramre_int <='1';
1956 
    end if;
1957 
   when '1' =>
1958 
    if ((ld_st_cml_3 or lds_st_cml_3 or pop_st_cml_3 or ret_st2_cml_3 or reti_st2_cml_3)and not cpuwait_cml_3)='1' then
1959 
     ramre_int <='0';
1960 
    end if;
1961 
   when others  =>      null;
1962 
  end case;
1963 
 end if;
1964 
end if;
1965 
end process;
1966 
 
1967 
-- ramwe LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS))
1968 
--ramwe_int <= not(reg_file_adr_space or io_file_adr_space) and
1969 
--            (st_st or sts_st2 or push_st or rcall_st1 or rcall_st2 or -- ST/STD/STS/PUSH/RCALL
1970 
--                                                      icall_st1 or icall_st2 or -- ICALL
1971 
--                                                      call_st2 or call_st3 or   -- CALL
1972 
--                                                                                      irq_st2 or irq_st3);      -- INTERRUPT
1973 
 
1974 
-- SynEDA CoreMultiplier
1975 
-- assignment(s): ramwe_int
1976 
-- replace(s): cpuwait, ramadr_reg_in, irq_st1, irq_st3, call_st1, call_st3, rcall_st2, icall_st2, sts_st, st_st, push_st, ramwe_int, idc_icall, idc_push, idc_rcall, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1977 
 
1978 
DataMemoryWrite:process(cp2,ireset)
1979 
begin
1980 
if ireset='0' then -- Reset
1981 
 ramwe_int <= '0';
1982 
elsif (cp2='1' and cp2'event) then ramwe_int <= ramwe_int_cml_3; -- Clock
1983 
 if (cp2en='1') then                                                      -- Clock enable
1984 
  case ramwe_int_cml_3 is
1985 
   when '0' =>
1986 
    if(ramadr_reg_in_cml_3(15 downto 5)/=const_ram_to_io_a and
1987 
           ramadr_reg_in_cml_3(15 downto 5)/=const_ram_to_io_b and
1988 
       ramadr_reg_in_cml_3(15 downto 5)/=const_ram_to_reg  and
1989 
      (idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3 or  -- ST/STD instruction
1990 
           idc_sts_cml_3 or                                                     -- STS instruction (two cycle execution)
1991 
           idc_push_cml_3 or                                                    -- PUSH instruction
1992 
           idc_rcall_cml_3 or                                                                                                     -- RCALL instruction
1993 
           idc_icall_cml_3 or                                                                                                     -- ICALL instruction
1994 
           call_st1_cml_3 or                                                    -- CALL instruction
1995 
           irq_st1_cml_3)='1')                                                  -- Interrupt
1996 
          then ramwe_int <='1';
1997 
    end if;
1998 
   when '1' =>
1999 
    if ((st_st_cml_3 or sts_st_cml_3 or push_st_cml_3 or rcall_st2_cml_3 or
2000 
             icall_st2_cml_3 or call_st3_cml_3 or irq_st3_cml_3)and not cpuwait_cml_3)='1' then ramwe_int <='0';
2001 
    end if;
2002 
   when others  =>      null;
2003 
  end case;
2004 
end if;
2005 
end if;
2006 
end process;
2007 
 
2008 
-- DBUSOUT MULTIPLEXER
2009 
--dbusout_mux_logic: for i in dbusout_int'range generate
2010 
--dbusout_int(i)<= (reg_rd_out(i) and (idc_push or idc_sts or
2011 
--                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2012 
--                               (gp_reg_tmp(i) and (st_st or sts_st))or                            -- NEW
2013 
--                               (bitpr_io_out(i) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
2014 
--                 (program_counter(i)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC                 (program_counter_high_fr(i) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
2015 
--                 (pc_for_interrupt(i) and irq_st1) or
2016 
--                               (pc_for_interrupt(8) and irq_st2) or
2017 
--                               (reg_rd_out(i) and  idc_out); -- OUT
2018 
--end generate;
2019 
 
2020 
dbusout_int(0)<= (reg_rd_out_cml_2(0) and (idc_push_cml_2 or idc_sts_cml_2 or
2021 
                 (idc_st_x_cml_2 or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2022 
                                 (gp_reg_tmp_cml_2(0) and (st_st_cml_2 or sts_st_cml_2))or                            -- NEW
2023 
                                 (bitpr_io_out_cml_2(0) and (cbi_st_cml_2 or sbi_st_cml_2))or                          -- CBI/SBI  INSTRUCTIONS
2024 
                 (program_counter_cml_2(0)         and (idc_rcall_cml_2 or idc_icall_cml_2 or call_st1_cml_2))or                        -- LOW  PART OF PC
2025 
                 (program_counter_high_fr_cml_2(0) and (rcall_st1_cml_2 or icall_st1_cml_2 or call_st2_cml_2))or                        -- HIGH PART OF PC
2026 
                 (pc_for_interrupt_cml_2(0) and irq_st1_cml_2) or
2027 
                                 (pc_for_interrupt_cml_2(8) and irq_st2_cml_2) or
2028 
                                 (reg_rd_out_cml_2(0) and  idc_out_cml_2); -- OUT
2029 
 
2030 
dbusout_int(1)<= (reg_rd_out_cml_2(1) and (idc_push_cml_2 or idc_sts_cml_2 or
2031 
                 (idc_st_x_cml_2 or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2032 
                                 (gp_reg_tmp_cml_2(1) and (st_st_cml_2 or sts_st_cml_2))or                            -- NEW
2033 
                                 (bitpr_io_out_cml_2(1) and (cbi_st_cml_2 or sbi_st_cml_2))or                          -- CBI/SBI  INSTRUCTIONS
2034 
                 (program_counter_cml_2(1)         and (idc_rcall_cml_2 or idc_icall_cml_2 or call_st1_cml_2))or                        -- LOW  PART OF PC
2035 
                 (program_counter_high_fr_cml_2(1) and (rcall_st1_cml_2 or icall_st1_cml_2 or call_st2_cml_2))or                        -- HIGH PART OF PC
2036 
                 (pc_for_interrupt_cml_2(1) and irq_st1_cml_2) or
2037 
                                 (pc_for_interrupt_cml_2(9) and irq_st2_cml_2) or
2038 
                                 (reg_rd_out_cml_2(1) and  idc_out_cml_2); -- OUT
2039 
 
2040 
dbusout_int(2)<= (reg_rd_out_cml_2(2) and (idc_push_cml_2 or idc_sts_cml_2 or
2041 
                 (idc_st_x_cml_2 or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2042 
                                 (gp_reg_tmp_cml_2(2) and (st_st_cml_2 or sts_st_cml_2))or                            -- NEW
2043 
                                 (bitpr_io_out_cml_2(2) and (cbi_st_cml_2 or sbi_st_cml_2))or                          -- CBI/SBI  INSTRUCTIONS
2044 
                 (program_counter_cml_2(2)         and (idc_rcall_cml_2 or idc_icall_cml_2 or call_st1_cml_2))or                        -- LOW  PART OF PC
2045 
                 (program_counter_high_fr_cml_2(2) and (rcall_st1_cml_2 or icall_st1_cml_2 or call_st2_cml_2))or                        -- HIGH PART OF PC
2046 
                 (pc_for_interrupt_cml_2(2) and irq_st1_cml_2) or
2047 
                                 (pc_for_interrupt_cml_2(10) and irq_st2_cml_2) or
2048 
                                 (reg_rd_out_cml_2(2) and  idc_out_cml_2); -- OUT
2049 
 
2050 
dbusout_int(3)<= (reg_rd_out_cml_2(3) and (idc_push_cml_2 or idc_sts_cml_2 or
2051 
                 (idc_st_x_cml_2 or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2052 
                                 (gp_reg_tmp_cml_2(3) and (st_st_cml_2 or sts_st_cml_2))or                            -- NEW
2053 
                                 (bitpr_io_out_cml_2(3) and (cbi_st_cml_2 or sbi_st_cml_2))or                          -- CBI/SBI  INSTRUCTIONS
2054 
                 (program_counter_cml_2(3)         and (idc_rcall_cml_2 or idc_icall_cml_2 or call_st1_cml_2))or                        -- LOW  PART OF PC
2055 
                 (program_counter_high_fr_cml_2(3) and (rcall_st1_cml_2 or icall_st1_cml_2 or call_st2_cml_2))or                        -- HIGH PART OF PC
2056 
                 (pc_for_interrupt_cml_2(3) and irq_st1_cml_2) or
2057 
                                 (pc_for_interrupt_cml_2(11) and irq_st2_cml_2) or
2058 
                                 (reg_rd_out_cml_2(3) and  idc_out_cml_2); -- OUT
2059 
 
2060 
dbusout_int(4)<= (reg_rd_out_cml_2(4) and (idc_push_cml_2 or idc_sts_cml_2 or
2061 
                 (idc_st_x_cml_2 or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2062 
                                 (gp_reg_tmp_cml_2(4) and (st_st_cml_2 or sts_st_cml_2))or                            -- NEW
2063 
                                 (bitpr_io_out_cml_2(4) and (cbi_st_cml_2 or sbi_st_cml_2))or                          -- CBI/SBI  INSTRUCTIONS
2064 
                 (program_counter_cml_2(4)         and (idc_rcall_cml_2 or idc_icall_cml_2 or call_st1_cml_2))or                        -- LOW  PART OF PC
2065 
                 (program_counter_high_fr_cml_2(4) and (rcall_st1_cml_2 or icall_st1_cml_2 or call_st2_cml_2))or                        -- HIGH PART OF PC
2066 
                 (pc_for_interrupt_cml_2(4) and irq_st1_cml_2) or
2067 
                                 (pc_for_interrupt_cml_2(12) and irq_st2_cml_2) or
2068 
                                 (reg_rd_out_cml_2(4) and  idc_out_cml_2); -- OUT
2069 
 
2070 
dbusout_int(5)<= (reg_rd_out_cml_2(5) and (idc_push_cml_2 or idc_sts_cml_2 or
2071 
                 (idc_st_x_cml_2 or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2072 
                                 (gp_reg_tmp_cml_2(5) and (st_st_cml_2 or sts_st_cml_2))or                            -- NEW
2073 
                                 (bitpr_io_out_cml_2(5) and (cbi_st_cml_2 or sbi_st_cml_2))or                          -- CBI/SBI  INSTRUCTIONS
2074 
                 (program_counter_cml_2(5)         and (idc_rcall_cml_2 or idc_icall_cml_2 or call_st1_cml_2))or                        -- LOW  PART OF PC
2075 
                 (program_counter_high_fr_cml_2(5) and (rcall_st1_cml_2 or icall_st1_cml_2 or call_st2_cml_2))or                        -- HIGH PART OF PC
2076 
                 (pc_for_interrupt_cml_2(5) and irq_st1_cml_2) or
2077 
                                 (pc_for_interrupt_cml_2(13) and irq_st2_cml_2) or
2078 
                                 (reg_rd_out_cml_2(5) and  idc_out_cml_2); -- OUT
2079 
 
2080 
dbusout_int(6)<= (reg_rd_out_cml_2(6) and (idc_push_cml_2 or idc_sts_cml_2 or
2081 
                 (idc_st_x_cml_2 or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2082 
                                 (gp_reg_tmp_cml_2(6) and (st_st_cml_2 or sts_st_cml_2))or                            -- NEW
2083 
                                 (bitpr_io_out_cml_2(6) and (cbi_st_cml_2 or sbi_st_cml_2))or                          -- CBI/SBI  INSTRUCTIONS
2084 
                 (program_counter_cml_2(6)         and (idc_rcall_cml_2 or idc_icall_cml_2 or call_st1_cml_2))or                        -- LOW  PART OF PC
2085 
                 (program_counter_high_fr_cml_2(6) and (rcall_st1_cml_2 or icall_st1_cml_2 or call_st2_cml_2))or                        -- HIGH PART OF PC
2086 
                 (pc_for_interrupt_cml_2(6) and irq_st1_cml_2) or
2087 
                                 (pc_for_interrupt_cml_2(14) and irq_st2_cml_2) or
2088 
                                 (reg_rd_out_cml_2(6) and  idc_out_cml_2); -- OUT
2089 
 
2090 
-- SynEDA CoreMultiplier
2091 
-- assignment(s): dbusout_int
2092 
-- replace(s): reg_rd_out, bitpr_io_out, program_counter, program_counter_high_fr, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, sts_st, st_st, sbi_st, cbi_st, pc_for_interrupt, gp_reg_tmp, idc_icall, idc_out, idc_push, idc_rcall, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
2093 
 
2094 
dbusout_int(7)<= (reg_rd_out_cml_2(7) and (idc_push_cml_2 or idc_sts_cml_2 or
2095 
                 (idc_st_x_cml_2 or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2096 
                                 (gp_reg_tmp_cml_2(7) and (st_st_cml_2 or sts_st_cml_2))or                            -- NEW
2097 
                                 (bitpr_io_out_cml_2(7) and (cbi_st_cml_2 or sbi_st_cml_2))or                          -- CBI/SBI  INSTRUCTIONS
2098 
                 (program_counter_cml_2(7)         and (idc_rcall_cml_2 or idc_icall_cml_2 or call_st1_cml_2))or                        -- LOW  PART OF PC
2099 
                 (program_counter_high_fr_cml_2(7) and (rcall_st1_cml_2 or icall_st1_cml_2 or call_st2_cml_2))or                        -- HIGH PART OF PC
2100 
                 (pc_for_interrupt_cml_2(7) and irq_st1_cml_2) or
2101 
                                 (pc_for_interrupt_cml_2(15) and irq_st2_cml_2) or
2102 
                                 (reg_rd_out_cml_2(7) and  idc_out_cml_2); -- OUT
2103 
 
2104 
-- SynEDA CoreMultiplier
2105 
-- assignment(s): dbusout_int_route
2106 
-- replace(s): dbusout_int
2107 
 
2108 
dbusout_int_route_cml_out <= dbusout_int_cml_3;
2109 
 
2110 
dbusout(0)<= (reg_rd_out_int(0) and (idc_push or idc_sts or
2111 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2112 
                                 (gp_reg_tmp(0) and (st_st or sts_st))or                            -- NEW
2113 
                                 (bitpr_io_out(0) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
2114 
                 (program_counter(0)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
2115 
                 (program_counter_high_fr(0) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
2116 
                 (pc_for_interrupt(0) and irq_st1) or
2117 
                                 (pc_for_interrupt(8) and irq_st2) or
2118 
                                 (reg_rd_out_int(0) and  idc_out); -- OUT
2119 
 
2120 
dbusout(1)<= (reg_rd_out_int(1) and (idc_push or idc_sts or
2121 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2122 
                                 (gp_reg_tmp(1) and (st_st or sts_st))or                            -- NEW
2123 
                                 (bitpr_io_out(1) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
2124 
                 (program_counter(1)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
2125 
                 (program_counter_high_fr(1) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
2126 
                 (pc_for_interrupt(1) and irq_st1) or
2127 
                                 (pc_for_interrupt(9) and irq_st2) or
2128 
                                 (reg_rd_out_int(1) and  idc_out); -- OUT
2129 
 
2130 
dbusout(2)<= (reg_rd_out_int(2) and (idc_push or idc_sts or
2131 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2132 
                                 (gp_reg_tmp(2) and (st_st or sts_st))or                            -- NEW
2133 
                                 (bitpr_io_out(2) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
2134 
                 (program_counter(2)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
2135 
                 (program_counter_high_fr(2) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
2136 
                 (pc_for_interrupt(2) and irq_st1) or
2137 
                                 (pc_for_interrupt(10) and irq_st2) or
2138 
                                 (reg_rd_out_int(2) and  idc_out); -- OUT
2139 
 
2140 
dbusout(3)<= (reg_rd_out_int(3) and (idc_push or idc_sts or
2141 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2142 
                                 (gp_reg_tmp(3) and (st_st or sts_st))or                            -- NEW
2143 
                                 (bitpr_io_out(3) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
2144 
                 (program_counter(3)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
2145 
                 (program_counter_high_fr(3) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
2146 
                 (pc_for_interrupt(3) and irq_st1) or
2147 
                                 (pc_for_interrupt(11) and irq_st2) or
2148 
                                 (reg_rd_out_int(3) and  idc_out); -- OUT
2149 
 
2150 
dbusout(4)<= (reg_rd_out_int(4) and (idc_push or idc_sts or
2151 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2152 
                                 (gp_reg_tmp(4) and (st_st or sts_st))or                            -- NEW
2153 
                                 (bitpr_io_out(4) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
2154 
                 (program_counter(4)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
2155 
                 (program_counter_high_fr(4) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
2156 
                 (pc_for_interrupt(4) and irq_st1) or
2157 
                                 (pc_for_interrupt(12) and irq_st2) or
2158 
                                 (reg_rd_out_int(4) and  idc_out); -- OUT
2159 
 
2160 
dbusout(5)<= (reg_rd_out_int(5) and (idc_push or idc_sts or
2161 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2162 
                                 (gp_reg_tmp(5) and (st_st or sts_st))or                            -- NEW
2163 
                                 (bitpr_io_out(5) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
2164 
                 (program_counter(5)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
2165 
                 (program_counter_high_fr(5) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
2166 
                 (pc_for_interrupt(5) and irq_st1) or
2167 
                                 (pc_for_interrupt(13) and irq_st2) or
2168 
                                 (reg_rd_out_int(5) and  idc_out); -- OUT
2169 
 
2170 
dbusout(6)<= (reg_rd_out_int(6) and (idc_push or idc_sts or
2171 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2172 
                                 (gp_reg_tmp(6) and (st_st or sts_st))or                            -- NEW
2173 
                                 (bitpr_io_out(6) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
2174 
                 (program_counter(6)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
2175 
                 (program_counter_high_fr(6) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
2176 
                 (pc_for_interrupt(6) and irq_st1) or
2177 
                                 (pc_for_interrupt(14) and irq_st2) or
2178 
                                 (reg_rd_out_int(6) and  idc_out); -- OUT
2179 
 
2180 
dbusout(7)<= (reg_rd_out_int(7) and (idc_push or idc_sts or
2181 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
2182 
                                 (gp_reg_tmp(7) and (st_st or sts_st))or                            -- NEW
2183 
                                 (bitpr_io_out(7) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
2184 
                 (program_counter(7)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
2185 
                 (program_counter_high_fr(7) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
2186 
                 (pc_for_interrupt(7) and irq_st1) or
2187 
                                 (pc_for_interrupt(15) and irq_st2) or
2188 
                                 (reg_rd_out_int(7) and  idc_out); -- OUT
2189 
 
2190 
 
2191 
-- ALU CONNECTION
2192 
 
2193 
-- ALU Rr INPUT MUX
2194 
alu_data_r_in <= dex_dat8_immed       when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi)='1' else
2195 
                 "00"&dex_dat6_immed  when (idc_adiw or idc_sbiw) ='1' else
2196 
                 "00000000"           when (adiw_st or sbiw_st) ='1' else
2197 
                 reg_rr_out;
2198 
 
2199 
 
2200 
-- SynEDA CoreMultiplier
2201 
-- assignment(s): gp_reg_tmp
2202 
-- replace(s): reg_rd_out, gp_reg_tmp, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
2203 
 
2204 
-- gp_reg_tmp STORES TEMPREOARY THE VALUE OF SOURCE REGISTER DURING ST/STD/STS INSTRUCTION
2205 
gp_registers_trig:process(cp2,ireset)
2206 
begin
2207 
if (ireset='0') then
2208 
gp_reg_tmp <= (others=>'0');
2209 
elsif (cp2='1' and cp2'event) then gp_reg_tmp <= gp_reg_tmp_cml_3;
2210 
 if (cp2en='1') then                                                      -- Clock enable
2211 
  -- if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or sts_st1)='1' then  -- CLOCK ENABLE
2212 
  if ((idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3) or idc_sts_cml_3)='1' then  -- CLOCK ENABLE
2213 
     gp_reg_tmp <= reg_rd_out_cml_3;
2214 
  end if;
2215 
 end if;
2216 
end if;
2217 
end process;
2218 
 
2219 
-- **********************************************************************************************************
2220 
 
2221 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2222 
-- +++++++++++++++++++++++++++++++++++++++ PROGRAM COUNTER ++++++++++++++++++++++++++++++++++++++++++++++++++
2223 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2224 
 
2225 
-- SynEDA CoreMultiplier
2226 
-- assignment(s): program_counter_high_fr
2227 
-- replace(s): program_counter, program_counter_high_fr, irq_st1, call_st1, idc_icall, idc_rcall
2228 
 
2229 
program_counter_high_store:process(cp2,ireset)
2230 
begin
2231 
if ireset='0' then                         -- RESET
2232 
program_counter_high_fr <=(others => '0');
2233 
elsif (cp2='1' and cp2'event) then program_counter_high_fr <= program_counter_high_fr_cml_3;       -- CLOCK
2234 
 if (cp2en='1') then                                                      -- Clock enable
2235 
  if (idc_rcall_cml_3 or idc_icall_cml_3 or call_st1_cml_3 or irq_st1_cml_3) ='1' then
2236 
   program_counter_high_fr <= program_counter_cml_3(15 downto 8);       -- STORE HIGH BYTE OF THE PROGRAMM COUNTER FOR RCALL/ICALL/CALL INSTRUCTIONS AND INTERRUPTS
2237 
  end if;
2238 
 end if;
2239 
end if;
2240 
end process;
2241 
 
2242 
 
2243 
-- SynEDA CoreMultiplier
2244 
-- assignment(s): program_counter_tmp
2245 
-- replace(s): program_counter_tmp, program_counter, idc_lpm
2246 
 
2247 
program_counter_for_lpm_elpm:process(cp2,ireset)
2248 
begin
2249 
if ireset='0' then                         -- RESET
2250 
program_counter_tmp<=(others => '0');
2251 
elsif (cp2='1' and cp2'event) then program_counter_tmp <= program_counter_tmp_cml_3;       -- CLOCK
2252 
 if (cp2en='1') then                                                      -- Clock enable
2253 
  if (idc_lpm_cml_3 or idc_elpm) ='1' then
2254 
   program_counter_tmp <= program_counter_cml_3;
2255 
  end if;
2256 
 end if;
2257 
end if;
2258 
end process;
2259 
 
2260 
-- SynEDA CoreMultiplier
2261 
-- assignment(s): pa15_pm
2262 
-- replace(s): rampz_out
2263 
 
2264 
pa15_pm <= rampz_out_cml_3(0) and idc_elpm; -- '0' WHEN LPM INSTRUCTIONS  RAMPZ(0) WHEN ELPM INSTRUCTION
2265 
 
2266 
-- OFFSET FOR BRBC/BRBS INSTRUCTIONS +63/-64
2267 
offset_brbx <= "0000000000"&dex_brxx_offset(5 downto 0) when (dex_brxx_offset(6)='0') else -- +
2268 
               "1111111111"&dex_brxx_offset(5 downto 0);                                   -- -
2269 
 
2270 
-- OFFSET FOR RJMP/RCALL INSTRUCTIONS +2047/-2048
2271 
offset_rxx <= "00000"&dex_adr12mem_s(10 downto 0) when (dex_adr12mem_s(11)='0') else       -- +
2272 
              "11111"&dex_adr12mem_s(10 downto 0);                                          -- -
2273 
 
2274 
program_counter <= pc_high&pc_low;
2275 
 
2276 
-- SynEDA CoreMultiplier
2277 
-- assignment(s): program_counter_in
2278 
-- replace(s): dbusin, reg_z_out, bit_test_op_out, irqackad_int, program_counter_tmp, program_counter, irq_st1, call_st1, jmp_st1, ret_st1, ret_st2, reti_st1, reti_st2, lpm_st1, instruction_reg, idc_brbc, idc_brbs, idc_icall, idc_ijmp, idc_lpm, idc_rcall, idc_rjmp
2279 
 
2280 
program_counter_in <= program_counter_cml_3 + offset_brbx when ((idc_brbc_cml_3 or idc_brbs_cml_3) and  bit_test_op_out_cml_3) ='1'else  -- BRBC/BRBS
2281 
                      program_counter_cml_3 + offset_rxx when (idc_rjmp_cml_3 or idc_rcall_cml_3)='1'else     -- RJMP/RCALL
2282 
                      reg_z_out_cml_3 when (idc_ijmp_cml_3 or idc_icall_cml_3)='1'else                        -- IJMP/ICALL
2283 
                      pa15_pm&reg_z_out_cml_3(15 downto 1) when (idc_lpm_cml_3 or idc_elpm) ='1'else    -- LPM/ELPM
2284 
                      instruction_reg_cml_3  when (jmp_st1_cml_3 or call_st1_cml_3)='1'else                    -- JMP/CALL
2285 
                      "0000000000"&irqackad_int_cml_3&'0' when irq_st1_cml_3 ='1' else                 -- INTERRUPT
2286 
                      dbusin_cml_3&"00000000"  when (ret_st1_cml_3 or reti_st1_cml_3)='1' else                 -- RET/RETI -> PC HIGH BYTE
2287 
                      "00000000"&dbusin_cml_3  when (ret_st2_cml_3 or reti_st2_cml_3)='1' else                 -- RET/RETI -> PC LOW BYTE
2288 
                      program_counter_tmp_cml_3 when (lpm_st1_cml_3)='1'                                 -- AFTER LPM/ELPM INSTRUCTION
2289 
                      else program_counter_cml_3+1;      -- THE MOST USUAL CASE
2290 
 
2291 
 
2292 
 
2293 
-- SynEDA CoreMultiplier
2294 
-- assignment(s): pc_low_en
2295 
-- replace(s): cpuwait, irq_st2, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, sts_st, lds_st, idc_adiw, idc_cbi, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_pop, idc_push, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
2296 
 
2297 
pc_low_en  <= not (idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_y_cml_3 or idc_ldd_z_cml_3 or
2298 
                       idc_st_x_cml_3 or idc_st_y_cml_3 or idc_st_z_cml_3 or idc_std_y_cml_3 or idc_std_z_cml_3 or
2299 
                                   ((sts_st_cml_3 or lds_st_cml_3) and cpuwait_cml_3)or
2300 
                                   idc_adiw_cml_3 or idc_sbiw_cml_3 or
2301 
                                   idc_push_cml_3 or idc_pop_cml_3 or
2302 
                                   idc_cbi_cml_3 or idc_sbi_cml_3 or
2303 
                                   rcall_st1_cml_3 or icall_st1_cml_3 or call_st2_cml_3 or irq_st2_cml_3 or cpuwait_cml_3 or
2304 
                                   ret_st1_cml_3 or reti_st1_cml_3);
2305 
 
2306 
 
2307 
-- SynEDA CoreMultiplier
2308 
-- assignment(s): pc_high_en
2309 
-- replace(s): cpuwait, irq_st2, call_st2, rcall_st1, icall_st1, ret_st2, reti_st2, sts_st, lds_st, idc_adiw, idc_cbi, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_pop, idc_push, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
2310 
 
2311 
pc_high_en <= not (idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_y_cml_3 or idc_ldd_z_cml_3 or
2312 
                       idc_st_x_cml_3 or idc_st_y_cml_3 or idc_st_z_cml_3 or idc_std_y_cml_3 or idc_std_z_cml_3 or
2313 
                                   ((sts_st_cml_3 or lds_st_cml_3) and cpuwait_cml_3) or
2314 
                                   idc_adiw_cml_3 or idc_sbiw_cml_3 or
2315 
                                   idc_push_cml_3 or idc_pop_cml_3 or
2316 
                                   idc_cbi_cml_3 or idc_sbi_cml_3 or
2317 
                                   rcall_st1_cml_3 or icall_st1_cml_3 or call_st2_cml_3 or irq_st2_cml_3 or cpuwait_cml_3 or
2318 
                                   ret_st2_cml_3 or reti_st2_cml_3);
2319 
 
2320 
-- SynEDA CoreMultiplier
2321 
-- assignment(s): pc_low
2322 
-- replace(s): pc_low
2323 
 
2324 
program_counter_low:process(cp2,ireset)
2325 
begin
2326 
if ireset='0' then                              -- RESET
2327 
pc_low<=(others => '0');
2328 
elsif (cp2='1' and cp2'event) then pc_low <= pc_low_cml_3;              -- CLOCK
2329 
 if (cp2en='1') then                                                    -- Clock enable
2330 
  if pc_low_en ='1' then
2331 
   pc_low <= program_counter_in(7 downto 0);
2332 
  end if;
2333 
 end if;
2334 
end if;
2335 
end process;
2336 
 
2337 
-- SynEDA CoreMultiplier
2338 
-- assignment(s): pc_high
2339 
-- replace(s): pc_high
2340 
 
2341 
program_counter_high:process(cp2,ireset)
2342 
begin
2343 
if ireset='0' then                               -- RESET
2344 
pc_high<=(others => '0');
2345 
elsif (cp2='1' and cp2'event) then pc_high <= pc_high_cml_3;               -- CLOCK
2346 
 if (cp2en='1') then                                                     -- Clock enable
2347 
  if pc_high_en ='1' then
2348 
   pc_high <= program_counter_in(15 downto 8);
2349 
  end if;
2350 
 end if;
2351 
end if;
2352 
end process;
2353 
 
2354 
pc <= program_counter;
2355 
 
2356 
 
2357 
-- SynEDA CoreMultiplier
2358 
-- assignment(s): pc_for_interrupt
2359 
-- replace(s): program_counter, pc_for_interrupt
2360 
 
2361 
program_counter_for_interrupt:process(cp2,ireset)
2362 
begin
2363 
if ireset='0' then                                 -- RESET
2364 
pc_for_interrupt <=(others => '0');
2365 
elsif (cp2='1' and cp2'event) then pc_for_interrupt <= pc_for_interrupt_cml_3;               -- CLOCK
2366 
 if (cp2en='1') then                                                     -- Clock enable
2367 
  if irq_start ='1' then
2368 
   pc_for_interrupt <= program_counter_cml_3;
2369 
  end if;
2370 
 end if;
2371 
end if;
2372 
end process;
2373 
 
2374 
-- END OF PROGRAM COUNTER
2375 
 
2376 
-- STATE MACHINES
2377 
 
2378 
-- SynEDA CoreMultiplier
2379 
-- assignment(s): skip_inst_start
2380 
-- replace(s): alu_z_flag_out, bit_test_op_out, idc_cpse, idc_sbic, idc_sbis, idc_sbrc, idc_sbrs
2381 
 
2382 
skip_inst_start <= ((idc_sbrc_cml_3 or idc_sbrs_cml_3 or idc_sbic_cml_3 or idc_sbis_cml_3) and bit_test_op_out_cml_3)or
2383 
                   (idc_cpse_cml_3 and alu_z_flag_out_cml_3);
2384 
 
2385 
-- SynEDA CoreMultiplier
2386 
-- assignment(s): nskip_inst_st0, skip_inst_st1, skip_inst_st2
2387 
-- replace(s): two_word_inst, nskip_inst_st0, skip_inst_st1, skip_inst_st2
2388 
 
2389 
skip_instruction_sm:process(cp2,ireset)
2390 
begin
2391 
if ireset='0' then                       -- RESET
2392 
nskip_inst_st0 <= '0';
2393 
skip_inst_st1  <= '0';
2394 
skip_inst_st2  <= '0';
2395 
elsif (cp2='1' and cp2'event) then skip_inst_st2 <= skip_inst_st2_cml_3; skip_inst_st1 <= skip_inst_st1_cml_3; nskip_inst_st0 <= nskip_inst_st0_cml_3;       -- CLOCK
2396 
 if (cp2en='1') then                                 -- Clock enable
2397 
  nskip_inst_st0 <= (not nskip_inst_st0_cml_3 and skip_inst_start) or
2398 
                    (nskip_inst_st0_cml_3 and not((skip_inst_st1_cml_3 and not two_word_inst_cml_3) or skip_inst_st2_cml_3));
2399 
  skip_inst_st1  <= (not skip_inst_st1_cml_3 and not nskip_inst_st0_cml_3 and skip_inst_start);
2400 
  skip_inst_st2  <=  not skip_inst_st2_cml_3 and skip_inst_st1_cml_3 and two_word_inst_cml_3;
2401 
 end if;
2402 
end if;
2403 
end process;
2404 
 
2405 
 
2406 
 
2407 
-- SynEDA CoreMultiplier
2408 
-- assignment(s): adiw_st, sbiw_st
2409 
-- replace(s): adiw_st, idc_adiw, sbiw_st, idc_sbiw
2410 
 
2411 
alu_state_machines:process(cp2,ireset)
2412 
begin
2413 
if ireset='0' then                       -- RESET
2414 
adiw_st <= '0';
2415 
sbiw_st <= '0';
2416 
elsif (cp2='1' and cp2'event) then sbiw_st <= sbiw_st_cml_3; adiw_st <= adiw_st_cml_3;       -- CLOCK
2417 
 if (cp2en='1') then                                     -- Clock enable
2418 
  adiw_st <= not adiw_st_cml_3 and idc_adiw_cml_3;
2419 
  sbiw_st <= not sbiw_st_cml_3 and idc_sbiw_cml_3;
2420 
 end if;
2421 
end if;
2422 
end process;
2423 
 
2424 
 
2425 
-- SynEDA CoreMultiplier
2426 
-- assignment(s): nlpm_st0, lpm_st1, lpm_st2
2427 
-- replace(s): nlpm_st0, lpm_st2, idc_lpm, lpm_st1
2428 
 
2429 
lpm_state_machine:process(cp2,ireset)
2430 
begin
2431 
if ireset='0' then                       -- RESET
2432 
nlpm_st0 <= '0';
2433 
lpm_st1 <= '0';
2434 
lpm_st2 <= '0';
2435 
elsif (cp2='1' and cp2'event) then lpm_st2 <= lpm_st2_cml_3; lpm_st1 <= lpm_st1_cml_3; nlpm_st0 <= nlpm_st0_cml_3;       -- CLOCK
2436 
 if (cp2en='1') then                                                      -- Clock enable
2437 
  nlpm_st0 <= (not nlpm_st0_cml_3 and (idc_lpm_cml_3 or idc_elpm)) or (nlpm_st0_cml_3 and not lpm_st2_cml_3);
2438 
  lpm_st1  <= (not lpm_st1_cml_3 and not nlpm_st0_cml_3 and (idc_lpm_cml_3 or idc_elpm)); -- ??
2439 
  lpm_st2  <=  not lpm_st2_cml_3 and lpm_st1_cml_3;
2440 
 end if;
2441 
end if;
2442 
end process;
2443 
 
2444 
 
2445 
-- SynEDA CoreMultiplier
2446 
-- assignment(s): lds_st
2447 
-- replace(s): cpuwait, lds_st, idc_lds
2448 
 
2449 
lds_state_machine:process(cp2,ireset)
2450 
begin
2451 
if ireset='0' then                       -- RESET
2452 
 lds_st <= '0';
2453 
elsif (cp2='1' and cp2'event) then lds_st <= lds_st_cml_3;       -- CLOCK
2454 
 if (cp2en='1') then                                                      -- Clock enable
2455 
  lds_st  <= (not lds_st_cml_3 and idc_lds_cml_3) or (lds_st_cml_3 and cpuwait_cml_3);
2456 
 end if;
2457 
end if;
2458 
end process;
2459 
 
2460 
 
2461 
-- SynEDA CoreMultiplier
2462 
-- assignment(s): sts_st
2463 
-- replace(s): cpuwait, sts_st, idc_sts
2464 
 
2465 
sts_state_machine:process(cp2,ireset)
2466 
begin
2467 
if ireset='0' then                       -- RESET
2468 
 sts_st <= '0';
2469 
elsif (cp2='1' and cp2'event) then sts_st <= sts_st_cml_3;       -- CLOCK
2470 
 if (cp2en='1') then                                                      -- Clock enable
2471 
  sts_st  <= (not sts_st_cml_3 and idc_sts_cml_3) or (sts_st_cml_3 and cpuwait_cml_3);
2472 
 end if;
2473 
end if;
2474 
end process;
2475 
 
2476 
-- SynEDA CoreMultiplier
2477 
-- assignment(s): njmp_st0, jmp_st1, jmp_st2
2478 
-- replace(s): njmp_st0, jmp_st2, idc_jmp, jmp_st1
2479 
 
2480 
jmp_state_machine:process(cp2,ireset)
2481 
begin
2482 
if ireset='0' then                       -- RESET
2483 
njmp_st0 <= '0';
2484 
jmp_st1 <= '0';
2485 
jmp_st2 <= '0';
2486 
elsif (cp2='1' and cp2'event) then jmp_st2 <= jmp_st2_cml_3; jmp_st1 <= jmp_st1_cml_3; njmp_st0 <= njmp_st0_cml_3;       -- CLOCK
2487 
 if (cp2en='1') then                                                      -- Clock enable
2488 
  njmp_st0 <= (not njmp_st0_cml_3 and idc_jmp_cml_3) or (njmp_st0_cml_3 and not jmp_st2_cml_3);
2489 
  jmp_st1  <= not jmp_st1_cml_3 and not njmp_st0_cml_3 and idc_jmp_cml_3; -- ??
2490 
  jmp_st2  <= not jmp_st2_cml_3 and jmp_st1_cml_3;
2491 
 end if;
2492 
end if;
2493 
end process;
2494 
 
2495 
-- SynEDA CoreMultiplier
2496 
-- assignment(s): nrcall_st0, rcall_st1, rcall_st2
2497 
-- replace(s): cpuwait, nrcall_st0, rcall_st2, idc_rcall, rcall_st1
2498 
 
2499 
rcall_state_machine:process(cp2,ireset)
2500 
begin
2501 
if ireset='0' then                       -- RESET
2502 
nrcall_st0 <= '0';
2503 
rcall_st1 <= '0';
2504 
rcall_st2 <= '0';
2505 
elsif (cp2='1' and cp2'event) then rcall_st2 <= rcall_st2_cml_3; rcall_st1 <= rcall_st1_cml_3; nrcall_st0 <= nrcall_st0_cml_3;       -- CLOCK
2506 
 if (cp2en='1') then                                                      -- Clock enable
2507 
  nrcall_st0 <= (not nrcall_st0_cml_3 and idc_rcall_cml_3) or (nrcall_st0_cml_3 and not (rcall_st2_cml_3 and not cpuwait_cml_3));
2508 
  rcall_st1  <= (not rcall_st1_cml_3 and not nrcall_st0_cml_3 and idc_rcall_cml_3) or (rcall_st1_cml_3 and cpuwait_cml_3);
2509 
  rcall_st2  <= (not rcall_st2_cml_3 and rcall_st1_cml_3 and not cpuwait_cml_3) or (rcall_st2_cml_3 and cpuwait_cml_3);
2510 
 end if;
2511 
end if;
2512 
end process;
2513 
 
2514 
-- SynEDA CoreMultiplier
2515 
-- assignment(s): nicall_st0, icall_st1, icall_st2
2516 
-- replace(s): cpuwait, nicall_st0, icall_st2, idc_icall, icall_st1
2517 
 
2518 
icall_state_machine:process(cp2,ireset)
2519 
begin
2520 
if ireset='0' then                       -- RESET
2521 
nicall_st0 <= '0';
2522 
icall_st1 <= '0';
2523 
icall_st2 <= '0';
2524 
elsif (cp2='1' and cp2'event) then icall_st2 <= icall_st2_cml_3; icall_st1 <= icall_st1_cml_3; nicall_st0 <= nicall_st0_cml_3;       -- CLOCK
2525 
 if (cp2en='1') then                                                      -- Clock enable
2526 
  nicall_st0 <= (not nicall_st0_cml_3 and idc_icall_cml_3) or (nicall_st0_cml_3 and not (icall_st2_cml_3 and not cpuwait_cml_3));
2527 
  icall_st1  <= (not icall_st1_cml_3 and not nicall_st0_cml_3 and idc_icall_cml_3) or (icall_st1_cml_3 and cpuwait_cml_3);
2528 
  icall_st2  <= (not icall_st2_cml_3 and icall_st1_cml_3 and not cpuwait_cml_3) or (icall_st2_cml_3 and cpuwait_cml_3);
2529 
 end if;
2530 
end if;
2531 
end process;
2532 
 
2533 
-- SynEDA CoreMultiplier
2534 
-- assignment(s): ncall_st0, call_st1, call_st2, call_st3
2535 
-- replace(s): cpuwait, ncall_st0, call_st3, idc_call, call_st1, call_st2
2536 
 
2537 
call_state_machine:process(cp2,ireset)
2538 
begin
2539 
if ireset='0' then                       -- RESET
2540 
ncall_st0 <= '0';
2541 
call_st1 <= '0';
2542 
call_st2 <= '0';
2543 
call_st3  <= '0';
2544 
elsif (cp2='1' and cp2'event) then call_st3 <= call_st3_cml_3; call_st2 <= call_st2_cml_3; call_st1 <= call_st1_cml_3; ncall_st0 <= ncall_st0_cml_3;       -- CLOCK
2545 
 if (cp2en='1') then                                                      -- Clock enable
2546 
  ncall_st0 <= (not ncall_st0_cml_3 and idc_call_cml_3) or (ncall_st0_cml_3 and not( call_st3_cml_3 and not cpuwait_cml_3));
2547 
  call_st1  <= not call_st1_cml_3 and not ncall_st0_cml_3 and idc_call_cml_3;
2548 
  call_st2  <= (not call_st2_cml_3 and call_st1_cml_3) or (call_st2_cml_3 and cpuwait_cml_3);
2549 
  call_st3  <= (not call_st3_cml_3 and call_st2_cml_3 and not cpuwait_cml_3) or (call_st3_cml_3 and cpuwait_cml_3);
2550 
 end if;
2551 
end if;
2552 
end process;
2553 
 
2554 
-- SynEDA CoreMultiplier
2555 
-- assignment(s): nret_st0, ret_st1, ret_st2, ret_st3
2556 
-- replace(s): nret_st0, ret_st3, idc_ret, cpuwait, ret_st1, ret_st2
2557 
 
2558 
ret_state_machine:process(cp2,ireset)
2559 
begin
2560 
if ireset='0' then                       -- RESET
2561 
nret_st0 <= '0';
2562 
ret_st1 <= '0';
2563 
ret_st2 <= '0';
2564 
ret_st3  <= '0';
2565 
elsif (cp2='1' and cp2'event) then ret_st3 <= ret_st3_cml_3; ret_st2 <= ret_st2_cml_3; ret_st1 <= ret_st1_cml_3; nret_st0 <= nret_st0_cml_3;       -- CLOCK
2566 
 if (cp2en='1') then                                                      -- Clock enable
2567 
  nret_st0 <= (not nret_st0_cml_3 and idc_ret_cml_3) or (nret_st0_cml_3 and not ret_st3_cml_3);
2568 
  ret_st1  <= (not ret_st1_cml_3 and not nret_st0_cml_3 and idc_ret_cml_3) or (ret_st1_cml_3 and cpuwait_cml_3);
2569 
  ret_st2  <= (not ret_st2_cml_3 and ret_st1_cml_3 and not cpuwait_cml_3) or (ret_st2_cml_3 and cpuwait_cml_3) ;
2570 
  ret_st3  <= not ret_st3_cml_3 and ret_st2_cml_3 and not cpuwait_cml_3;
2571 
 end if;
2572 
end if;
2573 
end process;
2574 
 
2575 
-- SynEDA CoreMultiplier
2576 
-- assignment(s): nreti_st0, reti_st1, reti_st2, reti_st3
2577 
-- replace(s): nreti_st0, reti_st3, idc_reti, cpuwait, reti_st1, reti_st2
2578 
 
2579 
reti_state_machine:process(cp2,ireset)
2580 
begin
2581 
if ireset='0' then                       -- RESET
2582 
nreti_st0 <= '0';
2583 
reti_st1 <= '0';
2584 
reti_st2 <= '0';
2585 
reti_st3  <= '0';
2586 
elsif (cp2='1' and cp2'event) then reti_st3 <= reti_st3_cml_3; reti_st2 <= reti_st2_cml_3; reti_st1 <= reti_st1_cml_3; nreti_st0 <= nreti_st0_cml_3;       -- CLOCK
2587 
 if (cp2en='1') then                                                      -- Clock enable
2588 
  nreti_st0 <= (not nreti_st0_cml_3 and idc_reti_cml_3) or (nreti_st0_cml_3 and not reti_st3_cml_3);
2589 
  reti_st1  <= (not reti_st1_cml_3 and not nreti_st0_cml_3 and idc_reti_cml_3) or (reti_st1_cml_3 and cpuwait_cml_3);
2590 
  reti_st2  <= (not reti_st2_cml_3 and reti_st1_cml_3 and not cpuwait_cml_3) or (reti_st2_cml_3 and cpuwait_cml_3) ;
2591 
  reti_st3  <= not reti_st3_cml_3 and reti_st2_cml_3 and not cpuwait_cml_3;
2592 
 end if;
2593 
end if;
2594 
end process;
2595 
 
2596 
 
2597 
-- INTERRUPT LOGIC AND STATE MACHINE
2598 
 
2599 
-- SynEDA CoreMultiplier
2600 
-- assignment(s): irq_int
2601 
-- replace(s): irqlines
2602 
 
2603 
irq_int <= '0' when      irqlines_cml_2="00000000000000000000000" else '1';
2604 
 
2605 
irq_vector_adr(15 downto 6)<=(others => '0');
2606 
irq_vector_adr(0) <= '0';
2607 
-- PRIORITY ENCODER
2608 
irq_vector_adr(5 downto 1) <= "00001" when irqlines(0)='1'  else -- 0x0002
2609 
                              "00010" when irqlines(1)='1'  else -- 0x0004
2610 
                              "00011" when irqlines(2)='1'  else -- 0x0006
2611 
                              "00100" when irqlines(3)='1'  else -- 0x0008
2612 
                              "00101" when irqlines(4)='1'  else -- 0x000A
2613 
                              "00110" when irqlines(5)='1'  else -- 0x000C
2614 
                              "00111" when irqlines(6)='1'  else -- 0x000E
2615 
                              "01000" when irqlines(7)='1'  else -- 0x0010
2616 
                              "01001" when irqlines(8)='1'  else -- 0x0012
2617 
                              "01010" when irqlines(9)='1'  else -- 0x0014
2618 
                              "01011" when irqlines(10)='1' else -- 0x0016
2619 
                              "01100" when irqlines(11)='1' else -- 0x0018
2620 
                              "01101" when irqlines(12)='1' else -- 0x001A
2621 
                              "01110" when irqlines(13)='1' else -- 0x001C
2622 
                              "01111" when irqlines(14)='1' else -- 0x001E
2623 
                              "10000" when irqlines(15)='1' else -- 0x0020
2624 
                              "10001" when irqlines(16)='1' else -- 0x0022
2625 
                              "10010" when irqlines(17)='1' else -- 0x0024
2626 
                              "10011" when irqlines(18)='1' else -- 0x0026
2627 
                              "10100" when irqlines(19)='1' else -- 0x0028
2628 
                              "10101" when irqlines(20)='1' else -- 0x002A
2629 
                              "10110" when irqlines(21)='1' else -- 0x002C
2630 
                              "10111" when irqlines(22)='1' else -- 0x002E
2631 
                                                          "00000";
2632 
 
2633 
-- SynEDA CoreMultiplier
2634 
-- assignment(s): cpu_busy
2635 
-- replace(s): cpuwait, bit_test_op_out, two_word_inst, nirq_st0, call_st1, call_st2, call_st3, rcall_st1, rcall_st2, icall_st1, icall_st2, jmp_st1, ret_st1, ret_st2, reti_st1, reti_st2, skip_inst_st1, lpm_st1, sts_st, lds_st, st_st, ld_st, push_st, pop_st, iowe_int, dbusout_int, idc_adiw, idc_bclr, idc_brbc, idc_brbs, idc_call, idc_cbi, idc_icall, idc_ijmp, idc_jmp, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_lpm, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_rjmp, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts, sreg_bop_wr_en, sreg_adr_eq
2636 
 
2637 
-- MULTI CYCLE INSTRUCTION FLAG FOR IRQ
2638 
cpu_busy <= idc_adiw_cml_3 or idc_sbiw_cml_3 or idc_cbi_cml_3 or idc_sbi_cml_3 or
2639 
            idc_rjmp_cml_3 or idc_ijmp_cml_3 or
2640 
                        idc_jmp_cml_3 or jmp_st1_cml_3 or
2641 
--                      idc_brbs or idc_brbc or -- Old variant
2642 
            ((idc_brbc_cml_3 or idc_brbs_cml_3) and  bit_test_op_out_cml_3) or
2643 
                        idc_lpm_cml_3 or lpm_st1_cml_3 or
2644 
                        skip_inst_start or (skip_inst_st1_cml_3 and two_word_inst_cml_3) or
2645 
                        idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ldd_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_z_cml_3 or (ld_st_cml_3 and cpuwait_cml_3) or
2646 
                        idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3 or (st_st_cml_3 and cpuwait_cml_3) or
2647 
                        idc_lds_cml_3 or (lds_st_cml_3 and cpuwait_cml_3) or
2648 
                        idc_sts_cml_3 or (sts_st_cml_3 and cpuwait_cml_3) or
2649 
                        idc_rcall_cml_3 or rcall_st1_cml_3 or (rcall_st2_cml_3 and cpuwait_cml_3) or           -- RCALL
2650 
                        idc_icall_cml_3 or icall_st1_cml_3 or (icall_st2_cml_3 and cpuwait_cml_3) or               -- ICALL
2651 
                        idc_call_cml_3 or call_st1_cml_3 or call_st2_cml_3 or (call_st3_cml_3 and cpuwait_cml_3) or  -- CALL
2652 
                        idc_push_cml_3 or (push_st_cml_3 and cpuwait_cml_3) or                           -- PUSH (added 14.07.05)
2653 
                        idc_pop_cml_3 or (pop_st_cml_3 and cpuwait_cml_3) or                             -- POP  (added 14.07.05)
2654 
                    (idc_bclr_cml_3 and sreg_bop_wr_en_cml_3(7)) or                 -- ??? CLI
2655 
                    (iowe_int_cml_3 and sreg_adr_eq_cml_3 and not dbusout_int_cml_3(7))or -- ??? Writing '0' to I flag (OUT/STD/ST/STD)
2656 
                        nirq_st0_cml_3 or
2657 
--                      idc_ret  or nret_st0 or                             -- Old variant
2658 
                        idc_ret_cml_3 or ret_st1_cml_3 or ret_st2_cml_3 or
2659 
--                      idc_reti or nreti_st0;                              -- At least one instruction must be executed after RETI and before the new interrupt.
2660 
                        idc_reti_cml_3 or reti_st1_cml_3 or reti_st2_cml_3;
2661 
 
2662 
-- SynEDA CoreMultiplier
2663 
-- assignment(s): sreg_adr_eq
2664 
-- replace(s): adr_int
2665 
 
2666 
sreg_adr_eq <= '1' when adr_int_cml_2=SREG_Address else '0';
2667 
 
2668 
-- SynEDA CoreMultiplier
2669 
-- assignment(s): irq_start
2670 
-- replace(s): irq_int
2671 
 
2672 
--irq_start <= irq_int and not cpu_busy and globint;
2673 
irq_start <= irq_int_cml_3 and not cpu_busy and globint;
2674 
 
2675 
-- SynEDA CoreMultiplier
2676 
-- assignment(s): nirq_st0, irq_st1, irq_st2, irq_st3
2677 
-- replace(s): cpuwait, nirq_st0, irq_st3, irq_st1, irq_st2
2678 
 
2679 
irq_state_machine:process(cp2,ireset)
2680 
begin
2681 
if ireset='0' then                       -- RESET
2682 
nirq_st0 <= '0';
2683 
irq_st1 <= '0';
2684 
irq_st2 <= '0';
2685 
irq_st3 <= '0';
2686 
elsif (cp2='1' and cp2'event) then irq_st3 <= irq_st3_cml_3; irq_st2 <= irq_st2_cml_3; irq_st1 <= irq_st1_cml_3; nirq_st0 <= nirq_st0_cml_3;       -- CLOCK
2687 
 if (cp2en='1') then                                                      -- Clock enable
2688 
  nirq_st0 <= (not nirq_st0_cml_3 and irq_start) or (nirq_st0_cml_3 and not (irq_st3_cml_3 and not cpuwait_cml_3));
2689 
  irq_st1  <= (not irq_st1_cml_3 and not nirq_st0_cml_3 and irq_start);
2690 
  irq_st2  <= (not irq_st2_cml_3 and irq_st1_cml_3) or (irq_st2_cml_3 and cpuwait_cml_3);
2691 
  irq_st3  <= (not irq_st3_cml_3 and irq_st2_cml_3 and not cpuwait_cml_3) or (irq_st3_cml_3 and cpuwait_cml_3);
2692 
 end if;
2693 
end if;
2694 
end process;
2695 
 
2696 
-- SynEDA CoreMultiplier
2697 
-- assignment(s): irqack_int
2698 
-- replace(s): irqack_int
2699 
 
2700 
irqack_reg:process(cp2,ireset)
2701 
begin
2702 
if ireset='0' then                       -- RESET
2703 
irqack_int<='0';
2704 
elsif (cp2='1' and cp2'event) then irqack_int <= irqack_int_cml_3;       -- CLOCK
2705 
 if (cp2en='1') then                                                      -- Clock enable
2706 
  irqack_int<= not irqack_int_cml_3 and irq_start;
2707 
 end if;
2708 
end if;
2709 
end process;
2710 
-- SynEDA CoreMultiplier
2711 
-- assignment(s): irqack
2712 
-- replace(s): irqack_int
2713 
 
2714 
irqack_cml_out <= irqack_int_cml_3;
2715 
 
2716 
-- SynEDA CoreMultiplier
2717 
-- assignment(s): irqackad_int
2718 
-- replace(s): irqackad_int, irq_vector_adr
2719 
 
2720 
irqackad_reg:process(cp2,ireset)
2721 
begin
2722 
if ireset='0' then                                -- RESET
2723 
irqackad_int<=(others=>'0');
2724 
elsif (cp2='1' and cp2'event) then irqackad_int <= irqackad_int_cml_3;              -- CLOCK
2725 
 if (cp2en='1') then                                                      -- Clock enable
2726 
  irqackad_int <= irq_vector_adr_cml_3(5 downto 1);
2727 
 end if;
2728 
end if;
2729 
end process;
2730 
-- SynEDA CoreMultiplier
2731 
-- assignment(s): irqackad
2732 
-- replace(s): irqackad_int
2733 
 
2734 
irqackad_cml_out <= irqackad_int_cml_3;
2735 
 
2736 
-- *******************************************************************************************
2737 
 
2738 
-- SynEDA CoreMultiplier
2739 
-- assignment(s): ijmp_st, rjmp_st, brxx_st, push_st, pop_st
2740 
-- replace(s): ijmp_st, idc_ijmp, rjmp_st, idc_rjmp, bit_test_op_out, brxx_st, idc_brbc, idc_brbs, cpuwait, push_st, idc_push, pop_st, idc_pop
2741 
 
2742 
rjmp_push_pop_ijmp_state_brxx_machine:process(cp2,ireset)
2743 
begin
2744 
if ireset='0' then                       -- RESET
2745 
rjmp_st <= '0';
2746 
ijmp_st <= '0';
2747 
push_st <= '0';
2748 
pop_st <= '0';
2749 
brxx_st <= '0';
2750 
elsif (cp2='1' and cp2'event) then pop_st <= pop_st_cml_3; push_st <= push_st_cml_3; brxx_st <= brxx_st_cml_3; rjmp_st <= rjmp_st_cml_3; ijmp_st <= ijmp_st_cml_3;       -- CLOCK
2751 
 if (cp2en='1') then                                                      -- Clock enable
2752 
  rjmp_st <= idc_rjmp_cml_3;    -- ??
2753 
  ijmp_st <= idc_ijmp_cml_3;
2754 
  push_st <= (not push_st_cml_3 and idc_push_cml_3) or (push_st_cml_3 and cpuwait_cml_3);
2755 
  pop_st  <= (not pop_st_cml_3  and idc_pop_cml_3) or (pop_st_cml_3 and cpuwait_cml_3);
2756 
  brxx_st <= not brxx_st_cml_3 and (idc_brbc_cml_3 or idc_brbs_cml_3) and bit_test_op_out_cml_3;
2757 
 end if;
2758 
end if;
2759 
end process;
2760 
 
2761 
-- SynEDA CoreMultiplier
2762 
-- assignment(s): st_st, ld_st
2763 
-- replace(s): cpuwait, st_st, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, ld_st, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z
2764 
 
2765 
-- LD/LDD/ST/STD
2766 
ld_st_state_machine:process(cp2,ireset)
2767 
begin
2768 
if ireset='0' then                       -- RESET
2769 
ld_st <= '0';
2770 
st_st <= '0';
2771 
elsif (cp2='1' and cp2'event) then ld_st <= ld_st_cml_3; st_st <= st_st_cml_3;       -- CLOCK
2772 
 if (cp2en='1') then                                                      -- Clock enable
2773 
  ld_st <= (not ld_st_cml_3 and (idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ldd_y_cml_3 or idc_ld_z_cml_3 or idc_ldd_z_cml_3)) or (ld_st_cml_3 and cpuwait_cml_3);
2774 
  st_st <= (not st_st_cml_3 and (idc_st_x_cml_3 or idc_st_y_cml_3 or idc_std_y_cml_3 or idc_st_z_cml_3 or idc_std_z_cml_3)) or (st_st_cml_3 and cpuwait_cml_3);
2775 
 end if;
2776 
end if;
2777 
end process;
2778 
 
2779 
-- SynEDA CoreMultiplier
2780 
-- assignment(s): sbi_st, cbi_st, cbi_sbi_io_adr_tmp, cbi_sbi_bit_num_tmp
2781 
-- replace(s): sbi_st, idc_sbi, cbi_st, idc_cbi, dex_adr5port, cbi_sbi_io_adr_tmp, dex_bitop_bitnum, cbi_sbi_bit_num_tmp
2782 
 
2783 
-- SBI/CBI
2784 
sbi_cbi_machine:process(cp2,ireset)
2785 
begin
2786 
if ireset='0' then                       -- RESET
2787 
sbi_st <= '0';
2788 
cbi_st <= '0';
2789 
cbi_sbi_io_adr_tmp  <= (others => '0');
2790 
cbi_sbi_bit_num_tmp     <= (others => '0');
2791 
elsif (cp2='1' and cp2'event) then cbi_sbi_bit_num_tmp <= cbi_sbi_bit_num_tmp_cml_3; cbi_sbi_io_adr_tmp <= cbi_sbi_io_adr_tmp_cml_3; cbi_st <= cbi_st_cml_3; sbi_st <= sbi_st_cml_3;       -- CLOCK
2792 
 if (cp2en='1') then                                                      -- Clock enable
2793 
  sbi_st <= not sbi_st_cml_3 and idc_sbi_cml_3;
2794 
  cbi_st <= not cbi_st_cml_3 and idc_cbi_cml_3;
2795 
  cbi_sbi_io_adr_tmp <= dex_adr5port_cml_3;
2796 
  cbi_sbi_bit_num_tmp <= dex_bitop_bitnum_cml_3;
2797 
 end if;
2798 
end if;
2799 
end process;
2800 
 
2801 
-- ########################################################################################
2802 
 
2803 
-- SREG FLAGS WRITE ENABLE LOGIC
2804 
 
2805 
--bclr_bset_op_en_logic:for i in sreg_bop_wr_en'range generate
2806 
--sreg_bop_wr_en(i) <= '1' when (dex_bitnum_sreg=i and (idc_bclr or idc_bset)='1') else '0';
2807 
--end generate;
2808 
 
2809 
sreg_bop_wr_en(0) <= '1' when (dex_bitnum_sreg=0 and (idc_bclr or idc_bset)='1') else '0';
2810 
sreg_bop_wr_en(1) <= '1' when (dex_bitnum_sreg=1 and (idc_bclr or idc_bset)='1') else '0';
2811 
sreg_bop_wr_en(2) <= '1' when (dex_bitnum_sreg=2 and (idc_bclr or idc_bset)='1') else '0';
2812 
sreg_bop_wr_en(3) <= '1' when (dex_bitnum_sreg=3 and (idc_bclr or idc_bset)='1') else '0';
2813 
sreg_bop_wr_en(4) <= '1' when (dex_bitnum_sreg=4 and (idc_bclr or idc_bset)='1') else '0';
2814 
sreg_bop_wr_en(5) <= '1' when (dex_bitnum_sreg=5 and (idc_bclr or idc_bset)='1') else '0';
2815 
sreg_bop_wr_en(6) <= '1' when (dex_bitnum_sreg=6 and (idc_bclr or idc_bset)='1') else '0';
2816 
sreg_bop_wr_en(7) <= '1' when (dex_bitnum_sreg=7 and (idc_bclr or idc_bset)='1') else '0';
2817 
 
2818 
-- SynEDA CoreMultiplier
2819 
-- assignment(s): sreg_c_wr_en
2820 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_adiw, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_lsr, idc_neg, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi, sreg_bop_wr_en
2821 
 
2822 
sreg_c_wr_en <= idc_add_cml_3 or idc_adc_cml_3 or (idc_adiw_cml_3 or adiw_st_cml_3) or idc_sub_cml_3  or idc_subi_cml_3 or
2823 
                idc_sbc_cml_3 or idc_sbci_cml_3 or (idc_sbiw_cml_3 or sbiw_st_cml_3) or idc_com_cml_3 or idc_neg_cml_3 or
2824 
                                idc_cp_cml_3 or idc_cpc_cml_3 or idc_cpi_cml_3 or
2825 
                idc_lsr_cml_3 or idc_ror_cml_3 or idc_asr_cml_3 or sreg_bop_wr_en_cml_3(0);
2826 
 
2827 
-- SynEDA CoreMultiplier
2828 
-- assignment(s): sreg_z_wr_en
2829 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_adiw, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi, sreg_bop_wr_en
2830 
 
2831 
sreg_z_wr_en <= idc_add_cml_3 or idc_adc_cml_3 or (idc_adiw_cml_3 or adiw_st_cml_3) or idc_sub_cml_3  or idc_subi_cml_3 or
2832 
                idc_sbc_cml_3 or idc_sbci_cml_3 or (idc_sbiw_cml_3 or sbiw_st_cml_3) or
2833 
                                idc_cp_cml_3 or idc_cpc_cml_3 or idc_cpi_cml_3 or
2834 
                idc_and_cml_3 or idc_andi_cml_3 or idc_or_cml_3 or idc_ori_cml_3 or idc_eor_cml_3 or idc_com_cml_3 or idc_neg_cml_3 or
2835 
                idc_inc_cml_3 or idc_dec_cml_3 or idc_lsr_cml_3 or idc_ror_cml_3 or idc_asr_cml_3 or sreg_bop_wr_en_cml_3(1);
2836 
 
2837 
 
2838 
-- SynEDA CoreMultiplier
2839 
-- assignment(s): sreg_n_wr_en
2840 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi, sreg_bop_wr_en
2841 
 
2842 
sreg_n_wr_en <= idc_add_cml_3 or idc_adc_cml_3 or adiw_st_cml_3 or idc_sub_cml_3  or idc_subi_cml_3 or
2843 
                idc_sbc_cml_3 or idc_sbci_cml_3 or sbiw_st_cml_3 or
2844 
                                idc_cp_cml_3 or idc_cpc_cml_3 or idc_cpi_cml_3 or
2845 
                idc_and_cml_3 or idc_andi_cml_3 or idc_or_cml_3 or idc_ori_cml_3 or idc_eor_cml_3 or idc_com_cml_3 or idc_neg_cml_3 or
2846 
                idc_inc_cml_3 or idc_dec_cml_3 or idc_lsr_cml_3 or idc_ror_cml_3 or idc_asr_cml_3 or sreg_bop_wr_en_cml_3(2);
2847 
 
2848 
-- SynEDA CoreMultiplier
2849 
-- assignment(s): sreg_v_wr_en
2850 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi, sreg_bop_wr_en
2851 
 
2852 
sreg_v_wr_en <= idc_add_cml_3 or idc_adc_cml_3 or adiw_st_cml_3 or idc_sub_cml_3  or idc_subi_cml_3 or -- idc_adiw
2853 
                idc_sbc_cml_3 or idc_sbci_cml_3 or sbiw_st_cml_3 or idc_neg_cml_3 or idc_com_cml_3 or  -- idc_sbiw
2854 
                idc_inc_cml_3 or idc_dec_cml_3 or
2855 
                                idc_cp_cml_3 or idc_cpc_cml_3 or idc_cpi_cml_3 or
2856 
                idc_lsr_cml_3 or idc_ror_cml_3 or idc_asr_cml_3 or sreg_bop_wr_en_cml_3(3) or
2857 
                                idc_and_cml_3 or idc_andi_cml_3 or idc_or_cml_3 or idc_ori_cml_3 or idc_eor_cml_3; -- V-flag bug fixing
2858 
 
2859 
-- SynEDA CoreMultiplier
2860 
-- assignment(s): sreg_s_wr_en
2861 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi, sreg_bop_wr_en
2862 
 
2863 
sreg_s_wr_en <= idc_add_cml_3 or idc_adc_cml_3 or adiw_st_cml_3 or idc_sub_cml_3 or idc_subi_cml_3 or
2864 
                idc_sbc_cml_3 or idc_sbci_cml_3 or sbiw_st_cml_3 or
2865 
                                idc_cp_cml_3 or idc_cpc_cml_3 or idc_cpi_cml_3 or
2866 
                                idc_and_cml_3 or idc_andi_cml_3 or idc_or_cml_3 or idc_ori_cml_3 or idc_eor_cml_3 or idc_com_cml_3 or idc_neg_cml_3 or
2867 
                                idc_inc_cml_3 or idc_dec_cml_3 or idc_lsr_cml_3 or idc_ror_cml_3 or idc_asr_cml_3 or sreg_bop_wr_en_cml_3(4);
2868 
 
2869 
-- SynEDA CoreMultiplier
2870 
-- assignment(s): sreg_h_wr_en
2871 
-- replace(s): idc_adc, idc_add, idc_cp, idc_cpc, idc_cpi, idc_neg, idc_sbc, idc_sbci, idc_sub, idc_subi, sreg_bop_wr_en
2872 
 
2873 
sreg_h_wr_en <= idc_add_cml_3 or idc_adc_cml_3 or idc_sub_cml_3  or idc_subi_cml_3 or
2874 
                                idc_cp_cml_3 or idc_cpc_cml_3 or idc_cpi_cml_3 or
2875 
                idc_sbc_cml_3 or idc_sbci_cml_3 or idc_neg_cml_3 or sreg_bop_wr_en_cml_3(5);
2876 
 
2877 
-- SynEDA CoreMultiplier
2878 
-- assignment(s): sreg_t_wr_en
2879 
-- replace(s): idc_bst, sreg_bop_wr_en
2880 
 
2881 
sreg_t_wr_en <=  idc_bst_cml_3 or sreg_bop_wr_en_cml_3(6);
2882 
 
2883 
-- SynEDA CoreMultiplier
2884 
-- assignment(s): sreg_i_wr_en
2885 
-- replace(s): irq_st1, reti_st3, sreg_bop_wr_en
2886 
 
2887 
sreg_i_wr_en <= irq_st1_cml_3 or reti_st3_cml_3 or sreg_bop_wr_en_cml_3(7); -- WAS "irq_start"
2888 
 
2889 
-- SynEDA CoreMultiplier
2890 
-- assignment(s): sreg_fl_in
2891 
-- replace(s): alu_z_flag_out, reti_st3, idc_bclr, idc_bset, idc_bst
2892 
 
2893 
sreg_fl_in_cml_out <=  bit_pr_sreg_out when (idc_bst_cml_3 or idc_bclr_cml_3 or idc_bset_cml_3)='1' else                           -- TO THE SREG
2894 
reti_st3_cml_3&'0'&alu_h_flag_out&alu_s_flag_out&alu_v_flag_out&alu_n_flag_out&alu_z_flag_out_cml_3&alu_c_flag_out;
2895 
 
2896 
-- #################################################################################################################
2897 
 
2898 
-- *********************************************************************************************
2899 
-- ************** INSTRUCTION DECODER OUTPUTS FOR THE OTHER BLOCKS  ****************************
2900 
-- *********************************************************************************************
2901 
 
2902 
-- FOR ALU
2903 
 
2904 
idc_add_out   <= idc_add;
2905 
idc_adc_out   <= idc_adc;
2906 
-- SynEDA CoreMultiplier
2907 
-- assignment(s): idc_adiw_out
2908 
-- replace(s): idc_adiw
2909 
 
2910 
idc_adiw_out_cml_out  <= idc_adiw_cml_1;
2911 
idc_sub_out   <= idc_sub;
2912 
idc_subi_out  <= idc_subi;
2913 
idc_sbc_out   <= idc_sbc;
2914 
idc_sbci_out  <= idc_sbci;
2915 
idc_sbiw_out  <= idc_sbiw;
2916 
adiw_st_out   <= adiw_st;
2917 
sbiw_st_out   <= sbiw_st;
2918 
idc_and_out   <= idc_and;
2919 
-- SynEDA CoreMultiplier
2920 
-- assignment(s): idc_andi_out
2921 
-- replace(s): idc_andi
2922 
 
2923 
idc_andi_out_cml_out  <= idc_andi_cml_1;
2924 
idc_or_out    <= idc_or;
2925 
-- SynEDA CoreMultiplier
2926 
-- assignment(s): idc_ori_out
2927 
-- replace(s): idc_ori
2928 
 
2929 
idc_ori_out_cml_out   <= idc_ori_cml_1;
2930 
idc_eor_out   <= idc_eor;
2931 
idc_com_out   <= idc_com;
2932 
idc_neg_out   <= idc_neg;
2933 
idc_inc_out   <= idc_inc;
2934 
idc_dec_out   <= idc_dec;
2935 
idc_cp_out    <= idc_cp;
2936 
idc_cpc_out   <= idc_cpc;
2937 
idc_cpi_out   <= idc_cpi;
2938 
idc_cpse_out  <= idc_cpse;
2939 
idc_lsr_out   <= idc_lsr;
2940 
idc_ror_out   <= idc_ror;
2941 
idc_asr_out   <= idc_asr;
2942 
idc_swap_out  <= idc_swap;
2943 
 
2944 
-- FOR THE BIT PROCESSOR
2945 
sbi_st_out   <= sbi_st;
2946 
cbi_st_out   <= cbi_st;
2947 
-- SynEDA CoreMultiplier
2948 
-- assignment(s): idc_bst_out
2949 
-- replace(s): idc_bst
2950 
 
2951 
idc_bst_out_cml_out  <= idc_bst_cml_3;
2952 
-- SynEDA CoreMultiplier
2953 
-- assignment(s): idc_bset_out
2954 
-- replace(s): idc_bset
2955 
 
2956 
idc_bset_out_cml_out <= idc_bset_cml_3;
2957 
-- SynEDA CoreMultiplier
2958 
-- assignment(s): idc_bclr_out
2959 
-- replace(s): idc_bclr
2960 
 
2961 
idc_bclr_out_cml_out <= idc_bclr_cml_3;
2962 
-- SynEDA CoreMultiplier
2963 
-- assignment(s): idc_sbic_out
2964 
-- replace(s): idc_sbic
2965 
 
2966 
idc_sbic_out_cml_out <= idc_sbic_cml_2;
2967 
-- SynEDA CoreMultiplier
2968 
-- assignment(s): idc_sbis_out
2969 
-- replace(s): idc_sbis
2970 
 
2971 
idc_sbis_out_cml_out <= idc_sbis_cml_2;
2972 
idc_sbrs_out <= idc_sbrs;
2973 
idc_sbrc_out <= idc_sbrc;
2974 
idc_brbs_out <= idc_brbs;
2975 
idc_brbc_out <= idc_brbc;
2976 
-- SynEDA CoreMultiplier
2977 
-- assignment(s): idc_reti_out
2978 
-- replace(s): idc_reti
2979 
 
2980 
idc_reti_out_cml_out <= idc_reti_cml_3;
2981 
 
2982 
-- POST INCREMENT/PRE DECREMENT FOR THE X,Y,Z REGISTERS
2983 
post_inc <= idc_psinc;
2984 
-- SynEDA CoreMultiplier
2985 
-- assignment(s): pre_dec
2986 
-- replace(s): idc_prdec
2987 
 
2988 
pre_dec_cml_out  <= idc_prdec_cml_1;
2989 
-- SynEDA CoreMultiplier
2990 
-- assignment(s): reg_h_wr
2991 
-- replace(s): idc_ld_x, idc_ld_y, idc_ld_z, idc_st_x, idc_st_y, idc_st_z, idc_prdec
2992 
 
2993 
reg_h_wr_cml_out <= (idc_st_x_cml_3 or idc_st_y_cml_3 or idc_st_z_cml_3 or idc_ld_x_cml_3 or idc_ld_y_cml_3 or idc_ld_z_cml_3) and (idc_psinc or idc_prdec_cml_3);
2994 
 
2995 
reg_h_adr_cml_out(0)<= idc_st_x_cml_1 or idc_ld_x_cml_1;
2996 
reg_h_adr_cml_out(1)<= idc_st_y_cml_1 or idc_std_y_cml_1 or idc_ld_y_cml_1 or idc_ldd_y_cml_1;
2997 
-- SynEDA CoreMultiplier
2998 
-- assignment(s): reg_h_adr
2999 
-- replace(s): idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
3000 
 
3001 
reg_h_adr_cml_out(2)<= idc_st_z_cml_1 or idc_std_z_cml_1 or idc_ld_z_cml_1 or idc_ldd_z_cml_1;
3002 
 
3003 
-- SynEDA CoreMultiplier
3004 
-- assignment(s): sp_en
3005 
-- replace(s): cpuwait, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti
3006 
 
3007 
-- SynEDA CoreMultiplier
3008 
-- assignment(s): sp_ndown_up
3009 
-- replace(s): cpuwait, ret_st1, reti_st1, idc_pop, idc_ret, idc_reti
3010 
 
3011 
-- STACK POINTER CONTROL
3012 
sp_ndown_up_cml_out <= idc_pop_cml_3 or idc_ret_cml_3 or (ret_st1_cml_3 and not cpuwait_cml_3) or idc_reti_cml_3 or (reti_st1_cml_3 and not cpuwait_cml_3); -- ?????????
3013 
sp_en_cml_out <= idc_push_cml_3 or idc_pop_cml_3 or idc_rcall_cml_3 or (rcall_st1_cml_3 and not cpuwait_cml_3) or idc_icall_cml_3 or (icall_st1_cml_3 and not cpuwait_cml_3) or
3014 
idc_ret_cml_3 or (ret_st1_cml_3 and not cpuwait_cml_3) or idc_reti_cml_3 or (reti_st1_cml_3 and not cpuwait_cml_3) or
3015 
call_st1_cml_3 or (call_st2_cml_3 and not cpuwait_cml_3) or irq_st1_cml_3 or (irq_st2_cml_3 and not cpuwait_cml_3); --????????
3016 
 
3017 
 
3018 
branch  <= dex_condition;
3019 
bit_num_r_io <= cbi_sbi_bit_num_tmp when (cbi_st or sbi_st)='1' else dex_bitop_bitnum;
3020 
 
3021 
adr <= adr_int;
3022 
 
3023 
ramre <= ramre_int;
3024 
ramwe <= ramwe_int;
3025 
 
3026 
iore <= iore_int;
3027 
-- SynEDA CoreMultiplier
3028 
-- assignment(s): iowe
3029 
-- replace(s): iowe_int
3030 
 
3031 
iowe_cml_out <= iowe_int_cml_3;
3032 
 
3033 
--dbusout <= dbusout_int;
3034 
 
3035 
-- Sleep Control
3036 
sleepi <= idc_sleep;
3037 
-- SynEDA CoreMultiplier
3038 
-- assignment(s): irqok
3039 
-- replace(s): irq_int
3040 
 
3041 
irqok_cml_out  <= irq_int_cml_3;
3042 
 
3043 
-- Watchdog
3044 
wdri <= idc_wdr;
3045 
 
3046 
-- ************************** JTAG OCD support ************************************
3047 
 
3048 
-- Change of flow
3049 
change_flow <= '0';
3050 
valid_instr <= '0';
3051 
 
3052 
 
3053 
end RTL;

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