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[/] [avs_aes/] [trunk/] [bench/] [VHDL/] [avs_aes_tb.vhd] - Blame information for rev 15

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1 2 ruschi
--------------------------------------------------------------------------------
2 11 ruschi
-- This file is part of the project      avs_aes
3 10 ruschi
-- see: http://opencores.org/project,avs_aes
4 2 ruschi
--
5
-- description:
6
-- Simple testbench for the avalon interface avs_aes together with aes_core.
7
--
8
-- Todo:  a lot! make it look nicer, more generic, maybe read data from file
9
--
10
-- Author(s):
11
--         Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
12
--
13
--------------------------------------------------------------------------------
14
-- Copyright (c) 2009, Thomas Ruschival
15
-- All rights reserved.
16
--
17
-- Redistribution and use in source and binary forms, with or without modification,
18
-- are permitted provided that the following conditions are met:
19 11 ruschi
--        * Redistributions of source code must retain the above copyright notice,
20
--        this list of conditions and the following disclaimer.
21
--        * Redistributions in binary form must reproduce the above copyright notice,
22
--        this list of conditions and the following disclaimer in the documentation
23
--        and/or other materials provided with the distribution.
24
--        * Neither the name of the      nor the names of its contributors
25
--        may be used to endorse or promote products derived from this software without
26
--        specific prior written permission.
27 2 ruschi
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
31
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
32
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
37
-- THE POSSIBILITY OF SUCH DAMAGE
38
-------------------------------------------------------------------------------
39
-- version management:
40
-- $Author$
41
-- $Date$
42
-- $Revision$                   
43
-------------------------------------------------------------------------------
44
 
45
 
46
library ieee;
47
use ieee.std_logic_1164.all;
48
use ieee.numeric_std.all;
49
 
50 11 ruschi
library avs_aes_lib;
51
use avs_aes_lib.avs_aes_pkg.all;
52
 
53 2 ruschi
-------------------------------------------------------------------------------
54
 
55
entity avs_aes_tb is
56
end entity avs_aes_tb;
57
 
58
-------------------------------------------------------------------------------
59
 
60
architecture arch1 of avs_aes_tb is
61
 
62
        -- component ports
63
        signal clk                                : STD_LOGIC                                     := '0';  -- avalon bus clock
64
        signal reset                      : STD_LOGIC                                     := '0';  -- avalon bus reset
65
        signal writedata                  : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');  -- data write port
66
        signal address                    : STD_LOGIC_VECTOR(4 downto 0)  := (others => '0');  -- slave address space offset
67
        signal write                      : STD_LOGIC                                     := '0';  -- write enable
68
        signal read                               : STD_LOGIC                                     := '0';  -- read request form avalon
69
        signal irq                                : STD_LOGIC;  -- interrupt to signal completion
70
        signal readdata                   : STD_LOGIC_VECTOR(31 downto 0);       -- result read port
71
        signal chipselect                 : STD_LOGIC;  -- enable component
72
        signal keyexp_done                : STD_LOGIC;
73
        signal avs_s1_waitrequest : STD_LOGIC;
74
 
75 11 ruschi
-------------------------------------------------------------------------------
76
-- test setup
77
-------------------------------------------------------------------------------
78
    constant TESTKEYSIZE : NATURAL := 128;
79
        constant KEYWORDS : NATURAL := TESTKEYSIZE/32;
80 2 ruschi
 
81 11 ruschi
        -- Signals for comparison
82
    signal testresult : DWORDARRAY(0 to 3);
83
    signal expected : DWORDARRAY(0 to 3);
84
    ---------------------------------------------------------------------------
85
        -- 1st Test: KeySetup +Encryption
86
        -- encrypt data_1 using key_1
87
    -- KEY:     603DEB1015CA71BE2B73AEF0857D77811F352C073B6108D72D9810A30914DFF4
88
        -- DATA:        AA221133114411551166117721212121
89
        ---------------------------------------------------------------------------
90
        -- key(0) is most significant word
91
        signal key_1 : DWORDARRAY(0 to 7) := (
92
 
93
                2 => X"2B73AEF0", 3 => X"857D7781",
94
                4 => X"1F352C07", 5 => X"3B6108D7",
95
                6 => X"2D9810A3", 7 => X"0914DFF4") ;
96
        signal data_1 : DWORDARRAY(0 to 3) := (
97
 
98
                2 => X"11661177", 3 => X"21212121");
99 2 ruschi
 
100 11 ruschi
        -- Expected result
101
        -- RESULT(encrypt):
102
        signal result256_1 : DWORDARRAY(0 to 3) := (
103
 
104
                2 => X"1A07623A", 3 => X"8E6E197B");
105 2 ruschi
 
106 11 ruschi
        signal result192_1 : DWORDARRAY(0 to 3) := (
107
 
108
                2 => X"C83EBA16", 3 => X"C5DB0D63");
109
 
110
        signal result128_1 : DWORDARRAY(0 to 3) := (
111
 
112
                2 => X"F3D2679C", 3 => X"4CB2F5B0");
113
 
114
 ------------------------------------------------------------------------------
115
 -- 2nd test: Decrypt
116
 -- Treat data_1 as cyphertext and perform decryption
117
 -- under given key_1
118
 ------------------------------------------------------------------------------
119
        signal result256_2 : DWORDARRAY(0 to 3) := (
120
 
121
                2 => X"8A1AD035", 3 => X"CAE6B024");
122
 
123
        signal result192_2 : DWORDARRAY(0 to 3) := (
124
 
125
                2 => X"CC18A1D6", 3 => X"C5D00B70");
126
 
127
        signal result128_2 : DWORDARRAY(0 to 3) := (
128
 
129
                2 => X"652E4125", 3 => X"11C98F9F");
130
 
131
-------------------------------------------------------------------------------
132
-- 3rd TestCase: Same as Testcase1 whitout loading key
133
-- to see if any internal state was kept
134
-------------------------------------------------------------------------------
135
        -- Expected result
136
        signal result256_3 : DWORDARRAY(0 to 3) := (
137
 
138
                2 => X"1A07623A", 3 => X"8E6E197B");
139
 
140
        signal result192_3 : DWORDARRAY(0 to 3) := (
141
 
142
                2 => X"C83EBA16", 3 => X"C5DB0D63");
143
 
144
        signal result128_3 : DWORDARRAY(0 to 3) := (
145
 
146
                2 => X"F3D2679C", 3 => X"4CB2F5B0");
147
 
148
-------------------------------------------------------------------------------
149
-- 4th TestCase: encrypt new Data, same key
150
-- DATA: AA2211CC 11440055 11001177 2121BBBB
151
------------------------------------------------------------------------------- 
152
        signal data_4 : DWORDARRAY(0 to 3) := (
153
 
154
                2 => X"11001177", 3 => X"2121BBBB");
155
        -- Expected result
156
        signal result256_4 : DWORDARRAY(0 to 3) := (
157
 
158
                2 => X"D7D39EE4", 3 => X"78900016");
159
 
160
        signal result192_4 : DWORDARRAY(0 to 3) := (
161
 
162
                2 => X"3F1B068F", 3 => X"93133736");
163
 
164
        signal result128_4 : DWORDARRAY(0 to 3) := (
165
 
166
                2 => X"8B479AE5", 3 => X"A6090EA7");
167
 
168
 
169
-------------------------------------------------------------------------------
170
-- 5th TestCase: Same Data as in 4, new key, encrypt
171
------------------------------------------------------------------------------- 
172
        signal key_5 : DWORDARRAY(0 to 7) := (
173
 
174
                2 => X"01234567", 3 => X"89ABCDEF",
175
                4 => X"AAAAAAAA", 5 => X"BBBBBBBB",
176
                6 => X"55555555", 7 => X"77777777") ;
177
 
178
        -- Expected result      
179
        signal result256_5 : DWORDARRAY(0 to 3) := (
180
 
181
                2 => X"05E71527", 3 => X"91F5975A");
182
 
183
        signal result192_5 : DWORDARRAY(0 to 3) := (
184
 
185
                2 => X"7E96025B", 3 => X"3278C352");
186
 
187
        signal result128_5 : DWORDARRAY(0 to 3) := (
188
 
189
                2 => X"B81AD39B", 3 => X"BBAD3530");
190
 
191
 
192
 
193
 
194
 
195
 ------------------------------------------------------------------------------
196
 -- Testbench begin
197
 ------------------------------------------------------------------------------  
198 2 ruschi
begin  -- architecture arch1
199 11 ruschi
        avs_aes_1 : entity avs_aes_lib.avs_aes
200 2 ruschi
                generic map (
201 11 ruschi
                        KEYLENGTH  => TESTKEYSIZE,                      -- AES key length
202 2 ruschi
                        DECRYPTION => true)                     -- With decrypt or encrypt only
203
                port map (
204
                        clk                                => clk,      -- avalon bus clock
205
                        reset                      => reset,    -- avalon bus reset
206
                        avs_s1_chipselect  => chipselect,                  -- enable component
207
                        avs_s1_writedata   => writedata,                   -- data write port
208
                        avs_s1_address     => address,  -- slave address space offset
209
                        avs_s1_write       => write,    -- write enable
210
                        avs_s1_read                => read,             -- read request form avalon
211
                        avs_s1_irq                 => irq,      -- interrupt to signal completion
212
                        avs_s1_waitrequest => avs_s1_waitrequest,  -- stall operations
213
                        avs_s1_readdata    => readdata);                   -- result read port
214 11 ruschi
 
215 2 ruschi
        -- clock generation
216
        Clk <= not Clk after 10 ns;
217
 
218
        -- waveform generation
219
        WaveGen_Proc : process
220
        begin
221
                -- insert signal assignments here
222
                reset      <= '1';
223
                write      <= '0';
224
                read       <= '0';
225
                wait for 25 ns;
226
                reset      <= '0';
227
                chipselect <= '1';
228
                wait until clk = '1';
229
 
230 11 ruschi
-----------------------------------------------------------------------
231
-- Test1
232
-----------------------------------------------------------------------
233
                if TESTKEYSIZE = 256 then
234
                        expected <= result256_1;
235
                elsif TESTKEYSIZE = 192 then
236
                        expected <= result192_1;
237
                elsif TESTKEYSIZE = 128 then
238
                        expected <= result128_1;
239
                else
240
                        report "wrong testkeysize" severity FAILURE;
241
                end if;
242
 
243
                -----------------------------------------------------------------------
244
                -- Setup key1
245
                -----------------------------------------------------------------------
246
                for cnt in 0 to KEYWORDS-1 loop
247
                        write <= '1';
248
                        address <= STD_LOGIC_VECTOR(to_unsigned(cnt,5));
249
                        writedata <= key_1(cnt);
250
                        wait until clk='1';
251
                end loop;  -- cnt
252
                -----------------------------------------------------------------------
253
                -- Send data
254
                -----------------------------------------------------------------------
255
                for cnt in 0 to 3 loop
256
                        write <= '1';
257
                        address <= STD_LOGIC_VECTOR(to_unsigned(8+cnt,5));
258
                        writedata <= data_1(cnt);
259
                        wait until clk='1';
260
                end loop;  -- cnt
261
 
262 2 ruschi
                -- write control
263 11 ruschi
                -- data stable, key_stable irq_ena
264 2 ruschi
                wait until clk = '1';
265
                write     <= '1';
266
                address   <= STD_LOGIC_VECTOR(to_unsigned(31, 5));
267
                writedata <= X"000000C1";
268
                wait until clk = '1';
269
                write     <= '0';
270 11 ruschi
                -- do the calc
271 2 ruschi
                wait until irq = '1';
272
                wait until clk = '1';
273 11 ruschi
                -----------------------------------------------------------------------
274
                --retrieve and check result
275
                -----------------------------------------------------------------------
276
                for cnt in 0 to 3 loop
277
                        read <= '1';
278
                        address <= STD_LOGIC_VECTOR(to_unsigned(16+cnt,5));
279
                        wait until clk = '1';
280
                        testresult(cnt) <= readdata;
281
                end loop;  -- cnt
282
 
283 2 ruschi
                wait until clk = '1';
284
 
285 11 ruschi
                if testresult /= expected then
286
                        report "RESULT MISMATCH! Test1 failed" severity ERROR;
287
                else
288
                        report "Test case 1 successful" severity note;
289
                end if;
290 2 ruschi
 
291
 
292
-------------------------------------------------------------------------------
293 11 ruschi
--  Test2: decrypt the the same data under the given key
294
-------------------------------------------------------------------------------
295
                if TESTKEYSIZE = 256 then
296
                        expected <= result256_2;
297
                elsif TESTKEYSIZE = 192 then
298
                        expected <= result192_2;
299
                elsif TESTKEYSIZE = 128 then
300
                        expected <= result128_2;
301
                else
302
                        report "wrong testkeysize test2" severity FAILURE;
303
                end if;
304
 
305 2 ruschi
                wait until clk = '1';
306 11 ruschi
                write            <= '1';
307 2 ruschi
                address   <= STD_LOGIC_VECTOR(to_unsigned(31, 5));
308
                writedata <= X"000000C2";
309
                wait until clk = '1';
310
                write     <= '0';
311
                -- do the calc
312
                wait until irq = '1';
313
                wait until clk = '1';
314 11 ruschi
                -----------------------------------------------------------------------
315
                --retrieve and check result
316
                -----------------------------------------------------------------------
317
                for cnt in 0 to 3 loop
318
                        read <= '1';
319
                        address <= STD_LOGIC_VECTOR(to_unsigned(16+cnt,5));
320
                        wait until clk = '1';
321
                        testresult(cnt) <= readdata;
322
                end loop;  -- cnt
323
 
324 2 ruschi
                wait until clk = '1';
325
 
326 11 ruschi
                if testresult /= expected then
327
                        report "RESULT MISMATCH! Test 2 failed" severity ERROR;
328
                else
329
                        report "Test case 2 successful" severity note;
330
                end if;
331 2 ruschi
 
332 11 ruschi
 
333 2 ruschi
-------------------------------------------------------------------------------
334 11 ruschi
-- TestCase3:  Encrypt again without changing anything
335
--  should yield the same result as TestCase1
336
-------------------------------------------------------------------------------
337
                if TESTKEYSIZE = 256 then
338
                        expected <= result256_1;
339
                elsif TESTKEYSIZE = 192 then
340
                        expected <= result192_1;
341
                elsif TESTKEYSIZE = 128 then
342
                        expected <= result128_1;
343
                else
344
                        report "wrong testkeysize" severity FAILURE;
345
                end if;
346
 
347 2 ruschi
                -- write control
348
                wait until clk = '1';
349
                write     <= '1';
350
                address   <= STD_LOGIC_VECTOR(to_unsigned(31, 5));
351
-- data stable, key_stable irq_ena
352
                writedata <= X"000000C1";
353
                wait until clk = '1';
354
                write     <= '0';
355
-- do the calc
356
                wait until irq = '1';
357
                wait until clk = '1';
358 11 ruschi
                -----------------------------------------------------------------------
359
                --retrieve and check result
360
                -----------------------------------------------------------------------
361
                for cnt in 0 to 3 loop
362
                        read <= '1';
363
                        address <= STD_LOGIC_VECTOR(to_unsigned(16+cnt,5));
364
                        wait until clk = '1';
365
                        testresult(cnt) <= readdata;
366
                end loop;  -- cnt
367
 
368 2 ruschi
                wait until clk = '1';
369 11 ruschi
 
370
                if testresult /= expected then
371
                        report "RESULT MISMATCH! Test 3 failed" severity ERROR;
372
                else
373
                        report "Test case 3 successful" severity note;
374
                end if;
375
 
376
 
377
-------------------------------------------------------------------------------
378
-- TestCase4: new data, same key 
379
-------------------------------------------------------------------------------
380
                if TESTKEYSIZE = 256 then
381
                        expected <= result256_4;
382
                elsif TESTKEYSIZE = 192 then
383
                        expected <= result192_4;
384
                elsif TESTKEYSIZE = 128 then
385
                        expected <= result128_4;
386
                else
387
                        report "wrong testkeysize" severity FAILURE;
388
                end if;
389
                -----------------------------------------------------------------------
390
                -- Send data
391
                -----------------------------------------------------------------------
392
                for cnt in 0 to 3 loop
393
                        write <= '1';
394
                        address <= STD_LOGIC_VECTOR(to_unsigned(8+cnt,5));
395
                        writedata <= data_4(cnt);
396
                        wait until clk='1';
397
                end loop;  -- cnt
398
 
399
                -- write control
400
                -- data stable, key_stable irq_ena
401 2 ruschi
                wait until clk = '1';
402 11 ruschi
                write     <= '1';
403
                address   <= STD_LOGIC_VECTOR(to_unsigned(31, 5));
404
                writedata <= X"000000C1";
405 2 ruschi
                wait until clk = '1';
406 11 ruschi
                write     <= '0';
407
                -- do the calc
408
                wait until irq = '1';
409 2 ruschi
                wait until clk = '1';
410 11 ruschi
                -----------------------------------------------------------------------
411
                --retrieve and check result
412
                -----------------------------------------------------------------------
413
                for cnt in 0 to 3 loop
414
                        read <= '1';
415
                        address <= STD_LOGIC_VECTOR(to_unsigned(16+cnt,5));
416
                        wait until clk = '1';
417
                        testresult(cnt) <= readdata;
418
                end loop;  -- cnt
419 2 ruschi
 
420 11 ruschi
                wait until clk = '1';
421 2 ruschi
 
422 11 ruschi
                if testresult /= expected then
423
                        report "RESULT MISMATCH! Test 4 failed" severity ERROR;
424
                else
425
                        report "Test case 4 successful" severity note;
426
                end if;
427 2 ruschi
 
428
-------------------------------------------------------------------------------
429 11 ruschi
-- 5th TestCase: Same Data, new key, encrypt
430
------------------------------------------------------------------------------- 
431
                if TESTKEYSIZE = 256 then
432
                        expected <= result256_5;
433
                elsif TESTKEYSIZE = 192 then
434
                        expected <= result192_5;
435
                elsif TESTKEYSIZE = 128 then
436
                        expected <= result128_5;
437
                else
438
                        report "wrong testkeysize" severity FAILURE;
439
                end if;
440
 
441
                -----------------------------------------------------------------------
442
                -- Setup key5
443
                -----------------------------------------------------------------------
444
                -- invalidate old key:
445 2 ruschi
                wait until clk = '1';
446
                write     <= '1';
447 11 ruschi
                address   <= STD_LOGIC_VECTOR(to_unsigned(31, 5));
448
                writedata <= X"00000000";
449 2 ruschi
                wait until clk = '1';
450 11 ruschi
 
451
                for cnt in 0 to KEYWORDS-1 loop
452
                        write <= '1';
453
                        address <= STD_LOGIC_VECTOR(to_unsigned(cnt,5));
454
                        writedata <= key_5(cnt);
455
                        wait until clk='1';
456
                end loop;  -- cnt
457
 
458
                -- write control
459 2 ruschi
                -- data stable, key_stable irq_ena
460
                wait until clk = '1';
461
                write     <= '1';
462
                address   <= STD_LOGIC_VECTOR(to_unsigned(31, 5));
463
                writedata <= X"000000C1";
464
                wait until clk = '1';
465
                write     <= '0';
466 11 ruschi
                -- do the calc
467 2 ruschi
                wait until irq = '1';
468
                wait until clk = '1';
469 11 ruschi
                -----------------------------------------------------------------------
470
                --retrieve and check result
471
                -----------------------------------------------------------------------
472
                for cnt in 0 to 3 loop
473
                        read <= '1';
474
                        address <= STD_LOGIC_VECTOR(to_unsigned(16+cnt,5));
475
                        wait until clk = '1';
476
                        testresult(cnt) <= readdata;
477
                end loop;  -- cnt
478
 
479 2 ruschi
                wait until clk = '1';
480
 
481 11 ruschi
                if testresult /= expected then
482
                        report "RESULT MISMATCH! Test 5 failed" severity ERROR;
483
                else
484
                        report "Test case 5 successful" severity note;
485
                end if;
486
 
487
 
488 2 ruschi
                wait;
489
        end process WaveGen_Proc;
490
 
491
 
492
 
493
end architecture arch1;

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