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[/] [avs_aes/] [trunk/] [rtl/] [VHDL/] [mixcol_inv.vhd] - Blame information for rev 21

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1 2 ruschi
--------------------------------------------------------------------------------
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-- This file is part of the project  avs_aes
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-- see: http://opencores.org/project,avs_aes
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--
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-- description:
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-- Mix the columns of the AES Block (decryption version)
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-- Invert what was computed in mixcol_fwd.vhd
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-- For decrytion the inverse matrix is needed:
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--
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--              | E B D 9 |       a(n,0)
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--              | 9 E B D | x a(n,1)  
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--              | D 9 E B |       a(n,2)
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--              | B D 9 E |       a(n,3)
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--
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-------------------------------------------------------------------------------
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--
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-- Author(s):
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--         Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
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--
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--------------------------------------------------------------------------------
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-- Copyright (c) 2009, Authors and opencores.org
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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--    * Redistributions of source code must retain the above copyright notice,
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--    this list of conditions and the following disclaimer.
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--    * Redistributions in binary form must reproduce the above copyright notice,
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--    this list of conditions and the following disclaimer in the documentation
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--    and/or other materials provided with the distribution.
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--    * Neither the name of the organization nor the names of its contributors
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--    may be used to endorse or promote products derived from this software without
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--    specific prior written permission.
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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-- THE POSSIBILITY OF SUCH DAMAGE
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-------------------------------------------------------------------------------
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-- version management:
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-- $Author::                                         $
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-- $Date::                                           $
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-- $Revision::                                       $
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use ieee.numeric_std.all;
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library avs_aes_lib;
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use avs_aes_lib.avs_aes_pkg.all;
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architecture inv of mixcol
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is
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        signal byte0 : BYTE;
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        signal byte1 : BYTE;
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        signal byte2 : BYTE;
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        signal byte3 : BYTE;
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begin  -- architecture ARCH1
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        -- Easier handling of the single cells of the column
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        byte0 <= col_in(31 downto 24);
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        byte1 <= col_in(23 downto 16);
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        byte2 <= col_in(15 downto 8);
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        byte3 <= col_in(7 downto 0);
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        -- purpose: multiplies the column of the input block with the matrix
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        -- type   : combinational
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        -- inputs : direction,byte0,byte1,byte2,byte3
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        -- outputs: col_out
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        matrix_mult : process ( byte0, byte1, byte2, byte3) is
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                -- temporary results for the row-col multiplication have to be 9 Bits
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                -- long because the input is shifted left
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                variable tmp_res0 : STD_LOGIC_VECTOR(10 downto 0);       -- result of row1*col
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                variable tmp_res1 : STD_LOGIC_VECTOR(10 downto 0);       -- result of row2*col
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                variable tmp_res2 : STD_LOGIC_VECTOR(10 downto 0);       -- result of row3*col
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                variable tmp_res3 : STD_LOGIC_VECTOR(10 downto 0);       -- result of row4*col
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        begin  -- process matrix_mult
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                -- Multiply by 1st row of the inverse matrix ( E B D 9 )
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                tmp_res0 := byte0 & "000" xor '0' & byte0 & "00" xor "00" & byte0 & '0' xor        -- byte0*8+byte0*4+byte0*2 +
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                                        byte1 & "000" xor "00" & byte1 & '0' xor "000" & byte1 xor       -- byte1*8      +  byte1*2 + byte1
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                                        byte2 & "000" xor "0" & byte2 & "00" xor "000" & byte2 xor       -- byte2*8      +  byte2*4 + byte2
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                                        byte3 & "000" xor "000" & byte3;  -- byte3*8 + byte3*1
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                -- check if bits>7 = 1 and XOR with magic numbers to make it 8 BIT
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                if tmp_res0(10) = '1' then
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                        tmp_res0 := tmp_res0 xor "10001101100";
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                end if;
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                if tmp_res0(9) = '1' then
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                        tmp_res0 := tmp_res0 xor "01000110110";
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                end if;
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                if tmp_res0(8) = '1' then
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                        tmp_res0 := tmp_res0 xor "00100011011";
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                end if;
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                -- Multiply by 2nd row of the inverse matrix ( 9 E B D )
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                tmp_res1 := byte0 & "000" xor "000" & byte0 xor
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                                        byte1 & "000" xor "0" & byte1 & "00" xor "00" & byte1 & '0' xor
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                                        byte2 & "000" xor "00" & byte2 & '0' xor "000" & byte2 xor
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                                        byte3 & "000" xor '0' & byte3 & "00" xor "000" & byte3;
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                -- check if bits>7 = 1 and XOR with magic numbers to make it 8 BIT
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                if tmp_res1(10) = '1' then
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                        tmp_res1 := tmp_res1 xor "10001101100";
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                end if;
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                if tmp_res1(9) = '1' then
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                        tmp_res1 := tmp_res1 xor "01000110110";
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                end if;
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                if tmp_res1(8) = '1' then
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                        tmp_res1 := tmp_res1 xor "00100011011";
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                end if;
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                -- Multiply by 3rd row of the inverse matrix    (D 9 E B) 
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                tmp_res2 := byte0 & "000" xor "0" & byte0 & "00" xor "000" & byte0 xor   --      byte0*8 +  byte0*4 + byte0
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                                        byte1 & "000" xor "000" & byte1 xor      -- byte1*8       +      byte1
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                                        byte2 & "000" xor "0" & byte2 & "00" xor "00" & byte2 &'0' xor    -- byte2*8      +  byte2*4 +   byte2*2
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                                        byte3 & "000" xor "00" & byte3 & '0' xor "000" & byte3;   -- byte3*8      +      byte3*2 + byte3
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                -- check if bits>7 = 1 and XOR with magic numbers to make it 8 BIT
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                if tmp_res2(10) = '1' then
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                        tmp_res2 := tmp_res2 xor "10001101100";
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                end if;
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                if tmp_res2(9) = '1' then
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                        tmp_res2 := tmp_res2 xor "01000110110";
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                end if;
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                if tmp_res2(8) = '1' then
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                        tmp_res2 := tmp_res2 xor "00100011011";
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                end if;
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                -- Multiply by 4th row of the inverse matrix (B D 9 E)
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                tmp_res3 := byte0 & "000" xor "00" & byte0 & '0' xor "000" & byte0 xor   --      byte0*8 +  byte0*2 + byte0*1
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                                        byte1 & "000" xor '0' & byte1 &"00" xor "000" & byte1 xor  -- byte1*8 + byte1*4 + byte1
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                                        byte2 & "000" xor "000" & byte2 xor      -- byte2*8 + byte2
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                                        byte3 & "000" xor "0" & byte3 & "00" xor "00" & byte3 &'0';        -- byte3*8      +       byte3*4 + byte3*2
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                -- check if bits>7 = 1 and XOR with magic numbers to make it 8 BIT
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                if tmp_res3(10) = '1' then
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                        tmp_res3 := tmp_res3 xor "10001101100";
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                end if;
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                if tmp_res3(9) = '1' then
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                        tmp_res3 := tmp_res3 xor "01000110110";
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                end if;
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                if tmp_res3(8) = '1' then
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                        tmp_res3 := tmp_res3 xor "00100011011";
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                end if;
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                -- build output signal (BYTE_RANGE =7 downto 0 see util_pkg.vhd)
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                col_out(31 downto 24) <= tmp_res0(BYTE_RANGE);
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                col_out(23 downto 16) <= tmp_res1(BYTE_RANGE);
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                col_out(15 downto 8)  <= tmp_res2(BYTE_RANGE);
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                col_out(7 downto 0)        <= tmp_res3(BYTE_RANGE);
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        end process matrix_mult;
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end architecture inv;
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