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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2009 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 9.1 Build 222 10/21/2009 SJ Web Edition
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# Date created = 13:58:07 April 02, 2010
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# avs_aes_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C35F484C8
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set_global_assignment -name TOP_LEVEL_ENTITY avs_aes
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:07 APRIL 02, 2010"
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set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP1"
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/shiftrow_inv.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/addroundkey.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/aes_core.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/aes_fsm_decrypt.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/aes_fsm_encrypt.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/avs_aes.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/avs_aes_pkg.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/keyexpansionV2.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/memory_word.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/mixcol.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/mixcol_fwd.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/mixcol_inv.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/mux2.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/mux3.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/sbox.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/sbox_arch1.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/sboxM4k.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/shiftrow.vhd
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set_global_assignment -name VHDL_FILE ../../rtl/VHDL/shiftrow_fwd.vhd
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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