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fblanco |
-- File generated by avuc.pl (7/8/2009)
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--
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---------------------------------------------------------------------------------------
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-- Copyright 2008 by USM
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-- Description: Search for the maximum number in a memory.
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---------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library work;
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use work.usm_pkg.all;
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entity max_mem is
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port (
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-- To start the program:
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avuc_start: in std_logic;
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-- To stop the program:
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avuc_rst: in std_logic;
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-- Main clock:
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clk: in std_logic;
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-- Memory data bus:
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mem_data: in std_logic_vector(7 downto 0);
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-- Memory address bus:
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mem_addr: out std_logic_vector(6 downto 0);
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-- State of the program (running/stopped):
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avuc_state: out std_logic
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);
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end max_mem;
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architecture program of max_mem is
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-- Temporary maximum number
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signal max_number: std_logic_vector(mem_data'range);
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-- Copy of output:
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signal mem_addr_s: std_logic_vector(mem_addr'range);
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-- Basic registers of usm:
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signal usm_opcode: std_logic_vector(2 downto 0);
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signal usm_pc: std_logic_vector(2 downto 0) := (others => '1');
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signal usm_data: std_logic_vector(2 downto 0);
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signal usm_cyclesno: std_logic_vector(0 downto 0);
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-- Cycles counter:
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signal usm_cy: std_logic_vector(1 downto 0);
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-- usm_cy(0) delayed 1 clock:
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signal usm_cy_0_d1: std_logic;
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-- To avoid usm_cy deadlock:
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signal usm_cy_rst: std_logic;
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-- Commands list:
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constant USMO_NOP:
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std_logic_vector(usm_opcode'range) := "000";
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constant USMO_JUMP:
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std_logic_vector(usm_opcode'range) := "001";
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constant USMO_MEM_ADDR_INI:
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std_logic_vector(usm_opcode'range) := "010";
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constant USMO_MEM_ADDR_INC:
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std_logic_vector(usm_opcode'range) := "011";
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constant USMO_MAX_NUMBER_INI:
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std_logic_vector(usm_opcode'range) := "100";
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constant USMO_MAX_NUMBER_ASSIGN:
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std_logic_vector(usm_opcode'range) := "101";
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constant USMO_JUMP_IF_MEM_ADDR_EQ_LAST:
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std_logic_vector(usm_opcode'range) := "110";
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constant USMO_JUMP_IF_MEM_DATA_LT_MAX:
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std_logic_vector(usm_opcode'range) := "111";
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-- Labels list:
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constant USML_NEXT1:
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std_logic_vector(usm_pc'range) := "100";
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constant USML_LOOP1:
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std_logic_vector(usm_pc'range) := "010";
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constant USML_BEGIN:
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std_logic_vector(usm_pc'range) := "000";
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constant USML_END:
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std_logic_vector(usm_pc'range) := "111";
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-- usm_pc reset:
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signal avuc_start_d: std_logic_vector(2 downto 0);
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signal avuc_rst_d: std_logic_vector(2 downto 0);
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signal stup_rst, stup_rst_d1: std_logic;
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signal stup_rst_cnt: std_logic_vector(5 downto 0) := (others => '0');
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signal usm_pc_gt_end: std_logic;
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signal usm_pc_ldini_init_d1: std_logic;
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signal usm_pc_ldend_init_d1: std_logic;
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-- usm_pc microcodes:
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signal usm_pc_inc: std_logic;
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signal usm_pc_ldjmp: std_logic;
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signal usm_pc_ldini: std_logic;
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signal usm_pc_ldend: std_logic;
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-- Remaining microcodes:
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signal usm_max_number_assign_0: std_logic;
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signal usm_max_number_ini_0: std_logic;
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signal usm_mem_addr_ini_0: std_logic;
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signal usm_mem_addr_inc_0: std_logic;
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begin
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--***************************** Program processes *****************************--
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-- Program start/stop/state:
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p_prog_init: process(clk)
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variable usm_pc_ld_init_var: std_logic;
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begin
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if rising_edge(clk) then
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-- Program start:
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avuc_start_d(0) <= avuc_start;
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avuc_start_d(1) <= avuc_start_d(0);
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avuc_start_d(2) <= avuc_start_d(1);
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usm_pc_ld_init_var := avuc_start_d(1) and not avuc_start_d(2);
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usm_pc_ldini_init_d1 <= usm_pc_ld_init_var;
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usm_pc_ldini <= usm_pc_ld_init_var or usm_pc_ldini_init_d1; -- 2 clocks long
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-- Program stop:
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if stup_rst = '1' then
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stup_rst_cnt <= stup_rst_cnt + 1;
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end if;
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stup_rst <= '0';
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if stup_rst_cnt(5 downto 4) /= 2 then
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stup_rst <= '1';
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end if;
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stup_rst_d1 <= stup_rst;
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usm_pc_gt_end <= '0';
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if usm_pc > USML_END and usm_pc_gt_end = '0' then
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usm_pc_gt_end <= '1';
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end if;
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avuc_rst_d(0) <= avuc_rst;
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avuc_rst_d(1) <= avuc_rst_d(0);
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avuc_rst_d(2) <= avuc_rst_d(1);
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usm_pc_ld_init_var := usm_pc_gt_end or (not stup_rst and stup_rst_d1) or
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( avuc_rst_d(1) and not avuc_rst_d(2) );
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usm_pc_ldend_init_d1 <= usm_pc_ld_init_var;
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usm_pc_ldend <= usm_pc_ld_init_var or usm_pc_ldend_init_d1; -- 2 clocks long
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-- Program state:
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avuc_state <= AVUC_STATE_RUNNING;
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if usm_pc = USML_END then
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avuc_state <= AVUC_STATE_STOPPED;
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end if;
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end if;
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end process p_prog_init;
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p_usm_prog_code: process(usm_pc)
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begin
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usm_data <= (others => '-');
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case usm_pc is
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when "000" =>
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usm_opcode <= USMO_MEM_ADDR_INI;
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usm_cyclesno <= (0 => '1', others => '0');
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when "001" =>
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usm_opcode <= USMO_MAX_NUMBER_INI;
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usm_cyclesno <= (0 => '1', others => '0');
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when "010" =>
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usm_opcode <= USMO_JUMP_IF_MEM_DATA_LT_MAX;
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usm_cyclesno <= (0 => '1', others => '0');
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usm_data <= "100";
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when "011" =>
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usm_opcode <= USMO_MAX_NUMBER_ASSIGN;
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usm_cyclesno <= (0 => '1', others => '0');
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when "100" =>
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usm_opcode <= USMO_JUMP_IF_MEM_ADDR_EQ_LAST;
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usm_cyclesno <= (0 => '1', others => '0');
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usm_data <= "111";
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when "101" =>
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usm_opcode <= USMO_MEM_ADDR_INC;
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usm_cyclesno <= (0 => '1', others => '0');
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when "110" =>
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usm_opcode <= USMO_JUMP;
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usm_cyclesno <= (0 => '1', others => '0');
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usm_data <= "010";
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when "111" =>
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usm_opcode <= USMO_JUMP;
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usm_cyclesno <= (0 => '1', others => '0');
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usm_data <= "111";
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when others =>
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usm_opcode <= (others => '-');
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usm_cyclesno <= (others => '-');
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end case;
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end process p_usm_prog_code;
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--************************** Jump & cycle processes ***************************--
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p_usm_pc_drv: process(clk)
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variable var_aux: std_logic_vector(3 downto 0);
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begin
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if rising_edge(clk) then
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-- usm_pc_inc (increment usm_pc):
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usm_pc_inc <= '0';
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if usm_cy = usm_cyclesno and usm_pc_ldini_init_d1 = '0' then
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usm_pc_inc <= '1';
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end if;
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-- usm_pc_ldjmp (load usm_pc with usm_data):
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usm_pc_ldjmp <= '0';
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case usm_opcode is
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when USMO_JUMP =>
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usm_pc_ldjmp <= '1';
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when USMO_JUMP_IF_MEM_ADDR_EQ_LAST =>
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if mem_addr_s = (mem_addr_s'range => '1') then
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usm_pc_ldjmp <= '1';
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end if;
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when USMO_JUMP_IF_MEM_DATA_LT_MAX =>
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if mem_data < max_number then
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usm_pc_ldjmp <= '1';
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end if;
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when others =>
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usm_pc_ldjmp <= '0';
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end case;
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-- usm_pc:
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usm_cy_0_d1 <= usm_cy(0) and not usm_pc_ldini_init_d1;
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var_aux := usm_pc_ldini & usm_pc_ldend & (usm_pc_ldjmp and usm_cy_0_d1) & usm_pc_inc;
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case var_aux is
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when "0000" =>
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null;
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when "0001" =>
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usm_pc <= usm_pc + 1;
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when "0010" | "0011" =>
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usm_pc <= usm_data(usm_pc'range);
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when "0100" | "0101" | "0110" | "0111" =>
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usm_pc <= USML_END;
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when "1000" | "1001" | "1010" | "1011" | "1100" | "1101" | "1110" | "1111" => -- 1XXX
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usm_pc <= USML_BEGIN;
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when others =>
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null;
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-- usm_pc <= USML_BEGIN;
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end case;
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end if;
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end process p_usm_pc_drv;
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p_usm_cy_drv: process(clk)
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begin
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if rising_edge(clk) then
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usm_cy_rst <= '0';
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if usm_cy = 0 then
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usm_cy_rst <= '1';
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end if;
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-- usm_cy:
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if usm_pc_inc = '1' or (usm_pc_ldjmp = '1' and usm_cy_0_d1 = '1') or
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usm_pc_ldini_init_d1 = '1' or usm_cy_rst = '1' then
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usm_cy <= (0 => '1', others => '0');
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else
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usm_cy(0) <= '0';
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for i in usm_cy'range loop
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if i /= 0 then
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usm_cy(i) <= usm_cy(i-1);
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end if;
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end loop;
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end if;
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end if;
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end process p_usm_cy_drv;
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--**************************** Drivers processes ******************************--
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p_usm_max_number_drv: process(clk)
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variable max_number_var: std_logic_vector(1 downto 0);
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begin
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if rising_edge(clk) then
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-- max_number_assign:
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usm_max_number_assign_0 <= '0';
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if usm_opcode = USMO_MAX_NUMBER_ASSIGN then
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if usm_cy(0) = '1' then
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usm_max_number_assign_0 <= '1';
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end if;
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end if;
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-- max_number_ini:
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usm_max_number_ini_0 <= '0';
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if usm_opcode = USMO_MAX_NUMBER_INI then
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if usm_cy(0) = '1' then
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usm_max_number_ini_0 <= '1';
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end if;
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end if;
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-- Actions:
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max_number_var := usm_max_number_assign_0 & usm_max_number_ini_0;
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case max_number_var is
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when "00" => null;
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when "10" =>
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max_number <= mem_data;
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when "01" =>
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max_number <= (others => '0');
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when others => null;
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end case;
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end if;
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end process p_usm_max_number_drv;
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p_usm_mem_addr_s_drv: process(clk)
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variable mem_addr_s_var: std_logic_vector(1 downto 0);
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begin
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if rising_edge(clk) then
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-- mem_addr_ini:
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usm_mem_addr_ini_0 <= '0';
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if usm_opcode = USMO_MEM_ADDR_INI then
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if usm_cy(0) = '1' then
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usm_mem_addr_ini_0 <= '1';
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end if;
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end if;
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-- mem_addr_inc:
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usm_mem_addr_inc_0 <= '0';
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if usm_opcode = USMO_MEM_ADDR_INC then
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if usm_cy(0) = '1' then
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usm_mem_addr_inc_0 <= '1';
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end if;
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end if;
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-- Actions:
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mem_addr_s_var := usm_mem_addr_inc_0 & usm_mem_addr_ini_0;
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case mem_addr_s_var is
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when "00" => null;
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when "10" =>
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mem_addr_s <= mem_addr_s + 1;
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when "01" =>
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mem_addr_s <= (others => '0');
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when others => null;
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end case;
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end if;
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end process p_usm_mem_addr_s_drv;
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--******************************** Extra code *********************************--
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mem_addr <= mem_addr_s;
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end program;
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