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-------------------------------------------------------------------------------
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-- Title : axil2wb
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-- Project :
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-------------------------------------------------------------------------------
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wzab |
-- File : axil2wb.vhd
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wzab |
-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
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-- Company : Institute of Electronic Systems, Warsaw University of Technology
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-- Created : 2016-04-24
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wzab |
-- Last update: 2016-05-15
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wzab |
-- License : This is a PUBLIC DOMAIN code, published under
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-- Creative Commons CC0 license
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: AXI Lite -> WB bridge
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-------------------------------------------------------------------------------
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-- Copyright (c) 2016
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2016-05-13 1.0 WZab Created
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-------------------------------------------------------------------------------
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-- The AXI implementation is based on the description of AXI provided by
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-- Rich Griffin in "Designing a Custom AXI-lite Slave Peripheral"
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-- available at:
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-- silica.com/wcsstore/Silica/Silica+Content+Library/Silica+Home/resources/71b10b18-9c9c-44c6-b62d-9a031b8f3df8/SILICA_Xilinx_Designing_a_custom_axi_slave_rev1.pdf
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--
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-------------------------------------------------------------------------------
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-- Implementation details
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-------------------------------------------------------------------------------
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-- In the AXI bus the read and write accesses may be handled independently
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-- In the IPbus they can't therefore we must provide an arbitration scheme.
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-- We assume "Write before read"
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--
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-- We must avoid duplicated writes and reads (which may corruppt e.g.
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-- FIFO slaves at IPbus!)
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--
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-- Additionally the IPbus uses the word adressing, while AXI uses the byte
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-- addressing. That is handled by the function a_axi2ipb, which additionally
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-- zeroes bits not used by the IPbus segment...
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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library work;
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entity axil2wb is
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generic (
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ADRWIDTH : integer := 15;
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DATAWIDTH : integer := 32);
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port (
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---------------------------------------------------------------------------
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-- AXI Interface
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---------------------------------------------------------------------------
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-- Clock and Reset
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S_AXI_ACLK : in std_logic;
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S_AXI_ARESETN : in std_logic;
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-- Write Address Channel
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S_AXI_AWADDR : in std_logic_vector(ADRWIDTH-1 downto 0);
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S_AXI_AWVALID : in std_logic;
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S_AXI_AWREADY : out std_logic;
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-- Write Data Channel
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S_AXI_WDATA : in std_logic_vector(31 downto 0);
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S_AXI_WSTRB : in std_logic_vector(3 downto 0);
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S_AXI_WVALID : in std_logic;
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S_AXI_WREADY : out std_logic;
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-- Read Address Channel
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S_AXI_ARADDR : in std_logic_vector(ADRWIDTH-1 downto 0);
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S_AXI_ARVALID : in std_logic;
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S_AXI_ARREADY : out std_logic;
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-- Read Data Channel
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S_AXI_RDATA : out std_logic_vector(31 downto 0);
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S_AXI_RRESP : out std_logic_vector(1 downto 0);
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S_AXI_RVALID : out std_logic;
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S_AXI_RREADY : in std_logic;
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-- Write Response Channel
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S_AXI_BRESP : out std_logic_vector(1 downto 0);
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S_AXI_BVALID : out std_logic;
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S_AXI_BREADY : in std_logic;
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wzab |
-- AWPROT and ARPROT - required by Altera
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--S_AXI_ARPROT : in std_logic_vector(2 downto 0);
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--S_AXI_AWPROT : in std_logic_vector(2 downto 0);
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wzab |
-- Here we have the WB ports
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-- The clock and reset are comming from AXI!
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wb_clk_o : out std_logic;
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wb_rst_o : out std_logic;
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-- master_ipb_out - flattened due to Vivado inability to handle user types
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-- in BD
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wb_addr_o : out std_logic_vector(31 downto 0);
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wb_dat_o : out std_logic_vector(31 downto 0);
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wb_we_o : out std_logic;
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wb_sel_o : out std_logic_vector(3 downto 0);
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wb_stb_o : out std_logic;
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wb_cyc_o : out std_logic;
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-- master_ipb_in - flattened due to Vivado inability to handle user types
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-- in BD
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wb_dat_i : in std_logic_vector(31 downto 0);
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wb_err_i : in std_logic; -- Not used in figure 1-2 in specification!
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wb_ack_i : in std_logic
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);
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end entity axil2wb;
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architecture beh of axil2wb is
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function a_axi2wb (
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constant axi_addr : std_logic_vector(ADRWIDTH-1 downto 0))
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return std_logic_vector is
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variable wb_addr : std_logic_vector(31 downto 0);
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begin -- function a_axi2wb
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wb_addr := (others => '0');
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-- Divide the address by 4 (we use word addresses, not the byte addresses)
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wb_addr(ADRWIDTH-3 downto 0) := axi_addr(ADRWIDTH-1 downto 2);
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return wb_addr;
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end function a_axi2wb;
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signal read_wait, read_wait_in, write_wait, write_wait_in : boolean := false;
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signal rdata, rdata_in, addr, addr_in, wdata, wdata_in : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
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signal bresp, rresp, bresp_in, rresp_in : std_logic_vector(1 downto 0) := "00";
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signal del_bresp, del_rresp, del_bresp_in, del_rresp_in : boolean := false;
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begin -- architecture beh
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wb_clk_o <= S_AXI_ACLK;
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wb_rst_o <= S_AXI_ARESETN;
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wb_sel_o <= (others => '1'); -- We support only whole word accesses
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qq : process (S_AXI_ARADDR, S_AXI_ARVALID, S_AXI_AWADDR, S_AXI_AWVALID,
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S_AXI_BREADY, S_AXI_RREADY, S_AXI_WDATA, S_AXI_WSTRB,
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S_AXI_WVALID, addr, bresp, del_bresp, del_rresp, rdata,
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read_wait, rresp, wb_ack_i, wb_dat_i, wb_err_i, wdata,
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write_wait) is
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variable is_read, is_write : boolean := false;
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begin -- process qq
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-- Defaults
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is_read := false;
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is_write := false;
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wb_stb_o <= '0';
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wb_addr_o <= (others => '0');
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wb_dat_o <= (others => '0');
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wb_we_o <= '0';
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wb_cyc_o <= '0';
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-- Flags handling delayed acceptance of results
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del_bresp_in <= del_bresp;
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del_rresp_in <= del_rresp;
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-- Registers storing the results
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bresp_in <= bresp;
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rresp_in <= rresp;
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rdata_in <= rdata;
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wdata_in <= wdata;
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read_wait_in <= read_wait;
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write_wait_in <= write_wait;
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addr_in <= addr;
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S_AXI_BVALID <= '0';
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S_AXI_BRESP <= (others => '0');
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S_AXI_ARREADY <= '0';
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S_AXI_RVALID <= '0';
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S_AXI_RDATA <= (others => '0');
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S_AXI_RRESP <= (others => '0');
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S_AXI_AWREADY <= '0';
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S_AXI_WREADY <= '0';
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-- Real processing
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-- Handling of delayed responses
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if del_bresp then
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S_AXI_BRESP <= bresp;
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S_AXI_BVALID <= '1';
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if S_AXI_BREADY = '1' then
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del_bresp_in <= false;
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end if;
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elsif del_rresp then
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S_AXI_RRESP <= rresp;
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S_AXI_RDATA <= rdata;
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S_AXI_RVALID <= '1';
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if S_AXI_RREADY = '1' then
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del_rresp_in <= false;
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end if;
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-- Handling of new transactions
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elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') or write_wait then
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is_write := true;
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elsif S_AXI_ARVALID = '1' or read_wait then
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is_read := true;
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end if;
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-- Set the IPbus signals
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if is_write then
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-- Check if this is a new transmission
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if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and write_wait = false then
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-- This is a new transmission
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-- Check if this is a correct 32-bit write
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if S_AXI_WSTRB /= "1111" then
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-- Erroneouos write. If slave is ready to accept status, inform about it
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S_AXI_AWREADY <= '1';
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S_AXI_WREADY <= '1';
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S_AXI_BRESP <= "10";
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S_AXI_BVALID <= '1';
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if S_AXI_BREADY = '0' then
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-- Prepare delayed response
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bresp_in <= "10";
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del_bresp_in <= true;
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end if;
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else
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-- Correct write
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-- Write transaction on IPbus
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wb_addr_o <= a_axi2wb(S_AXI_AWADDR);
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wb_dat_o <= S_AXI_WDATA;
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wb_stb_o <= '1';
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wb_cyc_o <= '1';
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wb_we_o <= '1';
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-- Store data for the next cycles
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addr_in <= a_axi2wb(S_AXI_AWADDR);
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wdata_in <= S_AXI_WDATA;
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S_AXI_AWREADY <= '1';
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S_AXI_WREADY <= '1';
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write_wait_in <= true;
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end if;
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else
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-- This the next cycle of the write transmission
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wb_addr_o <= addr;
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wb_dat_o <= wdata;
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wb_stb_o <= '1';
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wb_cyc_o <= '1';
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wb_we_o <= '1';
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end if;
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-- Check the slave response
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if wb_err_i = '1' then
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write_wait_in <= false;
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S_AXI_BRESP <= "10";
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S_AXI_BVALID <= '1';
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if S_AXI_BREADY = '0' then
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-- Prepare delayed response
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bresp_in <= "10";
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del_bresp_in <= true;
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end if;
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elsif wb_ack_i = '1' then
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write_wait_in <= false;
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S_AXI_BRESP <= "00";
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S_AXI_BVALID <= '1';
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if S_AXI_BREADY = '0' then
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-- Prepare delayed response
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bresp_in <= "00";
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del_bresp_in <= true;
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end if;
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end if;
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elsif is_read then
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-- Read transaction on IPbus
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if S_AXI_ARVALID = '1' and read_wait = false then
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addr_in <= a_axi2wb(S_AXI_ARADDR);
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wb_addr_o <= a_axi2wb(S_AXI_ARADDR);
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S_AXI_ARREADY <= '1';
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-- Remember that we are in read
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read_wait_in <= true;
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else
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wb_addr_o <= addr;
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end if;
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wb_stb_o <= '1';
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wb_cyc_o <= '1';
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wb_we_o <= '0';
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-- Check the slave response
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if wb_err_i = '1' then
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S_AXI_RRESP <= "10";
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S_AXI_RDATA <= wb_dat_i;
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S_AXI_RVALID <= '1';
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read_wait_in <= false;
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if S_AXI_RREADY = '0' then
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-- Prepare delayed response
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rresp_in <= "10";
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rdata_in <= wb_dat_i;
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del_rresp_in <= true;
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end if;
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elsif wb_ack_i = '1' then
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S_AXI_RRESP <= "00";
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S_AXI_RDATA <= wb_dat_i;
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S_AXI_RVALID <= '1';
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read_wait_in <= false;
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if S_AXI_RREADY = '0' then
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-- Prepare delayed response
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rresp_in <= "00";
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rdata_in <= wb_dat_i;
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del_rresp_in <= true;
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end if;
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end if;
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end if;
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end process qq;
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process (S_AXI_ACLK) is
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begin -- process
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if S_AXI_ACLK'event and S_AXI_ACLK = '1' then -- rising clock edge
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if S_AXI_ARESETN = '0' then -- synchronous reset (active low)
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del_rresp <= false;
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del_bresp <= false;
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rdata <= (others => '0');
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wdata <= (others => '0');
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rresp <= (others => '0');
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bresp <= (others => '0');
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addr <= (others => '0');
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read_wait <= false;
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write_wait <= false;
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else
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del_rresp <= del_rresp_in;
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del_bresp <= del_bresp_in;
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addr <= addr_in;
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rdata <= rdata_in;
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wdata <= wdata_in;
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rresp <= rresp_in;
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bresp <= bresp_in;
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read_wait <= read_wait_in;
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write_wait <= write_wait_in;
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end if;
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end if;
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end process;
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end architecture beh;
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