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[/] [ax8/] [trunk/] [bench/] [vhdl/] [AsyncStim.vhd] - Blame information for rev 31

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1 2 jesus
--
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-- Asynchronous serial generator with input from binary file
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--
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-- Version : 0146
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--
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-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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--      http://www.opencores.org/cvsweb.shtml/t51/
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--
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-- Limitations :
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--
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-- File history :
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity AsyncStim is
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        generic(
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                FileName                : string;
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                Baud                    : integer;
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                InterCharDelay  : time := 0 ns;
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                Bits                    : integer := 8;         -- Data bits
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                Parity                  : boolean := false;     -- Enable Parity
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                P_Odd_Even_n    : boolean := false      -- false => Even Parity, true => Odd Parity
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        );
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        port(
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                TXD                             : out std_logic
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        );
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end AsyncStim;
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architecture behaviour of AsyncStim is
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        signal  TX_ShiftReg             : std_logic_vector(Bits - 1 downto 0);
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        signal  TX_Bit_Cnt              : integer range 0 to 15 := 0;
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        signal  ParTmp                  : boolean;
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begin
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        process
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                type ChFile is file of character;
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                file InFile                             : ChFile open read_mode is FileName;
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                variable Inited                 : boolean := false;
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                variable CharTmp                : character;
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                variable IntTmp                 : integer;
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        begin
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                if not Inited then
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                        Inited := true;
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                        TXD <= '1';
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                end if;
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                wait for 1000000000 ns / Baud;
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                TX_Bit_Cnt <= TX_Bit_Cnt + 1;
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                case TX_Bit_Cnt is
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                when 0 =>
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                        TXD <= '1';
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                        wait for InterCharDelay;
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                when 1 => -- Start bit
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                        read(InFile, CharTmp);
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                        IntTmp := character'pos(CharTmp);
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                        TX_ShiftReg(Bits - 1 downto 0) <= std_logic_vector(to_unsigned(IntTmp, Bits));
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                        TXD <= '0';
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                        ParTmp <= P_Odd_Even_n;
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                when others =>
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                        TXD <= TX_ShiftReg(0);
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                        ParTmp <= ParTmp xor (TX_ShiftReg(0) = '1');
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                        TX_ShiftReg(Bits - 2 downto 0) <= TX_ShiftReg(Bits - 1 downto 1);
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                        if (TX_Bit_Cnt = Bits + 1 and not Parity) or
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                                (TX_Bit_Cnt = Bits + 2 and Parity) then -- Stop bit
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                                TX_Bit_Cnt <= 0;
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                        end if;
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                        if Parity and TX_Bit_Cnt = Bits + 2 then
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                                if ParTmp then
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                                        TXD <= '1';
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                                else
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                                        TXD <= '0';
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                                end if;
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                        end if;
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                end case;
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        end process;
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end;

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