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--
-- 90S2313 compatible microcontroller core
--
-- Version : 0224
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
--      http://www.opencores.org/cvsweb.shtml/ax8/
--
-- Limitations :
--
-- File history :
--
--      0146    : First release
--      0220    : Changed to synchronous ROM
--      0220b   : Changed reset
--      0221    : Changed to configurable buses
--      0224    : Fixed timer interrupt enables
 
--Registers:                                                                                            Comments:
--$3F SREG Status Register                                                                      Implemented in the AX8 core
--$3D SPL Stack Pointer Low                                                                     Implemented in the AX8 core
--$3B GIMSK General Interrupt Mask register
--$3A GIFR General Interrupt Flag Register
--$39 TIMSK Timer/Counter Interrupt Mask register
--$38 TIFR Timer/Counter Interrupt Flag register
--$35 MCUCR MCU General Control Register                                        No power down
--$33 TCCR0 Timer/Counter 0 Control Register
--$32 TCNT0 Timer/Counter 0 (8-bit)
--$2F TCCR1A Timer/Counter 1 Control Register A
--$2E TCCR1B Timer/Counter 1 Control Register B
--$2D TCNT1H Timer/Counter 1 High Byte
--$2C TCNT1L Timer/Counter 1 Low Byte
--$2B OCR1AH Output Compare Register 1 High Byte
--$2A OCR1AL Output Compare Register 1 Low Byte
--$25 ICR1H T/C 1 Input Capture Register High Byte
--$24 ICR1L T/C 1 Input Capture Register Low Byte
--$21 WDTCR Watchdog Timer Control Register                                     Not implemented
--$1E EEAR EEPROM Address Register                                                      Not implemented
--$1D EEDR EEPROM Data Register                                                         Not implemented
--$1C EECR EEPROM Control Register                                                      Not implemented
--$18 PORTB Data Register, Port B                                                       No pullup
--$17 DDRB Data Direction Register, Port B
--$16 PINB Input Pins, Port B
--$12 PORTD Data Register, Port D                                                       No pullup
--$11 DDRD Data Direction Register, Port D
--$10 PIND Input Pins, Port D
--$0C UDR UART I/O Data Register
--$0B USR UART Status Register
--$0A UCR UART Control Register
--$09 UBRR UART Baud Rate Register
--$08 ACSR Analog Comparator Control and Status Register        Not implemented
 
library IEEE;
use IEEE.std_logic_1164.all;
use work.AX_Pack.all;
 
entity A90S2313 is
        generic(
                SyncReset : boolean := true;
                TriState : boolean := false
        );
        port(
                Clk             : in std_logic;
                Reset_n : in std_logic;
                INT0    : in std_logic;
                INT1    : in std_logic;
                T0              : in std_logic;
                T1              : in std_logic;
                ICP             : in std_logic;
                RXD             : in std_logic;
                TXD             : out std_logic;
                OC              : out std_logic;
                Port_B  : inout std_logic_vector(7 downto 0);
                Port_D  : inout std_logic_vector(7 downto 0)
        );
end A90S2313;
 
architecture rtl of A90S2313 is
 
        constant        ROMAddressWidth         : integer := 10;
        constant        RAMAddressWidth         : integer := 7;
        constant        BigISet                         : boolean := true;
 
        component ROM2313
                port(
                        Clk     : in std_logic;
                        A       : in std_logic_vector(ROMAddressWidth - 1 downto 0);
                        D       : out std_logic_vector(15 downto 0)
                );
        end component;
 
        signal  Reset_s_n       : std_logic;
        signal  ROM_Addr        : std_logic_vector(ROMAddressWidth - 1 downto 0);
        signal  ROM_Data        : std_logic_vector(15 downto 0);
        signal  SREG            : std_logic_vector(7 downto 0);
        signal  SP                      : std_logic_vector(15 downto 0);
        signal  IO_Rd           : std_logic;
        signal  IO_Wr           : std_logic;
        signal  IO_Addr         : std_logic_vector(5 downto 0);
        signal  IO_WData        : std_logic_vector(7 downto 0);
        signal  IO_RData        : std_logic_vector(7 downto 0);
        signal  TCCR0_Sel       : std_logic;
        signal  TCNT0_Sel       : std_logic;
        signal  TCCR1_Sel       : std_logic;
        signal  TCNT1_Sel       : std_logic;
        signal  OCR1_Sel        : std_logic;
        signal  ICR1_Sel        : std_logic;
        signal  UDR_Sel         : std_logic;
        signal  USR_Sel         : std_logic;
        signal  UCR_Sel         : std_logic;
        signal  UBRR_Sel        : std_logic;
        signal  PORTB_Sel       : std_logic;
        signal  DDRB_Sel        : std_logic;
        signal  PINB_Sel        : std_logic;
        signal  PORTD_Sel       : std_logic;
        signal  DDRD_Sel        : std_logic;
        signal  PIND_Sel        : std_logic;
        signal  Sleep_En        : std_logic;
        signal  ISC0            : std_logic_vector(1 downto 0);
        signal  ISC1            : std_logic_vector(1 downto 0);
        signal  Int_ET          : std_logic_vector(1 downto 0);
        signal  Int_En          : std_logic_vector(1 downto 0);
        signal  Int0_r          : std_logic_vector(1 downto 0);
        signal  Int1_r          : std_logic_vector(1 downto 0);
        signal  TC_Trig         : std_logic;
        signal  TO_Trig         : std_logic;
        signal  OC_Trig         : std_logic;
        signal  IC_Trig         : std_logic;
        signal  TOIE0           : std_logic;
        signal  TICIE1          : std_logic;
        signal  OCIE1           : std_logic;
        signal  TOIE1           : std_logic;
        signal  TOV0            : std_logic;
        signal  ICF1            : std_logic;
        signal  OCF1            : std_logic;
        signal  TOV1            : std_logic;
        signal  Int_Trig        : std_logic_vector(15 downto 1);
        signal  Int_Acc         : std_logic_vector(15 downto 1);
        signal  TCCR0           : std_logic_vector(2 downto 0);
        signal  TCNT0           : std_logic_vector(7 downto 0);
        signal  COM                     : std_logic_vector(1 downto 0);
        signal  PWM                     : std_logic_vector(1 downto 0);
        signal  CRBH            : std_logic_vector(1 downto 0);
        signal  CRBL            : std_logic_vector(3 downto 0);
        signal  TCNT1           : std_logic_vector(15 downto 0);
        signal  IC                      : std_logic_vector(15 downto 0);
        signal  OCR                     : std_logic_vector(15 downto 0);
        signal  Tmp                     : std_logic_vector(15 downto 0);
        signal  UDR                     : std_logic_vector(7 downto 0);
        signal  USR                     : std_logic_vector(7 downto 3);
        signal  UCR                     : std_logic_vector(7 downto 0);
        signal  UBRR            : std_logic_vector(7 downto 0);
        signal  DirB            : std_logic_vector(7 downto 0);
        signal  Port_InB        : std_logic_vector(7 downto 0);
        signal  Port_OutB       : std_logic_vector(7 downto 0);
        signal  DirD            : std_logic_vector(7 downto 0);
        signal  Port_InD        : std_logic_vector(7 downto 0);
        signal  Port_OutD       : std_logic_vector(7 downto 0);
 
begin
 
        -- Synchronise reset
        process (Reset_n, Clk)
                variable Reset_v : std_logic;
        begin
                if Reset_n = '0' then
                        if SyncReset then
                                Reset_s_n <= '0';
                                Reset_v := '0';
                        end if;
                elsif Clk'event and Clk = '1' then
                        if SyncReset then
                                Reset_s_n <= Reset_v;
                                Reset_v := '1';
                        end if;
                end if;
        end process;
 
        g_reset : if not SyncReset generate
                Reset_s_n <= Reset_n;
        end generate;
 
        -- Registers/Interrupts
        process (Reset_s_n, Clk)
        begin
                if Reset_s_n = '0' then
                        Sleep_En <= '0';
                        ISC0 <= "00";
                        ISC1 <= "00";
                        Int_ET <= "00";
                        Int_En <= "00";
                        Int0_r <= "11";
                        Int1_r <= "11";
                        TOIE0 <= '0';
                        TICIE1 <= '0';
                        OCIE1 <= '0';
                        TOIE1 <= '0';
                        TOV0 <= '0';
                        ICF1 <= '0';
                        OCF1 <= '0';
                        TOV1 <= '0';
                elsif Clk'event and Clk = '1' then
                        Int0_r(0) <= INT0;
                        Int0_r(1) <= Int0_r(0);
                        Int1_r(0) <= INT1;
                        Int1_r(1) <= Int1_r(0);
                        if IO_Wr = '1' and IO_Addr = "110101" then      -- $35 MCUCR
                                Sleep_En <= IO_WData(5);
                                ISC0 <= IO_WData(1 downto 0);
                                ISC1 <= IO_WData(3 downto 2);
                        end if;
                        if IO_Wr = '1' and IO_Addr = "111011" then      -- $3B GIMSK
                                Int_En <= IO_WData(7 downto 6);
                        end if;
                        if IO_Wr = '1' and IO_Addr = "111001" then      -- $39 TIMSK
                                TOIE0 <= IO_WData(1);
                                TICIE1 <= IO_WData(3);
                                OCIE1 <= IO_WData(6);
                                TOIE1 <= IO_WData(7);
                        end if;
                        if IO_Wr = '1' and IO_Addr = "111000" then      -- $38 TIFR
                                if IO_WData(1) = '1' then
                                        TOV0 <= '0';
                                end if;
                                if IO_WData(3) = '1' then
                                        ICF1 <= '0';
                                end if;
                                if IO_WData(6) = '1' then
                                        OCF1 <= '0';
                                end if;
                                if IO_WData(7) = '1' then
                                        TOV1 <= '0';
                                end if;
                        end if;
                        if Int_Acc(3) = '1' then
                                ICF1 <= '0';
                        end if;
                        if Int_Acc(4) = '1' then
                                OCF1 <= '0';
                        end if;
                        if Int_Acc(5) = '1' then
                                TOV1 <= '0';
                        end if;
                        if Int_Acc(6) = '1' then
                                TOV0 <= '0';
                        end if;
                        if TC_Trig = '1' then
                                TOV0 <= '1';
                        end if;
                        if IC_Trig = '1' then
                                ICF1 <= '1';
                        end if;
                        if OC_Trig = '1' then
                                OCF1 <= '1';
                        end if;
                        if TO_Trig = '1' then
                                TOV1 <= '1';
                        end if;
                        if Int_Acc(1) = '1' then
                                Int_ET(0) <= '0';
                        end if;
                        if (ISC0 = "10" and Int0_r = "10") or (ISC0 = "11" and Int0_r = "01") then
                                Int_ET(0) <= '1';
                        end if;
                        if Int_Acc(2) = '1' then
                                Int_ET(1) <= '0';
                        end if;
                        if (ISC1 = "10" and Int1_r = "10") or (ISC1 = "11" and Int1_r = "01") then
                                Int_ET(1) <= '1';
                        end if;
                end if;
        end process;
 
        Int_Trig(1) <= '0' when Int_En(0) = '0' else not Int0_r(1) when ISC0 = "00" else Int_ET(0);
        Int_Trig(2) <= '0' when Int_En(1) = '0' else not Int1_r(1) when ISC1 = "00" else Int_ET(1);
        Int_Trig(3) <= '1' when TICIE1 = '1' and ICF1 = '1' else '0';
        Int_Trig(4) <= '1' when OCIE1 = '1' and OCF1 = '1' else '0';
        Int_Trig(5) <= '1' when TOIE1 = '1' and TOV1 = '1' else '0';
        Int_Trig(6) <= '1' when TOIE0 = '1' and TOV0 = '1' else '0';
        Int_Trig(15 downto 10) <= (others => '0');
 
        rom : ROM2313 port map(
                        Clk => Clk,
                        A => ROM_Addr,
                        D => ROM_Data);
 
        ax : AX8
                generic map(
                        ROMAddressWidth => ROMAddressWidth,
                        RAMAddressWidth => RAMAddressWidth,
                        BigIset => BigIset)
                port map(
                        Clk => Clk,
                        Reset_n => Reset_s_n,
                        ROM_Addr => ROM_Addr,
                        ROM_Data => ROM_Data,
                        Sleep_En => Sleep_En,
                        Int_Trig => Int_Trig,
                        Int_Acc => Int_Acc,
                        SREG => SREG,
                        SP => SP,
                        IO_Rd => IO_Rd,
                        IO_Wr => IO_Wr,
                        IO_Addr => IO_Addr,
                        IO_RData => IO_RData,
                        IO_WData => IO_WData);
 
        TCCR0_Sel <= '1' when IO_Addr = "110011" else '0';       -- $33 TCCR0
        TCNT0_Sel <= '1' when IO_Addr = "110010" else '0';       -- $32 TCNT0
        tc0 : AX_TC8 port map(
                        Clk => Clk,
                        Reset_n => Reset_s_n,
                        T => T0,
                        TCCR_Sel => TCCR0_Sel,
                        TCNT_Sel => TCNT0_Sel,
                        Wr => IO_Wr,
                        Data_In => IO_WData,
                        TCCR => TCCR0,
                        TCNT => TCNT0,
                        Int  => TC_Trig);
 
        TCCR1_Sel <= '1' when IO_Addr(5 downto 1) = "10111" else '0';    -- $2E TCCR1
        TCNT1_Sel <= '1' when IO_Addr(5 downto 1) = "10110" else '0';    -- $2C TCNT1
        OCR1_Sel <= '1' when IO_Addr(5 downto 1) = "10101" else '0';     -- $2A OCR1
        ICR1_Sel <= '1' when IO_Addr(5 downto 1) = "10100" else '0';     -- $24 ICR1
        tc1 : AX_TC16 port map(
                        Clk => Clk,
                        Reset_n => Reset_s_n,
                        T => T1,
                        ICP => ICP,
                        TCCR_Sel => TCCR1_Sel,
                        TCNT_Sel => TCNT1_Sel,
                        OCR_Sel => OCR1_Sel,
                        ICR_Sel => ICR1_Sel,
                        A0 => IO_Addr(0),
                        Rd => IO_Rd,
                        Wr => IO_Wr,
                        Data_In => IO_WData,
                        COM => COM,
                        PWM => PWM,
                        CRBH => CRBH,
                        CRBL => CRBL,
                        TCNT => TCNT1,
                        IC => IC,
                        OCR => OCR,
                        Tmp => Tmp,
                        OC => OC,
                        Int_TO => TO_Trig,
                        Int_OC => OC_Trig,
                        Int_IC => IC_Trig);
 
        UDR_Sel <= '1' when IO_Addr = "001100" else '0';
        USR_Sel <= '1' when IO_Addr = "001011" else '0';
        UCR_Sel <= '1' when IO_Addr = "001010" else '0';
        UBRR_Sel <= '1' when IO_Addr = "001001" else '0';
        uart : AX_UART port map(
                        Clk => Clk,
                        Reset_n => Reset_s_n,
                        UDR_Sel => UDR_Sel,
                        USR_Sel => USR_Sel,
                        UCR_Sel => UCR_Sel,
                        UBRR_Sel => UBRR_Sel,
                        Rd => IO_Rd,
                        Wr => IO_Wr,
                        TXC_Clr => Int_Acc(9),
                        Data_In => IO_WData,
                        UDR => UDR,
                        USR => USR,
                        UCR => UCR,
                        UBRR => UBRR,
                        RXD => RXD,
                        TXD => TXD,
                        Int_RX => Int_Trig(7),
                        Int_TR => Int_Trig(8),
                        Int_TC => Int_Trig(9));
 
        PINB_Sel <= '1' when IO_Addr = "010101" else '0';
        DDRB_Sel <= '1' when IO_Addr = "010111" else '0';
        PORTB_Sel <= '1' when IO_Addr = "011000" else '0';
        PIND_Sel <= '1' when IO_Addr = "010000" else '0';
        DDRD_Sel <= '1' when IO_Addr = "010001" else '0';
        PORTD_Sel <= '1' when IO_Addr = "010010" else '0';
        portb : AX_Port port map(
                        Clk => Clk,
                        Reset_n => Reset_s_n,
                        PORT_Sel => PORTB_Sel,
                        DDR_Sel => DDRB_Sel,
                        PIN_Sel => PINB_Sel,
                        Wr => IO_Wr,
                        Data_In => IO_WData,
                        Dir => DirB,
                        Port_Input => Port_InB,
                        Port_Output => Port_OutB,
                        IOPort  => Port_B);
        portd : AX_Port port map(
                        Clk => Clk,
                        Reset_n => Reset_s_n,
                        PORT_Sel => PORTD_Sel,
                        DDR_Sel => DDRD_Sel,
                        PIN_Sel => PIND_Sel,
                        Wr => IO_Wr,
                        Data_In => IO_WData,
                        Dir => DirD,
                        Port_Input => Port_InD,
                        Port_Output => Port_OutD,
                        IOPort  => Port_D);
 
        gNoTri : if not TriState generate
                with IO_Addr select
                        IO_RData <= SREG when "111111",
                                SP(7 downto 0) when "111101",
                                SP(15 downto 8) when "111110",
                                "00" & Sleep_En & "0" & ISC1 & ISC0 when "110101",
                                Int_En & "000000" when "111011",
                                TOIE1 & OCIE1 & "00" & TICIE1 & "0" & TOIE0 & "0" when "111001",
                                TOV1 & OCF1 & "00" & ICF1 & "0" & TOV0 & "0" when "111000",
                                UDR when "001100",
                                USR & "000" when "001011",
                                UCR(7 downto 1) & "0" when "001010",
                                UBRR when "001001",
                                "00000" & TCCR0 when "110011",
                                TCNT0 when "110010",
                                COM & "0000" & PWM when "101111",
                                CRBH & "00" & CRBL when "101110",
                                TCNT1(7 downto 0) when "101100",
                                OCR(7 downto 0) when "101010",
                                IC(7 downto 0) when "101000",
                                Tmp(15 downto 8) when "101101" | "101001" | "101011",
                                Port_InB when "010101",
                                DirB when "010111",
                                Port_OutB when "011000",
                                Port_InD when "010000",
                                DirD when "010001",
                                Port_OutD when "010010",
                                "--------" when others;
        end generate;
        gTri : if TriState generate
                IO_RData <= SREG when IO_Addr = "111111" else "ZZZZZZZZ";
                IO_RData <= SP(7 downto 0) when IO_Addr = "111101" and BigIset else "ZZZZZZZZ";
                IO_RData <= SP(15 downto 8) when IO_Addr = "111110" and BigIset else "ZZZZZZZZ";
 
                IO_RData <= "00" & Sleep_En & "0" & ISC1 & ISC0 when IO_Addr = "110101" else "ZZZZZZZZ";
                IO_RData <= Int_En & "000000" when IO_Rd = '1' and IO_Addr = "111011" else "ZZZZZZZZ";
                IO_RData <= TOIE1 & OCIE1 & "00" & TICIE1 & "0" & TOIE0 & "0" when IO_Addr = "111001" else "ZZZZZZZZ";
                IO_RData <= TOV1 & OCF1 & "00" & ICF1 & "0" & TOV0 & "0" when IO_Addr = "111000" else "ZZZZZZZZ";
 
                IO_RData <= UDR when UDR_Sel = '1' else "ZZZZZZZZ";
                IO_RData <= USR & "000" when USR_Sel = '1' else "ZZZZZZZZ";
                IO_RData <= UCR(7 downto 1) & "0" when UCR_Sel = '1' else "ZZZZZZZZ";
                IO_RData <= UBRR when UBRR_Sel = '1' else "ZZZZZZZZ";
 
                IO_RData <= "00000" & TCCR0 when TCCR0_Sel = '1' else "ZZZZZZZZ";
                IO_RData <= TCNT0 when TCNT0_Sel = '1' else "ZZZZZZZZ";
 
                IO_RData <= COM & "0000" & PWM when TCCR1_Sel = '1' and IO_Addr(0) = '1' else "ZZZZZZZZ";
                IO_RData <= CRBH & "00" & CRBL when TCCR1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";
                IO_RData <= TCNT1(7 downto 0) when TCNT1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";
                IO_RData <= OCR(7 downto 0) when OCR1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";
                IO_RData <= IC(7 downto 0) when ICR1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";
                IO_RData <= Tmp(15 downto 8) when (TCNT1_Sel = '1' or ICR1_Sel = '1' or OCR1_Sel = '1') and IO_Addr(0) = '1' else "ZZZZZZZZ";
 
                IO_RData <= Port_InB when PINB_Sel = '1' else "ZZZZZZZZ";
                IO_RData <= DirB when DDRB_Sel = '1' else "ZZZZZZZZ";
                IO_RData <= Port_OutB when PORTB_Sel = '1' else "ZZZZZZZZ";
 
                IO_RData <= Port_InD when PIND_Sel = '1' else "ZZZZZZZZ";
                IO_RData <= DirD when DDRD_Sel = '1' else "ZZZZZZZZ";
                IO_RData <= Port_OutD when PORTD_Sel = '1' else "ZZZZZZZZ";
        end generate;
 
end;

Line No.	Rev	Author	Line
1	5	jesus	`--`
2			`-- 90S2313 compatible microcontroller core`
3			`--`
4	25	jesus	`-- Version : 0224`
5	5	jesus	`--`
6			`-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)`
7			`--`
8			`-- All rights reserved`
9			`--`
10			`-- Redistribution and use in source and synthezised forms, with or without`
11			`-- modification, are permitted provided that the following conditions are met:`
12			`--`
13			`-- Redistributions of source code must retain the above copyright notice,`
14			`-- this list of conditions and the following disclaimer.`
15			`--`
16			`-- Redistributions in synthesized form must reproduce the above copyright`
17			`-- notice, this list of conditions and the following disclaimer in the`
18			`-- documentation and/or other materials provided with the distribution.`
19			`--`
20			`-- Neither the name of the author nor the names of other contributors may`
21			`-- be used to endorse or promote products derived from this software without`
22			`-- specific prior written permission.`
23			`--`
24			`-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
25			`-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
26			`-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
27			`-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE`
28			`-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR`
29			`-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF`
30			`-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS`
31			`-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN`
32			`-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)`
33			`-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE`
34			`-- POSSIBILITY OF SUCH DAMAGE.`
35			`--`
36			`-- Please report bugs to the author, but before you do so, please`
37			`-- make sure that this is not a derivative work and that`
38			`-- you have the latest version of this file.`
39			`--`
40			`-- The latest version of this file can be found at:`
41	25	jesus	`-- http://www.opencores.org/cvsweb.shtml/ax8/`
42	5	jesus	`--`
43			`-- Limitations :`
44			`--`
45			`-- File history :`
46			`--`
47	13	jesus	`-- 0146 : First release`
48			`-- 0220 : Changed to synchronous ROM`
49			`-- 0220b : Changed reset`
50	24	jesus	`-- 0221 : Changed to configurable buses`
51	25	jesus	`-- 0224 : Fixed timer interrupt enables`
52	5	jesus
53			`--Registers: Comments:`
54			`--$3F SREG Status Register Implemented in the AX8 core`
55			`--$3D SPL Stack Pointer Low Implemented in the AX8 core`
56			`--$3B GIMSK General Interrupt Mask register`
57			`--$3A GIFR General Interrupt Flag Register`
58			`--$39 TIMSK Timer/Counter Interrupt Mask register`
59			`--$38 TIFR Timer/Counter Interrupt Flag register`
60			`--$35 MCUCR MCU General Control Register No power down`
61			`--$33 TCCR0 Timer/Counter 0 Control Register`
62			`--$32 TCNT0 Timer/Counter 0 (8-bit)`
63			`--$2F TCCR1A Timer/Counter 1 Control Register A`
64			`--$2E TCCR1B Timer/Counter 1 Control Register B`
65			`--$2D TCNT1H Timer/Counter 1 High Byte`
66			`--$2C TCNT1L Timer/Counter 1 Low Byte`
67			`--$2B OCR1AH Output Compare Register 1 High Byte`
68			`--$2A OCR1AL Output Compare Register 1 Low Byte`
69			`--$25 ICR1H T/C 1 Input Capture Register High Byte`
70			`--$24 ICR1L T/C 1 Input Capture Register Low Byte`
71			`--$21 WDTCR Watchdog Timer Control Register Not implemented`
72			`--$1E EEAR EEPROM Address Register Not implemented`
73			`--$1D EEDR EEPROM Data Register Not implemented`
74			`--$1C EECR EEPROM Control Register Not implemented`
75			`--$18 PORTB Data Register, Port B No pullup`
76			`--$17 DDRB Data Direction Register, Port B`
77			`--$16 PINB Input Pins, Port B`
78			`--$12 PORTD Data Register, Port D No pullup`
79			`--$11 DDRD Data Direction Register, Port D`
80			`--$10 PIND Input Pins, Port D`
81			`--$0C UDR UART I/O Data Register`
82			`--$0B USR UART Status Register`
83			`--$0A UCR UART Control Register`
84			`--$09 UBRR UART Baud Rate Register`
85			`--$08 ACSR Analog Comparator Control and Status Register Not implemented`
86
87			`library IEEE;`
88			`use IEEE.std_logic_1164.all;`
89			`use work.AX_Pack.all;`
90
91			`entity A90S2313 is`
92			`generic(`
93	24	jesus	`SyncReset : boolean := true;`
94			`TriState : boolean := false`
95	5	jesus	`);`
96			`port(`
97			`Clk : in std_logic;`
98			`Reset_n : in std_logic;`
99			`INT0 : in std_logic;`
100			`INT1 : in std_logic;`
101			`T0 : in std_logic;`
102			`T1 : in std_logic;`
103			`ICP : in std_logic;`
104			`RXD : in std_logic;`
105			`TXD : out std_logic;`
106			`OC : out std_logic;`
107			`Port_B : inout std_logic_vector(7 downto 0);`
108			`Port_D : inout std_logic_vector(7 downto 0)`
109			`);`
110			`end A90S2313;`
111
112			`architecture rtl of A90S2313 is`
113
114			`constant ROMAddressWidth : integer := 10;`
115			`constant RAMAddressWidth : integer := 7;`
116			`constant BigISet : boolean := true;`
117
118			`component ROM2313`
119			`port(`
120			`Clk : in std_logic;`
121			`A : in std_logic_vector(ROMAddressWidth - 1 downto 0);`
122			`D : out std_logic_vector(15 downto 0)`
123			`);`
124			`end component;`
125
126			`signal Reset_s_n : std_logic;`
127			`signal ROM_Addr : std_logic_vector(ROMAddressWidth - 1 downto 0);`
128			`signal ROM_Data : std_logic_vector(15 downto 0);`
129	24	jesus	`signal SREG : std_logic_vector(7 downto 0);`
130			`signal SP : std_logic_vector(15 downto 0);`
131	5	jesus	`signal IO_Rd : std_logic;`
132			`signal IO_Wr : std_logic;`
133			`signal IO_Addr : std_logic_vector(5 downto 0);`
134			`signal IO_WData : std_logic_vector(7 downto 0);`
135			`signal IO_RData : std_logic_vector(7 downto 0);`
136			`signal TCCR0_Sel : std_logic;`
137			`signal TCNT0_Sel : std_logic;`
138			`signal TCCR1_Sel : std_logic;`
139			`signal TCNT1_Sel : std_logic;`
140			`signal OCR1_Sel : std_logic;`
141			`signal ICR1_Sel : std_logic;`
142			`signal UDR_Sel : std_logic;`
143			`signal USR_Sel : std_logic;`
144			`signal UCR_Sel : std_logic;`
145			`signal UBRR_Sel : std_logic;`
146			`signal PORTB_Sel : std_logic;`
147			`signal DDRB_Sel : std_logic;`
148			`signal PINB_Sel : std_logic;`
149			`signal PORTD_Sel : std_logic;`
150			`signal DDRD_Sel : std_logic;`
151			`signal PIND_Sel : std_logic;`
152			`signal Sleep_En : std_logic;`
153			`signal ISC0 : std_logic_vector(1 downto 0);`
154			`signal ISC1 : std_logic_vector(1 downto 0);`
155			`signal Int_ET : std_logic_vector(1 downto 0);`
156			`signal Int_En : std_logic_vector(1 downto 0);`
157			`signal Int0_r : std_logic_vector(1 downto 0);`
158			`signal Int1_r : std_logic_vector(1 downto 0);`
159			`signal TC_Trig : std_logic;`
160			`signal TO_Trig : std_logic;`
161			`signal OC_Trig : std_logic;`
162			`signal IC_Trig : std_logic;`
163			`signal TOIE0 : std_logic;`
164			`signal TICIE1 : std_logic;`
165			`signal OCIE1 : std_logic;`
166			`signal TOIE1 : std_logic;`
167			`signal TOV0 : std_logic;`
168			`signal ICF1 : std_logic;`
169			`signal OCF1 : std_logic;`
170			`signal TOV1 : std_logic;`
171			`signal Int_Trig : std_logic_vector(15 downto 1);`
172			`signal Int_Acc : std_logic_vector(15 downto 1);`
173	24	jesus	`signal TCCR0 : std_logic_vector(2 downto 0);`
174			`signal TCNT0 : std_logic_vector(7 downto 0);`
175			`signal COM : std_logic_vector(1 downto 0);`
176			`signal PWM : std_logic_vector(1 downto 0);`
177			`signal CRBH : std_logic_vector(1 downto 0);`
178			`signal CRBL : std_logic_vector(3 downto 0);`
179			`signal TCNT1 : std_logic_vector(15 downto 0);`
180			`signal IC : std_logic_vector(15 downto 0);`
181			`signal OCR : std_logic_vector(15 downto 0);`
182			`signal Tmp : std_logic_vector(15 downto 0);`
183			`signal UDR : std_logic_vector(7 downto 0);`
184			`signal USR : std_logic_vector(7 downto 3);`
185			`signal UCR : std_logic_vector(7 downto 0);`
186			`signal UBRR : std_logic_vector(7 downto 0);`
187			`signal DirB : std_logic_vector(7 downto 0);`
188			`signal Port_InB : std_logic_vector(7 downto 0);`
189			`signal Port_OutB : std_logic_vector(7 downto 0);`
190			`signal DirD : std_logic_vector(7 downto 0);`
191			`signal Port_InD : std_logic_vector(7 downto 0);`
192			`signal Port_OutD : std_logic_vector(7 downto 0);`
193	5	jesus
194			`begin`
195
196			`-- Synchronise reset`
197			`process (Reset_n, Clk)`
198			`variable Reset_v : std_logic;`
199			`begin`
200			`if Reset_n = '0' then`
201			`if SyncReset then`
202			`Reset_s_n <= '0';`
203			`Reset_v := '0';`
204			`end if;`
205			`elsif Clk'event and Clk = '1' then`
206			`if SyncReset then`
207			`Reset_s_n <= Reset_v;`
208			`Reset_v := '1';`
209			`end if;`
210			`end if;`
211			`end process;`
212
213			`g_reset : if not SyncReset generate`
214			`Reset_s_n <= Reset_n;`
215			`end generate;`
216
217			`-- Registers/Interrupts`
218			`process (Reset_s_n, Clk)`
219			`begin`
220			`if Reset_s_n = '0' then`
221			`Sleep_En <= '0';`
222			`ISC0 <= "00";`
223			`ISC1 <= "00";`
224			`Int_ET <= "00";`
225			`Int_En <= "00";`
226			`Int0_r <= "11";`
227			`Int1_r <= "11";`
228			`TOIE0 <= '0';`
229			`TICIE1 <= '0';`
230			`OCIE1 <= '0';`
231			`TOIE1 <= '0';`
232			`TOV0 <= '0';`
233			`ICF1 <= '0';`
234			`OCF1 <= '0';`
235			`TOV1 <= '0';`
236			`elsif Clk'event and Clk = '1' then`
237			`Int0_r(0) <= INT0;`
238			`Int0_r(1) <= Int0_r(0);`
239			`Int1_r(0) <= INT1;`
240			`Int1_r(1) <= Int1_r(0);`
241			`if IO_Wr = '1' and IO_Addr = "110101" then -- $35 MCUCR`
242			`Sleep_En <= IO_WData(5);`
243			`ISC0 <= IO_WData(1 downto 0);`
244			`ISC1 <= IO_WData(3 downto 2);`
245			`end if;`
246			`if IO_Wr = '1' and IO_Addr = "111011" then -- $3B GIMSK`
247			`Int_En <= IO_WData(7 downto 6);`
248			`end if;`
249			`if IO_Wr = '1' and IO_Addr = "111001" then -- $39 TIMSK`
250			`TOIE0 <= IO_WData(1);`
251			`TICIE1 <= IO_WData(3);`
252			`OCIE1 <= IO_WData(6);`
253			`TOIE1 <= IO_WData(7);`
254			`end if;`
255			`if IO_Wr = '1' and IO_Addr = "111000" then -- $38 TIFR`
256			`if IO_WData(1) = '1' then`
257			`TOV0 <= '0';`
258			`end if;`
259			`if IO_WData(3) = '1' then`
260			`ICF1 <= '0';`
261			`end if;`
262			`if IO_WData(6) = '1' then`
263			`OCF1 <= '0';`
264			`end if;`
265			`if IO_WData(7) = '1' then`
266			`TOV1 <= '0';`
267			`end if;`
268			`end if;`
269			`if Int_Acc(3) = '1' then`
270			`ICF1 <= '0';`
271			`end if;`
272			`if Int_Acc(4) = '1' then`
273			`OCF1 <= '0';`
274			`end if;`
275			`if Int_Acc(5) = '1' then`
276			`TOV1 <= '0';`
277			`end if;`
278			`if Int_Acc(6) = '1' then`
279			`TOV0 <= '0';`
280			`end if;`
281			`if TC_Trig = '1' then`
282			`TOV0 <= '1';`
283			`end if;`
284			`if IC_Trig = '1' then`
285			`ICF1 <= '1';`
286			`end if;`
287			`if OC_Trig = '1' then`
288			`OCF1 <= '1';`
289			`end if;`
290			`if TO_Trig = '1' then`
291			`TOV1 <= '1';`
292			`end if;`
293			`if Int_Acc(1) = '1' then`
294			`Int_ET(0) <= '0';`
295			`end if;`
296			`if (ISC0 = "10" and Int0_r = "10") or (ISC0 = "11" and Int0_r = "01") then`
297			`Int_ET(0) <= '1';`
298			`end if;`
299			`if Int_Acc(2) = '1' then`
300			`Int_ET(1) <= '0';`
301			`end if;`
302			`if (ISC1 = "10" and Int1_r = "10") or (ISC1 = "11" and Int1_r = "01") then`
303			`Int_ET(1) <= '1';`
304			`end if;`
305			`end if;`
306			`end process;`
307
308			`Int_Trig(1) <= '0' when Int_En(0) = '0' else not Int0_r(1) when ISC0 = "00" else Int_ET(0);`
309			`Int_Trig(2) <= '0' when Int_En(1) = '0' else not Int1_r(1) when ISC1 = "00" else Int_ET(1);`
310	25	jesus	`Int_Trig(3) <= '1' when TICIE1 = '1' and ICF1 = '1' else '0';`
311			`Int_Trig(4) <= '1' when OCIE1 = '1' and OCF1 = '1' else '0';`
312			`Int_Trig(5) <= '1' when TOIE1 = '1' and TOV1 = '1' else '0';`
313			`Int_Trig(6) <= '1' when TOIE0 = '1' and TOV0 = '1' else '0';`
314	5	jesus	`Int_Trig(15 downto 10) <= (others => '0');`
315
316			`rom : ROM2313 port map(`
317			`Clk => Clk,`
318			`A => ROM_Addr,`
319			`D => ROM_Data);`
320
321			`ax : AX8`
322			`generic map(`
323			`ROMAddressWidth => ROMAddressWidth,`
324			`RAMAddressWidth => RAMAddressWidth,`
325			`BigIset => BigIset)`
326			`port map(`
327			`Clk => Clk,`
328			`Reset_n => Reset_s_n,`
329			`ROM_Addr => ROM_Addr,`
330			`ROM_Data => ROM_Data,`
331			`Sleep_En => Sleep_En,`
332			`Int_Trig => Int_Trig,`
333			`Int_Acc => Int_Acc,`
334	24	jesus	`SREG => SREG,`
335			`SP => SP,`
336	5	jesus	`IO_Rd => IO_Rd,`
337			`IO_Wr => IO_Wr,`
338			`IO_Addr => IO_Addr,`
339	24	jesus	`IO_RData => IO_RData,`
340			`IO_WData => IO_WData);`
341	5	jesus
342			`TCCR0_Sel <= '1' when IO_Addr = "110011" else '0'; -- $33 TCCR0`
343			`TCNT0_Sel <= '1' when IO_Addr = "110010" else '0'; -- $32 TCNT0`
344			`tc0 : AX_TC8 port map(`
345			`Clk => Clk,`
346			`Reset_n => Reset_s_n,`
347			`T => T0,`
348			`TCCR_Sel => TCCR0_Sel,`
349			`TCNT_Sel => TCNT0_Sel,`
350			`Wr => IO_Wr,`
351			`Data_In => IO_WData,`
352	24	jesus	`TCCR => TCCR0,`
353			`TCNT => TCNT0,`
354	5	jesus	`Int => TC_Trig);`
355
356			`TCCR1_Sel <= '1' when IO_Addr(5 downto 1) = "10111" else '0'; -- $2E TCCR1`
357			`TCNT1_Sel <= '1' when IO_Addr(5 downto 1) = "10110" else '0'; -- $2C TCNT1`
358			`OCR1_Sel <= '1' when IO_Addr(5 downto 1) = "10101" else '0'; -- $2A OCR1`
359			`ICR1_Sel <= '1' when IO_Addr(5 downto 1) = "10100" else '0'; -- $24 ICR1`
360			`tc1 : AX_TC16 port map(`
361			`Clk => Clk,`
362			`Reset_n => Reset_s_n,`
363			`T => T1,`
364			`ICP => ICP,`
365			`TCCR_Sel => TCCR1_Sel,`
366			`TCNT_Sel => TCNT1_Sel,`
367			`OCR_Sel => OCR1_Sel,`
368			`ICR_Sel => ICR1_Sel,`
369			`A0 => IO_Addr(0),`
370			`Rd => IO_Rd,`
371			`Wr => IO_Wr,`
372			`Data_In => IO_WData,`
373	24	jesus	`COM => COM,`
374			`PWM => PWM,`
375			`CRBH => CRBH,`
376			`CRBL => CRBL,`
377			`TCNT => TCNT1,`
378			`IC => IC,`
379			`OCR => OCR,`
380			`Tmp => Tmp,`
381	5	jesus	`OC => OC,`
382			`Int_TO => TO_Trig,`
383			`Int_OC => OC_Trig,`
384			`Int_IC => IC_Trig);`
385
386			`UDR_Sel <= '1' when IO_Addr = "001100" else '0';`
387			`USR_Sel <= '1' when IO_Addr = "001011" else '0';`
388			`UCR_Sel <= '1' when IO_Addr = "001010" else '0';`
389			`UBRR_Sel <= '1' when IO_Addr = "001001" else '0';`
390			`uart : AX_UART port map(`
391			`Clk => Clk,`
392			`Reset_n => Reset_s_n,`
393			`UDR_Sel => UDR_Sel,`
394			`USR_Sel => USR_Sel,`
395			`UCR_Sel => UCR_Sel,`
396			`UBRR_Sel => UBRR_Sel,`
397			`Rd => IO_Rd,`
398			`Wr => IO_Wr,`
399			`TXC_Clr => Int_Acc(9),`
400			`Data_In => IO_WData,`
401	24	jesus	`UDR => UDR,`
402			`USR => USR,`
403			`UCR => UCR,`
404			`UBRR => UBRR,`
405	5	jesus	`RXD => RXD,`
406			`TXD => TXD,`
407			`Int_RX => Int_Trig(7),`
408			`Int_TR => Int_Trig(8),`
409			`Int_TC => Int_Trig(9));`
410
411			`PINB_Sel <= '1' when IO_Addr = "010101" else '0';`
412			`DDRB_Sel <= '1' when IO_Addr = "010111" else '0';`
413			`PORTB_Sel <= '1' when IO_Addr = "011000" else '0';`
414			`PIND_Sel <= '1' when IO_Addr = "010000" else '0';`
415			`DDRD_Sel <= '1' when IO_Addr = "010001" else '0';`
416			`PORTD_Sel <= '1' when IO_Addr = "010010" else '0';`
417	24	jesus	`portb : AX_Port port map(`
418	5	jesus	`Clk => Clk,`
419			`Reset_n => Reset_s_n,`
420			`PORT_Sel => PORTB_Sel,`
421			`DDR_Sel => DDRB_Sel,`
422			`PIN_Sel => PINB_Sel,`
423			`Wr => IO_Wr,`
424			`Data_In => IO_WData,`
425	24	jesus	`Dir => DirB,`
426			`Port_Input => Port_InB,`
427			`Port_Output => Port_OutB,`
428	5	jesus	`IOPort => Port_B);`
429	24	jesus	`portd : AX_Port port map(`
430	5	jesus	`Clk => Clk,`
431			`Reset_n => Reset_s_n,`
432			`PORT_Sel => PORTD_Sel,`
433			`DDR_Sel => DDRD_Sel,`
434			`PIN_Sel => PIND_Sel,`
435			`Wr => IO_Wr,`
436			`Data_In => IO_WData,`
437	24	jesus	`Dir => DirD,`
438			`Port_Input => Port_InD,`
439			`Port_Output => Port_OutD,`
440	5	jesus	`IOPort => Port_D);`
441
442	24	jesus	`gNoTri : if not TriState generate`
443			`with IO_Addr select`
444			`IO_RData <= SREG when "111111",`
445			`SP(7 downto 0) when "111101",`
446			`SP(15 downto 8) when "111110",`
447			`"00" & Sleep_En & "0" & ISC1 & ISC0 when "110101",`
448			`Int_En & "000000" when "111011",`
449			`TOIE1 & OCIE1 & "00" & TICIE1 & "0" & TOIE0 & "0" when "111001",`
450			`TOV1 & OCF1 & "00" & ICF1 & "0" & TOV0 & "0" when "111000",`
451			`UDR when "001100",`
452			`USR & "000" when "001011",`
453			`UCR(7 downto 1) & "0" when "001010",`
454			`UBRR when "001001",`
455			`"00000" & TCCR0 when "110011",`
456			`TCNT0 when "110010",`
457			`COM & "0000" & PWM when "101111",`
458			`CRBH & "00" & CRBL when "101110",`
459			`TCNT1(7 downto 0) when "101100",`
460			`OCR(7 downto 0) when "101010",`
461			`IC(7 downto 0) when "101000",`
462			`Tmp(15 downto 8) when "101101" \| "101001" \| "101011",`
463			`Port_InB when "010101",`
464			`DirB when "010111",`
465			`Port_OutB when "011000",`
466			`Port_InD when "010000",`
467			`DirD when "010001",`
468			`Port_OutD when "010010",`
469			`"--------" when others;`
470			`end generate;`
471			`gTri : if TriState generate`
472			`IO_RData <= SREG when IO_Addr = "111111" else "ZZZZZZZZ";`
473			`IO_RData <= SP(7 downto 0) when IO_Addr = "111101" and BigIset else "ZZZZZZZZ";`
474			`IO_RData <= SP(15 downto 8) when IO_Addr = "111110" and BigIset else "ZZZZZZZZ";`
475
476			`IO_RData <= "00" & Sleep_En & "0" & ISC1 & ISC0 when IO_Addr = "110101" else "ZZZZZZZZ";`
477			`IO_RData <= Int_En & "000000" when IO_Rd = '1' and IO_Addr = "111011" else "ZZZZZZZZ";`
478			`IO_RData <= TOIE1 & OCIE1 & "00" & TICIE1 & "0" & TOIE0 & "0" when IO_Addr = "111001" else "ZZZZZZZZ";`
479			`IO_RData <= TOV1 & OCF1 & "00" & ICF1 & "0" & TOV0 & "0" when IO_Addr = "111000" else "ZZZZZZZZ";`
480
481			`IO_RData <= UDR when UDR_Sel = '1' else "ZZZZZZZZ";`
482			`IO_RData <= USR & "000" when USR_Sel = '1' else "ZZZZZZZZ";`
483			`IO_RData <= UCR(7 downto 1) & "0" when UCR_Sel = '1' else "ZZZZZZZZ";`
484			`IO_RData <= UBRR when UBRR_Sel = '1' else "ZZZZZZZZ";`
485
486			`IO_RData <= "00000" & TCCR0 when TCCR0_Sel = '1' else "ZZZZZZZZ";`
487			`IO_RData <= TCNT0 when TCNT0_Sel = '1' else "ZZZZZZZZ";`
488
489			`IO_RData <= COM & "0000" & PWM when TCCR1_Sel = '1' and IO_Addr(0) = '1' else "ZZZZZZZZ";`
490			`IO_RData <= CRBH & "00" & CRBL when TCCR1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";`
491			`IO_RData <= TCNT1(7 downto 0) when TCNT1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";`
492			`IO_RData <= OCR(7 downto 0) when OCR1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";`
493			`IO_RData <= IC(7 downto 0) when ICR1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";`
494			`IO_RData <= Tmp(15 downto 8) when (TCNT1_Sel = '1' or ICR1_Sel = '1' or OCR1_Sel = '1') and IO_Addr(0) = '1' else "ZZZZZZZZ";`
495
496			`IO_RData <= Port_InB when PINB_Sel = '1' else "ZZZZZZZZ";`
497			`IO_RData <= DirB when DDRB_Sel = '1' else "ZZZZZZZZ";`
498			`IO_RData <= Port_OutB when PORTB_Sel = '1' else "ZZZZZZZZ";`
499
500			`IO_RData <= Port_InD when PIND_Sel = '1' else "ZZZZZZZZ";`

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