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jesus |
--
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-- AT90Sxxxx compatible microcontroller core
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--
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-- Version : 0224
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/ax8/
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--
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-- Limitations :
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-- Four level stack
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--
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-- File history :
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity AX_PCS is
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generic(
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HW_Stack : boolean
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);
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port(
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Clk : in std_logic;
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Reset_n : in std_logic;
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Offs_In : in std_logic_vector(11 downto 0);
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Z : in unsigned(15 downto 0);
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Data_In : in std_logic_vector(7 downto 0);
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Pause : in std_logic;
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Push : in std_logic;
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Pop : in std_logic;
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HRet : in std_logic;
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LRet : in std_logic;
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ZJmp : in std_logic;
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RJmp : in std_logic;
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CInt : in std_logic_vector(3 downto 0);
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IPending : in std_logic;
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IPush : out std_logic;
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NPC : out std_logic_vector(15 downto 0);
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PC : out std_logic_vector(15 downto 0)
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);
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end AX_PCS;
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architecture rtl of AX_PCS is
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signal PC_i : unsigned(15 downto 0);
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signal NPC_i : unsigned(15 downto 0);
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signal IPush_i : std_logic;
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type Stack_Image is array (3 downto 0) of unsigned(15 downto 0);
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signal Stack : Stack_Image;
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signal StackPtr : unsigned(1 downto 0);
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begin
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NPC <= std_logic_vector(NPC_i);
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PC <= std_logic_vector(PC_i);
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IPush <= IPush_i;
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process (PC_i, Pause, IPending, IPush_i, Push, Pop, Stack, Data_In, Offs_In, CInt, HRet, LRet, RJmp, ZJmp, Z)
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begin
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NPC_i <= PC_i;
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if Pause = '0' then
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if IPending = '0' then
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NPC_i <= PC_i + 1;
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end if;
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if IPending = '0' and IPush_i = '1' then
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NPC_i(15 downto 4) <= "000000000000";
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NPC_i(3 downto 0) <= unsigned(CInt);
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end if;
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end if;
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if Pop = '1' and HW_Stack then
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NPC_i <= Stack(to_integer(StackPtr - 1));
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end if;
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if HRet = '1' then
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NPC_i(15 downto 8) <= unsigned(Data_In);
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end if;
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if LRet = '1' then
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NPC_i(7 downto 0) <= unsigned(Data_In);
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end if;
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if ZJmp = '1' then
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NPC_i <= Z;
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end if;
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if RJmp = '1' then
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NPC_i <= PC_i + unsigned(resize(signed(Offs_In), 16));
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end if;
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end process;
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process (Reset_n, Clk)
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begin
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if Reset_n = '0' then
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PC_i <= (others => '0');
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IPush_i <= '0';
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if HW_Stack then
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Stack <= (others => (others => '0'));
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StackPtr <= "00";
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end if;
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elsif Clk'event and Clk = '1' then
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PC_i <= NPC_i;
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if Pause = '0' then
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IPush_i <= IPending;
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if IPending = '0' and IPush_i = '1' then
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if HW_Stack then
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Stack(to_integer(StackPtr)) <= PC_i;
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StackPtr <= StackPtr + 1;
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end if;
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end if;
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end if;
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if Push = '1' and HW_Stack then
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Stack(to_integer(StackPtr)) <= PC_i;
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StackPtr <= StackPtr + 1;
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end if;
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if Pop = '1' and HW_Stack then
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StackPtr <= StackPtr - 1;
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end if;
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end if;
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end process;
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end;
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