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//
// Xilinx VHDL ROM generator
//
// Version : 0244
//
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
//
// All rights reserved
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
//      http://www.opencores.org/cvsweb.shtml/t51/
//
// Limitations :
//      Not all address/data widths produce working code
//      Requires stl to compile
//
// File history :
//
// 0220 : Initial release
//
// 0221 : Fixed block ROMs with partial bytes
//
// 0241 : Updated for WebPack 5.1
//
// 0244 : Added -n option and component declaration
//
 
#include <stdio.h>
#include <string>
#include <vector>
#include <iostream>
 
using namespace std;
 
#if !(defined(max)) && _MSC_VER
        // VC fix
        #define max __max
#endif
 
int main (int argc, char *argv[])
{
        cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0244\n";
 
        try
        {
                unsigned long aWidth;
                unsigned long dWidth;
                unsigned long select = 0;
                unsigned long length = 0;
                char z = 0;
 
                if (argc < 4)
                {
                        cerr << "\nUsage: xrom <entity name> <address bits> <data bits> <options>\n";
                        cerr << "\nThe options can be:\n";
                        cerr << "  -[decimal number] = SelectRAM usage in 1/16 parts\n";
                        cerr << "  -z = use tri-state buses\n";
                        cerr << "  -n [decimal size] = limit rom size\n";
                        cerr << "\nExample:\n";
                        cerr << "  xrom Test_ROM 13 8 -6\n\n";
                        return -1;
                }
 
                int result;
 
                result = sscanf(argv[2], "%lu", &aWidth);
                if (result < 1)
                {
                        throw "Error in address bits argument!\n";
                }
 
                result = sscanf(argv[3], "%lu", &dWidth);
                if (result < 1)
                {
                        throw "Error in data bits argument!\n";
                }
 
                int argument = 4;
 
                while (argument < argc)
                {
                        char tmpC = 0;
                        unsigned long tmpL = 0;
 
                        result = sscanf(argv[argument], "%c%lu", &tmpC, &tmpL);
                        if (result < 1 || tmpC != '-' )
                        {
                                throw "Error in options!\n";
                        }
 
                        if (result < 2)
                        {
                                sscanf(argv[argument], "%c%c", &tmpC, &tmpC);
                                if (tmpC != 'z' && tmpC != 'n')
                                {
                                        throw "Unkown option!\n";
                                }
                                if (tmpC == 'z')
                                {
                                        z = tmpC;
                                }
                                else
                                {
                                        argument++;
 
                                        if (argument == argc)
                                        {
                                                throw "No memory size argument!\n";
                                        }
 
                                        result = sscanf(argv[argument], "%lu", &tmpL);
                                        if (!result)
                                        {
                                                throw "Memory size not a number!\n";
                                        }
                                        length = tmpL;
                                }
                        }
                        else
                        {
                                select = tmpL;
                        }
                        argument++;
                }
 
                unsigned long selectIter = 0;
                unsigned long blockIter = 0;
                unsigned long bytes = (dWidth + 7) / 8;
 
                if (!select)
                {
                        blockIter = ((1UL << aWidth) + 511) / 512;
                        if (length && length < blockIter * 512)
                        {
                                blockIter = (length + 511) / 512;
                        }
                }
                else if (select == 16)
                {
                        selectIter = ((1UL << aWidth) + 15) / 16;
                        if (length && length < selectIter * 16)
                        {
                                selectIter = (length + 15) / 16;
                        }
                }
                else
                {
                        blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;
                        selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;
                }
 
                unsigned long blockTotal = ((1UL << aWidth) + 511) / 512;
                if (length && length < blockTotal * 512)
                {
                        blockTotal = (length + 511) / 512;
                }
 
                if (length)
                {
                        if (length > selectIter * 16)
                        {
                                blockIter -= ((1UL << aWidth) + 511) / 512 - blockTotal;
                        }
                        else
                        {
                                blockIter = 0;
                        }
                }
                if (length && !blockIter && length < selectIter * 16)
                {
                        selectIter = (length + 15) / 16;
                }
 
                cerr << "Creating ROM with " << selectIter * bytes;
                cerr << " RAM16X1S and "  << blockIter * bytes << " RAMB4_S8\n";
 
                printf("-- This file was generated with xrom written by Daniel Wallner\n");
                printf("\nlibrary IEEE;");
                printf("\nuse IEEE.std_logic_1164.all;");
                printf("\nuse IEEE.numeric_std.all;");
                printf("\n\nentity %s is", argv[1]);
                printf("\n\tport(");
                printf("\n\t\tClk\t: in std_logic;");
                printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);
                printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);
                printf("\n\t);");
                printf("\nend %s;", argv[1]);
                printf("\n\narchitecture rtl of %s is", argv[1]);
 
                if (selectIter)
                {
                        printf("\n\tcomponent RAM16X1S");
                        printf("\n\t\tport(");
                        printf("\n\t\t\tO    : out std_ulogic;");
                        printf("\n\t\t\tA0   : in std_ulogic;");
                        printf("\n\t\t\tA1   : in std_ulogic;");
                        printf("\n\t\t\tA2   : in std_ulogic;");
                        printf("\n\t\t\tA3   : in std_ulogic;");
                        printf("\n\t\t\tD    : in std_ulogic;");
                        printf("\n\t\t\tWCLK : in std_ulogic;");
                        printf("\n\t\t\tWE   : in std_ulogic);");
                        printf("\n\tend component;\n");
                }
                if (blockIter)
                {
                        printf("\n\tcomponent RAMB4_S8");
                        printf("\n\t\tport(");
                        printf("\n\t\t\tDO     : out std_logic_vector(7 downto 0);");
                        printf("\n\t\t\tADDR   : in std_logic_vector(8 downto 0);");
                        printf("\n\t\t\tCLK    : in std_ulogic;");
                        printf("\n\t\t\tDI     : in std_logic_vector(7 downto 0);");
                        printf("\n\t\t\tEN     : in std_ulogic;");
                        printf("\n\t\t\tRST    : in std_ulogic;");
                        printf("\n\t\t\tWE     : in std_ulogic);");
                        printf("\n\tend component;\n");
                }
 
                if (selectIter > 0)
                {
                        printf("\n\tsignal A_r: unsigned(A'range);");
                }
                if (selectIter > 1)
                {
                        printf("\n\ttype sRAMOut_a is array(0 to %d) of std_logic_vector(D'range);", selectIter - 1);
                        printf("\n\tsignal sRAMOut : sRAMOut_a;");
                        printf("\n\tsignal siA_r : integer;");
                }
                if (selectIter && blockIter)
                {
                        printf("\n\tsignal sD : std_logic_vector(D'range);");
                }
                if (blockIter == 1)
                {
                        printf("\n\tsignal bRAMOut : std_logic_vector(%d downto 0);", bytes * 8 - 1);
                }
                if (blockIter > 1)
                {
                        printf("\n\ttype bRAMOut_a is array(%d to %d) of std_logic_vector(%d downto 0);", blockTotal - blockIter, blockTotal - 1, bytes * 8 - 1);
                        printf("\n\tsignal bRAMOut : bRAMOut_a;");
                        printf("\n\tsignal biA_r : integer;");
                        if (!selectIter)
                        {
                                printf("\n\tsignal A_r : unsigned(A'left downto 9);");
                        }
                }
                if (selectIter && blockIter)
                {
                        printf("\n\tsignal bD : std_logic_vector(D'range);");
                }
 
                printf("\nbegin");
 
                if (selectIter > 0 || blockIter > 1)
                {
                        printf("\n\tprocess (Clk)");
                        printf("\n\tbegin");
                        printf("\n\t\tif Clk'event and Clk = '1' then");
                        if (!selectIter)
                        {
                                printf("\n\t\t\tA_r <= unsigned(A(A'left downto 9));");
                        }
                        else
                        {
                                printf("\n\t\t\tA_r <= unsigned(A);");
                        }
                        printf("\n\t\tend if;");
                        printf("\n\tend process;");
                }
 
                if (selectIter == 1)
                {
                        printf("\n\n\tsG1: for I in 0 to %d generate", dWidth - 1);
                        printf("\n\t\tS%s : RAM16X1S\n\t\t\tport map (", argv[1]);
                        if (blockIter)
                        {
                                printf("s");
                        }
                        printf("WE => '0', WCLK => '0', D => '0', O => D(I), A0 => A_r(0), A1 => A_r(1), A2 => A_r(2), A3 => A_r(3));");
                        printf("\n\tend generate;");
                }
                if (selectIter > 1)
                {
                        printf("\n\n\tsiA_r <= to_integer(A_r(A'left downto 4));");
                        printf("\n\n\tsG1: for I in 0 to %d generate", selectIter - 1);
                        printf("\n\t\tsG2: for J in 0 to %d generate", dWidth - 1);
                        printf("\n\t\t\tS%s : RAM16X1S\n\t\t\t\tport map (WE => '0', WCLK => '0', D => '0', O => sRAMOut(I)(J), A0 => A_r(0), A1 => A_r(1), A2 => A_r(2), A3 => A_r(3));", argv[1]);
                        printf("\n\t\tend generate;");
                        if (z == 'z')
                        {
                                printf("\n\t\t");
                                if (blockIter)
                                {
                                        printf("s");
                                }
                                printf("D <= sRAMOut(I) when siA_r = I else (others => 'Z');");
                        }
                        printf("\n\tend generate;");
                        if (z != 'z')
                        {
                                printf("\n\n\tprocess (siA_r, sRAMOut)\n\tbegin\n\t\t");
                                if (blockIter)
                                {
                                        printf("s");
                                }
                                printf("D <= sRAMOut(0);");
                                printf("\n\t\tfor I in 1 to %d loop", selectIter - 1);
                                printf("\n\t\t\tif siA_r = I then\n\t\t\t\t");
                                if (blockIter)
                                {
                                        printf("s");
                                }
                                printf("D <= sRAMOut(I);\n\t\t\tend if;");
                                printf("\n\t\tend loop;\n\tend process;");
                        }
                }
 
                if (blockIter == 1)
                {
                        printf("\n\n\tbG1: for J in 0 to %d generate", bytes - 1);
                        printf("\n\t\tB%s : RAMB4_S8", argv[1]);
                        printf("\n\t\t\tport map (DI => \"00000000\", EN => '1', RST => '0', WE => '0', CLK => Clk, ADDR => A(8 downto 0), DO => bRAMOut(7 + 8 * J downto 8 * J));", argv[1]);
                        printf("\n\tend generate;");
                        printf("\n\n\t");
                        if (selectIter)
                        {
                                printf("b");
                        }
                        printf("D <= bRAMOut(D'range);");
                }
                if (blockIter > 1)
                {
                        printf("\n\n\tbiA_r <= to_integer(A_r(A'left downto 9));");
                        printf("\n\n\tbG1: for I in %d to %d generate", blockTotal - blockIter, blockTotal - 1);
                        printf("\n\t\tbG2: for J in 0 to %d generate", bytes - 1);
                        printf("\n\t\t\tB%s : RAMB4_S8\n\t\t\t\tport map (DI => \"00000000\", EN => '1', RST => '0', WE => '0', CLK => Clk, ADDR => A(8 downto 0), DO => bRAMOut(I)(7 + 8 * J downto 8 * J));", argv[1]);
                        printf("\n\t\tend generate;");
                        if (z == 'z')
                        {
                                printf("\n\t\t");
                                if (selectIter)
                                {
                                        printf("b");
                                }
                                printf("D <= bRAMOut(I) when biA_r = I else (others => 'Z');");
                        }
                        printf("\n\tend generate;");
                        if (z != 'z')
                        {
                                printf("\n\n\tprocess (biA_r, bRAMOut)\n\tbegin\n\t\t");
                                if (selectIter)
                                {
                                        printf("b");
                                }
                                printf("D <= bRAMOut(%d)(D'range);", blockTotal - blockIter);
                                printf("\n\t\tfor I in %d to %d loop", blockTotal - blockIter + 1, blockTotal - 1);
                                printf("\n\t\t\tif biA_r = I then\n\t\t\t\t");
                                if (selectIter)
                                {
                                        printf("b");
                                }
                                printf("D <= bRAMOut(I)(D'range);\n\t\t\tend if;");
                                printf("\n\t\tend loop;\n\tend process;");
                        }
                }
 
                if (selectIter && blockIter)
                {
                        printf("\n\n\tD <= bD when A_r(A'left downto 9) >= %d else sD;", blockTotal - blockIter);
                }
 
                printf("\nend;\n");
 
                return 0;
        }
        catch (string error)
        {
                cerr << "Fatal: " << error;
        }
        catch (const char *error)
        {
                cerr << "Fatal: " << error;
        }
        return -1;
}

Line No.	Rev	Author	Line
1	14	jesus	`//`
2			`// Xilinx VHDL ROM generator`
3			`//`
4	30	jesus	`// Version : 0244`
5	14	jesus	`//`
6			`// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)`
7			`//`
8			`// All rights reserved`
9			`//`
10			`// Redistribution and use in source and binary forms, with or without`
11			`// modification, are permitted provided that the following conditions are met:`
12			`//`
13			`// Redistributions of source code must retain the above copyright notice,`
14			`// this list of conditions and the following disclaimer.`
15			`//`
16			`// Redistributions in binary form must reproduce the above copyright`
17			`// notice, this list of conditions and the following disclaimer in the`
18			`// documentation and/or other materials provided with the distribution.`
19			`//`
20			`// Neither the name of the author nor the names of other contributors may`
21			`// be used to endorse or promote products derived from this software without`
22			`// specific prior written permission.`
23			`//`
24			`// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
25			`// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
26			`// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
27			`// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE`
28			`// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR`
29			`// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF`
30			`// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS`
31			`// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN`
32			`// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)`
33			`// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE`
34			`// POSSIBILITY OF SUCH DAMAGE.`
35			`//`
36			`// Please report bugs to the author, but before you do so, please`
37			`// make sure that this is not a derivative work and that`
38			`// you have the latest version of this file.`
39			`//`
40			`// The latest version of this file can be found at:`
41			`// http://www.opencores.org/cvsweb.shtml/t51/`
42			`//`
43			`// Limitations :`
44			`// Not all address/data widths produce working code`
45			`// Requires stl to compile`
46			`//`
47			`// File history :`
48			`//`
49			`// 0220 : Initial release`
50			`//`
51	18	jesus	`// 0221 : Fixed block ROMs with partial bytes`
52	27	jesus	`//`
53			`// 0241 : Updated for WebPack 5.1`
54	30	jesus	`//`
55			`// 0244 : Added -n option and component declaration`
56			`//`
57	14	jesus
58			`#include <stdio.h>`
59			`#include <string>`
60			`#include <vector>`
61			`#include <iostream>`
62
63			`using namespace std;`
64
65			`#if !(defined(max)) && _MSC_VER`
66			`// VC fix`
67			`#define max __max`
68			`#endif`
69
70			`int main (int argc, char *argv[])`
71			`{`
72	30	jesus	`cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0244\n";`
73	14	jesus
74			`try`
75			`{`
76			`unsigned long aWidth;`
77			`unsigned long dWidth;`
78			`unsigned long select = 0;`
79	30	jesus	`unsigned long length = 0;`
80	14	jesus	`char z = 0;`
81
82			`if (argc < 4)`
83			`{`
84			`cerr << "\nUsage: xrom <entity name> <address bits> <data bits> <options>\n";`
85			`cerr << "\nThe options can be:\n";`
86	28	jesus	`cerr << " -[decimal number] = SelectRAM usage in 1/16 parts\n";`
87	14	jesus	`cerr << " -z = use tri-state buses\n";`
88	30	jesus	`cerr << " -n [decimal size] = limit rom size\n";`
89	14	jesus	`cerr << "\nExample:\n";`
90			`cerr << " xrom Test_ROM 13 8 -6\n\n";`
91			`return -1;`
92			`}`
93
94			`int result;`
95
96			`result = sscanf(argv[2], "%lu", &aWidth);`
97			`if (result < 1)`
98			`{`
99			`throw "Error in address bits argument!\n";`
100			`}`
101
102			`result = sscanf(argv[3], "%lu", &dWidth);`
103			`if (result < 1)`
104			`{`
105			`throw "Error in data bits argument!\n";`
106			`}`
107
108	30	jesus	`int argument = 4;`
109
110			`while (argument < argc)`
111	14	jesus	`{`
112	30	jesus	`char tmpC = 0;`
113			`unsigned long tmpL = 0;`
114
115			`result = sscanf(argv[argument], "%c%lu", &tmpC, &tmpL);`
116			`if (result < 1 \|\| tmpC != '-' )`
117	14	jesus	`{`
118			`throw "Error in options!\n";`
119			`}`
120	30	jesus
121	14	jesus	`if (result < 2)`
122			`{`
123	30	jesus	`sscanf(argv[argument], "%c%c", &tmpC, &tmpC);`
124			`if (tmpC != 'z' && tmpC != 'n')`
125	14	jesus	`{`
126	30	jesus	`throw "Unkown option!\n";`
127	14	jesus	`}`
128	30	jesus	`if (tmpC == 'z')`
129			`{`
130			`z = tmpC;`
131			`}`
132			`else`
133			`{`
134			`argument++;`
135	14	jesus
136	30	jesus	`if (argument == argc)`
137			`{`
138			`throw "No memory size argument!\n";`
139			`}`
140
141			`result = sscanf(argv[argument], "%lu", &tmpL);`
142			`if (!result)`
143			`{`
144			`throw "Memory size not a number!\n";`
145			`}`
146			`length = tmpL;`
147			`}`
148	14	jesus	`}`
149	30	jesus	`else`
150	14	jesus	`{`
151	30	jesus	`select = tmpL;`
152	14	jesus	`}`
153	30	jesus	`argument++;`
154	14	jesus	`}`
155
156			`unsigned long selectIter = 0;`
157			`unsigned long blockIter = 0;`
158			`unsigned long bytes = (dWidth + 7) / 8;`
159
160			`if (!select)`
161			`{`
162			`blockIter = ((1UL << aWidth) + 511) / 512;`
163	30	jesus	`if (length && length < blockIter * 512)`
164			`{`
165			`blockIter = (length + 511) / 512;`
166			`}`
167	14	jesus	`}`
168			`else if (select == 16)`
169			`{`
170			`selectIter = ((1UL << aWidth) + 15) / 16;`
171	30	jesus	`if (length && length < selectIter * 16)`
172			`{`
173			`selectIter = (length + 15) / 16;`
174			`}`
175	14	jesus	`}`
176			`else`
177			`{`
178			`blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;`
179			`selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;`
180			`}`
181
182			`unsigned long blockTotal = ((1UL << aWidth) + 511) / 512;`
183	30	jesus	`if (length && length < blockTotal * 512)`
184			`{`
185			`blockTotal = (length + 511) / 512;`
186			`}`
187	14	jesus
188	30	jesus	`if (length)`
189			`{`
190			`if (length > selectIter * 16)`
191			`{`
192			`blockIter -= ((1UL << aWidth) + 511) / 512 - blockTotal;`
193			`}`
194			`else`
195			`{`
196			`blockIter = 0;`
197			`}`
198			`}`
199			`if (length && !blockIter && length < selectIter * 16)`
200			`{`
201			`selectIter = (length + 15) / 16;`
202			`}`
203
204			`cerr << "Creating ROM with " << selectIter * bytes;`
205			`cerr << " RAM16X1S and " << blockIter * bytes << " RAMB4_S8\n";`
206
207	14	jesus	`printf("-- This file was generated with xrom written by Daniel Wallner\n");`
208			`printf("\nlibrary IEEE;");`
209			`printf("\nuse IEEE.std_logic_1164.all;");`
210			`printf("\nuse IEEE.numeric_std.all;");`
211			`printf("\n\nentity %s is", argv[1]);`
212			`printf("\n\tport(");`
213			`printf("\n\t\tClk\t: in std_logic;");`
214			`printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);`
215			`printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);`
216			`printf("\n\t);");`
217			`printf("\nend %s;", argv[1]);`
218			`printf("\n\narchitecture rtl of %s is", argv[1]);`
219
220	30	jesus	`if (selectIter)`
221			`{`
222			`printf("\n\tcomponent RAM16X1S");`
223			`printf("\n\t\tport(");`
224			`printf("\n\t\t\tO : out std_ulogic;");`
225			`printf("\n\t\t\tA0 : in std_ulogic;");`
226			`printf("\n\t\t\tA1 : in std_ulogic;");`
227			`printf("\n\t\t\tA2 : in std_ulogic;");`
228			`printf("\n\t\t\tA3 : in std_ulogic;");`
229			`printf("\n\t\t\tD : in std_ulogic;");`
230			`printf("\n\t\t\tWCLK : in std_ulogic;");`
231			`printf("\n\t\t\tWE : in std_ulogic);");`
232			`printf("\n\tend component;\n");`
233			`}`
234			`if (blockIter)`
235			`{`
236			`printf("\n\tcomponent RAMB4_S8");`
237			`printf("\n\t\tport(");`
238			`printf("\n\t\t\tDO : out std_logic_vector(7 downto 0);");`
239			`printf("\n\t\t\tADDR : in std_logic_vector(8 downto 0);");`
240			`printf("\n\t\t\tCLK : in std_ulogic;");`
241			`printf("\n\t\t\tDI : in std_logic_vector(7 downto 0);");`
242			`printf("\n\t\t\tEN : in std_ulogic;");`
243			`printf("\n\t\t\tRST : in std_ulogic;");`
244			`printf("\n\t\t\tWE : in std_ulogic);");`
245			`printf("\n\tend component;\n");`
246			`}`
247
248	14	jesus	`if (selectIter > 0)`
249			`{`
250			`printf("\n\tsignal A_r: unsigned(A'range);");`
251			`}`
252			`if (selectIter > 1)`
253			`{`
254			`printf("\n\ttype sRAMOut_a is array(0 to %d) of std_logic_vector(D'range);", selectIter - 1);`
255			`printf("\n\tsignal sRAMOut : sRAMOut_a;");`
256			`printf("\n\tsignal siA_r : integer;");`
257			`}`
258			`if (selectIter && blockIter)`
259			`{`
260			`printf("\n\tsignal sD : std_logic_vector(D'range);");`
261			`}`
262	18	jesus	`if (blockIter == 1)`
263			`{`
264			`printf("\n\tsignal bRAMOut : std_logic_vector(%d downto 0);", bytes * 8 - 1);`
265			`}`
266	14	jesus	`if (blockIter > 1)`
267			`{`
268	18	jesus	`printf("\n\ttype bRAMOut_a is array(%d to %d) of std_logic_vector(%d downto 0);", blockTotal - blockIter, blockTotal - 1, bytes * 8 - 1);`
269	14	jesus	`printf("\n\tsignal bRAMOut : bRAMOut_a;");`
270			`printf("\n\tsignal biA_r : integer;");`
271			`if (!selectIter)`
272			`{`
273			`printf("\n\tsignal A_r : unsigned(A'left downto 9);");`
274			`}`
275			`}`
276			`if (selectIter && blockIter)`
277			`{`
278			`printf("\n\tsignal bD : std_logic_vector(D'range);");`
279			`}`
280
281			`printf("\nbegin");`
282
283			`if (selectIter > 0 \|\| blockIter > 1)`
284			`{`
285			`printf("\n\tprocess (Clk)");`
286			`printf("\n\tbegin");`
287			`printf("\n\t\tif Clk'event and Clk = '1' then");`
288			`if (!selectIter)`
289			`{`
290			`printf("\n\t\t\tA_r <= unsigned(A(A'left downto 9));");`
291			`}`
292			`else`
293			`{`
294			`printf("\n\t\t\tA_r <= unsigned(A);");`
295			`}`
296			`printf("\n\t\tend if;");`
297			`printf("\n\tend process;");`
298			`}`
299
300			`if (selectIter == 1)`
301			`{`
302			`printf("\n\n\tsG1: for I in 0 to %d generate", dWidth - 1);`
303	30	jesus	`printf("\n\t\tS%s : RAM16X1S\n\t\t\tport map (", argv[1]);`
304	14	jesus	`if (blockIter)`
305			`{`
306			`printf("s");`
307			`}`
308	27	jesus	`printf("WE => '0', WCLK => '0', D => '0', O => D(I), A0 => A_r(0), A1 => A_r(1), A2 => A_r(2), A3 => A_r(3));");`
309	14	jesus	`printf("\n\tend generate;");`
310			`}`
311			`if (selectIter > 1)`
312			`{`
313			`printf("\n\n\tsiA_r <= to_integer(A_r(A'left downto 4));");`
314			`printf("\n\n\tsG1: for I in 0 to %d generate", selectIter - 1);`
315			`printf("\n\t\tsG2: for J in 0 to %d generate", dWidth - 1);`
316	27	jesus	`printf("\n\t\t\tS%s : RAM16X1S\n\t\t\t\tport map (WE => '0', WCLK => '0', D => '0', O => sRAMOut(I)(J), A0 => A_r(0), A1 => A_r(1), A2 => A_r(2), A3 => A_r(3));", argv[1]);`
317	14	jesus	`printf("\n\t\tend generate;");`
318			`if (z == 'z')`
319			`{`
320			`printf("\n\t\t");`
321			`if (blockIter)`
322			`{`
323			`printf("s");`
324			`}`
325			`printf("D <= sRAMOut(I) when siA_r = I else (others => 'Z');");`
326			`}`
327			`printf("\n\tend generate;");`
328			`if (z != 'z')`
329			`{`
330			`printf("\n\n\tprocess (siA_r, sRAMOut)\n\tbegin\n\t\t");`
331			`if (blockIter)`
332			`{`
333			`printf("s");`
334			`}`
335			`printf("D <= sRAMOut(0);");`
336			`printf("\n\t\tfor I in 1 to %d loop", selectIter - 1);`
337			`printf("\n\t\t\tif siA_r = I then\n\t\t\t\t");`
338			`if (blockIter)`
339			`{`
340			`printf("s");`
341			`}`
342			`printf("D <= sRAMOut(I);\n\t\t\tend if;");`
343			`printf("\n\t\tend loop;\n\tend process;");`
344			`}`
345			`}`
346
347			`if (blockIter == 1)`
348			`{`
349			`printf("\n\n\tbG1: for J in 0 to %d generate", bytes - 1);`
350	18	jesus	`printf("\n\t\tB%s : RAMB4_S8", argv[1]);`
351	27	jesus	`printf("\n\t\t\tport map (DI => \"00000000\", EN => '1', RST => '0', WE => '0', CLK => Clk, ADDR => A(8 downto 0), DO => bRAMOut(7 + 8 * J downto 8 * J));", argv[1]);`
352	18	jesus	`printf("\n\tend generate;");`
353			`printf("\n\n\t");`
354	14	jesus	`if (selectIter)`
355			`{`
356			`printf("b");`
357			`}`
358	18	jesus	`printf("D <= bRAMOut(D'range);");`
359	14	jesus	`}`
360			`if (blockIter > 1)`
361			`{`
362			`printf("\n\n\tbiA_r <= to_integer(A_r(A'left downto 9));");`
363			`printf("\n\n\tbG1: for I in %d to %d generate", blockTotal - blockIter, blockTotal - 1);`
364			`printf("\n\t\tbG2: for J in 0 to %d generate", bytes - 1);`
365	27	jesus	`printf("\n\t\t\tB%s : RAMB4_S8\n\t\t\t\tport map (DI => \"00000000\", EN => '1', RST => '0', WE => '0', CLK => Clk, ADDR => A(8 downto 0), DO => bRAMOut(I)(7 + 8 * J downto 8 * J));", argv[1]);`
366	14	jesus	`printf("\n\t\tend generate;");`
367			`if (z == 'z')`
368			`{`
369			`printf("\n\t\t");`
370			`if (selectIter)`
371			`{`
372			`printf("b");`
373			`}`
374			`printf("D <= bRAMOut(I) when biA_r = I else (others => 'Z');");`
375			`}`
376			`printf("\n\tend generate;");`
377			`if (z != 'z')`
378			`{`
379			`printf("\n\n\tprocess (biA_r, bRAMOut)\n\tbegin\n\t\t");`
380			`if (selectIter)`
381			`{`
382			`printf("b");`
383			`}`
384	18	jesus	`printf("D <= bRAMOut(%d)(D'range);", blockTotal - blockIter);`
385	14	jesus	`printf("\n\t\tfor I in %d to %d loop", blockTotal - blockIter + 1, blockTotal - 1);`
386			`printf("\n\t\t\tif biA_r = I then\n\t\t\t\t");`
387			`if (selectIter)`
388			`{`
389			`printf("b");`
390			`}`
391	18	jesus	`printf("D <= bRAMOut(I)(D'range);\n\t\t\tend if;");`
392	14	jesus	`printf("\n\t\tend loop;\n\tend process;");`
393			`}`
394			`}`
395
396			`if (selectIter && blockIter)`
397			`{`
398			`printf("\n\n\tD <= bD when A_r(A'left downto 9) >= %d else sD;", blockTotal - blockIter);`
399			`}`
400
401			`printf("\nend;\n");`
402
403			`return 0;`
404			`}`
405			`catch (string error)`
406			`{`
407			`cerr << "Fatal: " << error;`
408			`}`
409			`catch (const char *error)`
410			`{`
411			`cerr << "Fatal: " << error;`
412			`}`
413			`return -1;`
414			`}`

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