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https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk
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daniel.kho |
/*
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Tauhop Solutions common types.
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Author(s):
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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later version.
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml.
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*/
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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package types is
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type byte is array(7 downto 0) of std_logic;
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type byte_vector is array(natural range <>) of byte;
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/* VHDL-2008 datatypes.
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Comment out for simulation. Questa/ModelSim already supports this.
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*/
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-- type boolean_vector is array(natural range <>) of boolean;
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-- type integer_vector is array(natural range <>) of integer;
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/* [end]: VHDL-2008 datatypes. */
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end package types;
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package body types is
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end package body types;
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