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daniel.kho |
/*
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This file is part of the AXI4 Transactor and Bus Functional Model
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(axi4_tlm_bfm) project:
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http://www.opencores.org/project,axi4_tlm_bfm
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Description
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Implementation of AXI4 transactor data structures and high-level API.
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To Do:
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Author(s):
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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later version.
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml.
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*/
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/* FIXME VHDL-2008 instantiated package. Unsupported by VCS-MX, Quartus, and Vivado. QuestaSim/ModelSim supports well. */
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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--use std.textio.all;
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library tauhop;
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/* Record I/O data structures for AXI interface transactor (block interface). */
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package axiTLM is
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-- generic(
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-- type t_qualifier; type t_id; type t_dest; type t_user; type t_resp;
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-- package transactor is new tauhop.tlm generic map(<>)
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-- );
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-- /* Makes transactor.t_addr and transactor.t_msg visible. */
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-- use transactor.all;
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/* TODO remove once generic packages are supported. */
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use tauhop.tlm.all;
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daniel.kho |
--type boolean_vector is array(natural range<>) of boolean;
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--subtype t_qualifier is boolean_vector(32/8-1 downto 0);
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daniel.kho |
subtype t_qualifier is std_ulogic_vector(32/8-1 downto 0);
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subtype t_id is unsigned(31 downto 0);
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subtype t_dest is unsigned(3 downto 0);
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subtype t_user is unsigned(7 downto 0);
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subtype t_resp is unsigned(1 downto 0); --2 bits. b"00" = OKAY, b"01" = ExOKAY, b"10" = SLVERR (slave error), b"11" = DECERR (decode error).
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/* AXI Transactor block interfaces. */
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type t_axi4Transactor_m2s is record
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/* Address must be unresolved, because you need to drive the read address only when read is asserted, and
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drive the write address when write is asserted. Resolution functions are not expected to know how to decide this.
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*/
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/* Write address channel. */
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awId:t_id;
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-- awLen:unsigned(7 downto 0); --8 bits as defined by the standard.
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-- awSize:unsigned(2 downto 0); --3 bits as defined by the standard. Burst size for write transfers.
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-- awBurst:
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-- awLock:
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-- awCache:
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-- awQoS:
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-- awRegion:
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-- awUser:
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-- AXI4-Lite required signals.
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awAddr:t_addr;
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awProt:boolean;
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awValid:boolean;
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/* Write data channel. */
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wId:t_id;
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-- wLast:
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-- wUser:
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-- AXI4-Lite required signals.
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wValid:boolean;
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wData:t_msg;
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-- wStrb:std_ulogic_vector(wData'length/8-1 downto 0); --default is all ones if master always performs full datawidth write transactions.
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wStrb:t_qualifier; --default is all ones if master always performs full datawidth write transactions.
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/* Write response channel. */
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bReady:boolean;
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/* Read address channel. */
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arId:t_id;
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-- arLen:unsigned(7 downto 0); --8 bits as defined by the standard.
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-- arSize:unsigned(2 downto 0); --3 bits as defined by the standard.
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-- arBurst:
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-- arLock:
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-- arCache:
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-- arQoS:
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-- arRegion:
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-- arUser:
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-- AXI4-Lite required signals.
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arValid:boolean;
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arAddr:t_addr;
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arProt:boolean;
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/* Read data channel. */
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rReady:boolean;
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end record t_axi4Transactor_m2s;
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type t_axi4Transactor_s2m is record
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/* Write address channel. */
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awReady:boolean;
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/* Write data channel. */
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wReady:boolean;
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/* Write response channel. */
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bId:t_id;
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-- bUser:
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-- AXI4-Lite required signals.
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bValid:boolean;
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bResp:t_resp;
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/* Read address channel. */
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arReady:boolean;
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/* Read data channel. */
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rId:t_id;
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-- rLast:
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-- rUser:
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-- AXI4-Lite required signals.
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rValid:boolean;
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rData:t_msg;
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rResp:t_resp;
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end record t_axi4Transactor_s2m;
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type t_axi4StreamTransactor_m2s is record
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/* AXI4 streaming interface. */
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tValid:boolean;
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tData:t_msg;
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tStrb:t_qualifier;
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tKeep:t_qualifier;
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tLast:boolean;
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tId:t_id;
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tDest:t_dest;
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tUser:t_user;
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end record t_axi4StreamTransactor_m2s;
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type t_axi4StreamTransactor_s2m is record
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tReady:boolean;
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end record t_axi4StreamTransactor_s2m;
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-- /* AXI Low-power interface. */
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-- type tAxiTransactor_lp is record
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-- cSysReq:
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-- cSysAck:
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-- cActive:
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-- end record tAxiTransactor_lp;
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type t_fsm is (idle,sendAddr,startOfPacket,payload,endOfPacket,endOfTx);
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type axiBfmStatesTx is (idle,payload,endOfTx);
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type axiBfmStatesRx is (idle,checkAddr,startOfPacket,payload);
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daniel.kho |
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attribute enum_encoding:string;
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attribute enum_encoding of axiBfmStatesTx:type is "00 01 10";
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function to_std_logic_vector(fsm:axiBfmStatesTx) return std_logic_vector;
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end package axiTLM;
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package body axiTLM is
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function to_std_logic_vector(fsm:axiBfmStatesTx) return std_logic_vector is
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variable r:std_logic_vector(1 downto 0);
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begin
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case fsm is
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when idle=> r:=2x"0";
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when payload=> r:=2x"1";
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when endOfTx=> r:=2x"2";
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when others=> null;
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end case;
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return r;
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end function to_std_logic_vector;
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end package body axiTLM;
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/* AXI Transactor API.
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* Generally, transactors are high-level bus interface models that perform
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* read/write transactions to/from the bus. These models are not concerned
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* with the low-level implementation of the bus protocol. However, the
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* TLM models encapsulate the lower-level models known as the BFM.
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* axiTLM uses generic package tauhop.tlm, hence inherits basic TLM types and
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* procedures generally used in any messaging system (i.e. address and message
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* information, and bus read/write methods). It also extends the tauhop.tlm
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* package with application-specific types, such as record structures specific
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* to the AXI protocol.
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* axiTransactor instantiates the axiTLM, and assigns specific types to the
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* transactor model.
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*/
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/*library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library tauhop;
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package transactor is new tauhop.tlm generic map(
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t_addr=>unsigned(31 downto 0), -- default assignment. Used only for non-stream interfaces.
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t_msg=>signed(63 downto 0),
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t_cnt=>unsigned(127 downto 0)
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);
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library tauhop; use tauhop.transactor.all;
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package axiTransactor is new tauhop.axiTLM generic map(
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t_qualifier=>boolean_vector(32/8-1 downto 0),
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t_id=>unsigned(7 downto 0),
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t_dest=>unsigned(3 downto 0),
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t_user=>unsigned(7 downto 0), --unsigned(86*2-1 downto 0),
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t_resp=>unsigned(1 downto 0), --only used for AXI4-Lite (non-streaming).
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transactor=>tauhop.transactor
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);
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*/
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