OpenCores
URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] [stp.vhd] - Blame information for rev 37

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 daniel.kho
-- megafunction wizard: %SignalTap II Logic Analyzer%
2
-- GENERATION: STANDARD
3
-- VERSION: WM1.0
4
-- MODULE: sld_signaltap 
5
 
6
-- ============================================================
7
-- File Name: stp.vhd
8
-- Megafunction Name(s):
9
--                      sld_signaltap
10
--
11
-- Simulation Library Files(s):
12
--                      
13
-- ============================================================
14
-- ************************************************************
15
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16
--
17
-- 12.1 Build 177 11/07/2012 SJ Full Version
18
-- ************************************************************
19
 
20
 
21
--Copyright (C) 1991-2012 Altera Corporation
22
--Your use of Altera Corporation's design tools, logic functions 
23
--and other software and tools, and its AMPP partner logic 
24
--functions, and any output files from any of the foregoing 
25
--(including device programming or simulation files), and any 
26
--associated documentation or information are expressly subject 
27
--to the terms and conditions of the Altera Program License 
28
--Subscription Agreement, Altera MegaCore Function License 
29
--Agreement, or other applicable license agreement, including, 
30
--without limitation, that your use is for the sole purpose of 
31
--programming logic devices manufactured by Altera and sold by 
32
--Altera or its authorized distributors.  Please refer to the 
33
--applicable agreement for further details.
34
 
35
 
36
LIBRARY ieee;
37
USE ieee.std_logic_1164.all;
38
 
39
LIBRARY altera_mf;
40
USE altera_mf.all;
41
 
42
ENTITY stp IS
43
        PORT
44
        (
45
                acq_clk         : IN STD_LOGIC ;
46
                acq_data_in             : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
47
                acq_trigger_in          : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
48
                trigger_in              : IN STD_LOGIC
49
        );
50
END stp;
51
 
52
 
53
ARCHITECTURE SYN OF stp IS
54
 
55
 
56
 
57
 
58
        COMPONENT sld_signaltap
59
        GENERIC (
60
                sld_advanced_trigger_entity             : STRING;
61
                sld_data_bits           : NATURAL;
62
                sld_data_bit_cntr_bits          : NATURAL;
63
                sld_enable_advanced_trigger             : NATURAL;
64
                sld_mem_address_bits            : NATURAL;
65
                sld_node_crc_bits               : NATURAL;
66
                sld_node_crc_hiword             : NATURAL;
67
                sld_node_crc_loword             : NATURAL;
68
                sld_node_info           : NATURAL;
69
                sld_ram_block_type              : STRING;
70
                sld_sample_depth                : NATURAL;
71
                sld_storage_qualifier_gap_record                : NATURAL;
72
                sld_storage_qualifier_mode              : STRING;
73
                sld_trigger_bits                : NATURAL;
74
                sld_trigger_in_enabled          : NATURAL;
75
                sld_trigger_level               : NATURAL;
76
                sld_trigger_level_pipeline              : NATURAL;
77
                lpm_type                : STRING
78
        );
79
        PORT (
80
                        acq_clk : IN STD_LOGIC ;
81
                        acq_data_in     : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
82
                        acq_trigger_in  : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
83
                        trigger_in      : IN STD_LOGIC
84
        );
85
        END COMPONENT;
86
 
87
BEGIN
88
 
89
        sld_signaltap_component : sld_signaltap
90
        GENERIC MAP (
91
                sld_advanced_trigger_entity => "basic,1,",
92
                sld_data_bits => 128,
93
                sld_data_bit_cntr_bits => 8,
94
                sld_enable_advanced_trigger => 0,
95
                sld_mem_address_bits => 12,
96
                sld_node_crc_bits => 32,
97 17 daniel.kho
                sld_node_crc_hiword => 7854,
98
                sld_node_crc_loword => 42699,
99 9 daniel.kho
                sld_node_info => 1076736,
100
                sld_ram_block_type => "Auto",
101
                sld_sample_depth => 4096,
102
                sld_storage_qualifier_gap_record => 0,
103
                sld_storage_qualifier_mode => "OFF",
104
                sld_trigger_bits => 1,
105
                sld_trigger_in_enabled => 1,
106
                sld_trigger_level => 1,
107
                sld_trigger_level_pipeline => 1,
108
                lpm_type => "sld_signaltap"
109
        )
110
        PORT MAP (
111
                acq_clk => acq_clk,
112
                acq_data_in => acq_data_in,
113
                acq_trigger_in => acq_trigger_in,
114
                trigger_in => trigger_in
115
        );
116
 
117
 
118
 
119
END SYN;
120
 
121
-- ============================================================
122
-- CNX file retrieval info
123
-- ============================================================
124
-- Retrieval info: PRIVATE: DATA_WIDTH_SPIN STRING ""
125
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
126
-- Retrieval info: PRIVATE: RAM_TYPE_COMBO STRING "Auto"
127
-- Retrieval info: PRIVATE: SAMPLE_DEPTH_COMBO STRING "4 K"
128
-- Retrieval info: PRIVATE: SLD_TRIGGER_OUT_ENABLED NUMERIC "0"
129
-- Retrieval info: PRIVATE: TRIGGER_LEVELS_COMBO STRING "1"
130
-- Retrieval info: PRIVATE: TRIGGER_WIDTH_SPIN STRING ""
131
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
132
-- Retrieval info: CONSTANT: SLD_ADVANCED_TRIGGER_ENTITY STRING "basic,1,"
133 17 daniel.kho
-- Retrieval info: CONSTANT: SLD_DATA_BITS NUMERIC "128"
134 9 daniel.kho
-- Retrieval info: CONSTANT: SLD_DATA_BIT_CNTR_BITS NUMERIC "8"
135
-- Retrieval info: CONSTANT: SLD_ENABLE_ADVANCED_TRIGGER NUMERIC "0"
136
-- Retrieval info: CONSTANT: SLD_MEM_ADDRESS_BITS NUMERIC "12"
137
-- Retrieval info: CONSTANT: SLD_NODE_CRC_BITS NUMERIC "32"
138 17 daniel.kho
-- Retrieval info: CONSTANT: SLD_NODE_CRC_HIWORD NUMERIC "7854"
139
-- Retrieval info: CONSTANT: SLD_NODE_CRC_LOWORD NUMERIC "42699"
140 9 daniel.kho
-- Retrieval info: CONSTANT: SLD_NODE_INFO NUMERIC "1076736"
141
-- Retrieval info: CONSTANT: SLD_RAM_BLOCK_TYPE STRING "Auto"
142
-- Retrieval info: CONSTANT: SLD_SAMPLE_DEPTH NUMERIC "4096"
143
-- Retrieval info: CONSTANT: SLD_STORAGE_QUALIFIER_GAP_RECORD NUMERIC "0"
144
-- Retrieval info: CONSTANT: SLD_STORAGE_QUALIFIER_MODE STRING "OFF"
145
-- Retrieval info: CONSTANT: SLD_TRIGGER_BITS NUMERIC "1"
146
-- Retrieval info: CONSTANT: SLD_TRIGGER_IN_ENABLED NUMERIC "1"
147
-- Retrieval info: CONSTANT: SLD_TRIGGER_LEVEL NUMERIC "1"
148
-- Retrieval info: CONSTANT: SLD_TRIGGER_LEVEL_PIPELINE NUMERIC "1"
149
-- Retrieval info: USED_PORT: acq_clk 0 0 0 0 INPUT NODEFVAL "acq_clk"
150 17 daniel.kho
-- Retrieval info: USED_PORT: acq_data_in 0 0 128 0 INPUT NODEFVAL "acq_data_in[127..0]"
151 9 daniel.kho
-- Retrieval info: USED_PORT: acq_trigger_in 0 0 1 0 INPUT NODEFVAL "acq_trigger_in[0..0]"
152
-- Retrieval info: USED_PORT: trigger_in 0 0 0 0 INPUT NODEFVAL "trigger_in"
153
-- Retrieval info: CONNECT: @acq_clk 0 0 0 0 acq_clk 0 0 0 0
154 17 daniel.kho
-- Retrieval info: CONNECT: @acq_data_in 0 0 128 0 acq_data_in 0 0 128 0
155 9 daniel.kho
-- Retrieval info: CONNECT: @acq_trigger_in 0 0 1 0 acq_trigger_in 0 0 1 0
156
-- Retrieval info: CONNECT: @trigger_in 0 0 0 0 trigger_in 0 0 0 0
157
-- Retrieval info: GEN_FILE: TYPE_NORMAL stp.vhd TRUE
158
-- Retrieval info: GEN_FILE: TYPE_NORMAL stp.inc FALSE
159
-- Retrieval info: GEN_FILE: TYPE_NORMAL stp.cmp FALSE
160
-- Retrieval info: GEN_FILE: TYPE_NORMAL stp.bsf FALSE
161
-- Retrieval info: GEN_FILE: TYPE_NORMAL stp_inst.vhd FALSE

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.