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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] [tester.vhdl] - Blame information for rev 31

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/*
        This file is part of the AXI4 Transactor and Bus Functional Model
        (axi4_tlm_bfm) project:
                http://www.opencores.org/project,axi4_tlm_bfm
 
        Description
        Synthesisable use case for AXI4 on-chip messaging.
 
        To Do:
 
        Author(s):
        - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
 
        Copyright (C) 2012-2013 Authors and OPENCORES.ORG
 
        This source file may be used and distributed without
        restriction provided that this copyright statement is not
        removed from the file and that any derivative work contains
        the original copyright notice and the associated disclaimer.
 
        This source file is free software; you can redistribute it
        and/or modify it under the terms of the GNU Lesser General
        Public License as published by the Free Software Foundation;
        either version 2.1 of the License, or (at your option) any
        later version.
 
        This source is distributed in the hope that it will be
        useful, but WITHOUT ANY WARRANTY; without even the implied
        warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
        PURPOSE. See the GNU Lesser General Public License for more
        details.
 
        You should have received a copy of the GNU Lesser General
        Public License along with this source; if not, download it
        from http://www.opencores.org/lgpl.shtml.
*/
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all;          --TODO just use axiTransactor here as transactor should already be wrapped up.
 
/* TODO remove once generic packages are supported. */
library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
 
/* synthesis translate_off */
library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
/* synthesis translate_on */
 
library altera; use altera.stp;
 
 
entity tester is port(
        /* Comment-out for simulation. */
        clk,reset:in std_ulogic;
 
        /* AXI Master interface */
        axiMaster_in:buffer t_axi4StreamTransactor_s2m;
        axiMaster_out:in t_axi4StreamTransactor_m2s;
 
        /* BFM signalling. */
--      readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
--      readResponse,writeResponse:t_bfm;
        readRequest,writeRequest:buffer t_bfm;
        readResponse,writeResponse:in t_bfm;
 
        irq_write:buffer std_ulogic;            -- clock gating.
 
        symbolsPerTransfer:buffer t_cnt;
        outstandingTransactions:buffer t_cnt;
 
        /* Debug ports. */
--      dataIn:in t_msg;
        selTxn:in unsigned(3 downto 0)
);
end entity tester;
 
architecture rtl of tester is
--      signal reset:std_ulogic:='0';
        signal locked:std_ulogic;
        signal porCnt:unsigned(3 downto 0);
        signal trigger:boolean;
 
        /* Global counters. */
        constant maxSymbols:positive:=2048;             --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width. 
--      signal symbolsPerTransfer:t_cnt;
--      signal outstandingTransactions:t_cnt;
 
--      /* BFM signalling. */
--      signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
--      signal readResponse,writeResponse:t_bfm;
 
        type txStates is (idle,transmitting);
        signal txFSM,i_txFSM:txStates;
 
        /* Tester signals. */
        /* synthesis translate_off */
        signal clk,nReset:std_ulogic:='0';
        attribute period:time; attribute period of clk:signal is 10 ps;
        /* synthesis translate_on */
 
        signal testerClk:std_ulogic;
        signal dbg_axiTxFSM:axiBfmStatesTx;
        signal anlysr_dataIn:std_logic_vector(127 downto 0);
        signal anlysr_trigger:std_ulogic;
 
--      signal axiMaster_in:t_axi4StreamTransactor_s2m;
--      signal irq_write:std_ulogic;            -- clock gating.
 
        signal prbs:t_msg;
 
begin
        /* PLL to generate tester's clock. */
    f100MHz: entity altera.pll(syn) port map(
        areset=>'0',    --not nReset,
        inclk0=>clk,
        c0=>testerClk,
        locked=>locked
    );
 
        /* Interrupt-request generator. */
        trigger<=txFSM/=i_txFSM or writeResponse.trigger;
        irq_write<=clk when not reset else '0';
 
        /* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
        --anlysr_trigger<='1' when writeRequest.trigger else '0';
        anlysr_trigger<='1' when reset else '0';
 
        /* Disable this for synthesis as this is not currently synthesisable.
                Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
        */
        /* synthesis translate_off */
        --framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);
        /* synthesis translate_on */
 
        anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
        anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
        --anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>;
        anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
        anlysr_dataIn(18)<='1' when clk else '0';
        anlysr_dataIn(19)<='1' when reset else '0';
        anlysr_dataIn(20)<='1' when irq_write else '0';
        anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
        anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
        anlysr_dataIn(54 downto 23)<=std_logic_vector(axiMaster_out.tData);
        anlysr_dataIn(86 downto 55)<=std_logic_vector(prbs);
        anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
        anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
        anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
        anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
        anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
        --anlysr_dataIn(99 downto 98)<=to_std_logic_vector(txFSM);
        anlysr_dataIn(101 downto 98)<=std_logic_vector(porCnt);
--      anlysr_dataIn(102)<='1' when locked else '0';
--      anlysr_dataIn(102)<=locked;
 
        anlysr_dataIn(anlysr_dataIn'high downto 102)<=(others=>'0');
 
 
        /* Simulate only if you have compiled Altera's simulation libraries. */
        i_bist_logicAnalyser: entity altera.stp(syn) port map(
                acq_clk=>testerClk,
                acq_data_in=>anlysr_dataIn,
                acq_trigger_in=>"1",
                trigger_in=>anlysr_trigger
        );
 
 
 
        /* Stimuli sequencer. TODO move to tester/stimuli.
                This emulates the AXI4-Stream Slave.
        */
        /* Simulation-only stimuli sequencer. */
        /* synthesis translate_off */
        process is begin
                report "Performing fast read..." severity note;
 
                /* Fast read. */
                while not axiMaster_out.tLast loop
                        /* Wait for tValid to assert. */
                        while not axiMaster_out.tValid loop
                                wait until falling_edge(clk);
                        end loop;
 
                        axiMaster_in.tReady<=true;
 
                        wait until falling_edge(clk);
                        axiMaster_in.tReady<=false;
                end loop;
 
                wait until falling_edge(clk);
                report "Performing normal read..." severity note;
 
                /* Normal read. */
                while not axiMaster_out.tLast loop
                        /* Wait for tValid to assert. */
                        while not axiMaster_out.tValid loop
                                wait until falling_edge(clk);
                        end loop;
 
                        wait until falling_edge(clk);
                        wait until falling_edge(clk);
                        axiMaster_in.tReady<=true;
 
                        wait until falling_edge(clk);
                        axiMaster_in.tReady<=false;
 
                        wait until falling_edge(clk);
                end loop;
 
                report "Completed normal read." severity note;
 
                for i in 0 to 10 loop
                        wait until falling_edge(clk);
                end loop;
 
                /* One-shot read. */
                axiMaster_in.tReady<=true;
 
                wait until falling_edge(clk);
                axiMaster_in.tReady<=false;
 
                report "Completed one-shot read." severity note;
 
                wait;
        end process;
        /* synthesis translate_on */
 
        /* Synthesisable stimuli sequencer. */
        process(clk) is begin
                if falling_edge(clk) then
                        axiMaster_in.tReady<=false;
                        --if axiMaster_out.tValid and not axiMaster_out.tLast then
                        if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then
                                axiMaster_in.tReady<=true;
                        end if;
                end if;
        end process;
 
 
        /* Data transmitter. */
        i_prbs: entity tauhop.prbs31(rtl)
                generic map(
                        isParallelLoad=>true,
                        tapVector=>(
                                /* Example polynomial from Wikipedia:
                                        http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
                                */
                                0|3|31=>true, 1|2|30 downto 4=>false
                        )
                )
                port map(
                        /* Comment-out for simulation. */
                        clk=>irq_write, reset=>reset,
                        en=>trigger,
                        seed=>32x"ace1",        --9x"57",
                        prbs=>prbs
                );
 
        sequencer_ns: process(all) is begin
                txFSM<=i_txFSM;
                if reset then txFSM<=idle;
                else
                        case i_txFSM is
                                when idle=>
                                        if outstandingTransactions>0 then txFSM<=transmitting; end if;
                                when transmitting=>
                                        if axiMaster_out.tLast then
                                                txFSM<=idle;
                                        end if;
                                when others=> null;
                        end case;
                end if;
        end process sequencer_ns;
 
        sequencer_op: process(reset,irq_write) is
                /* Local procedures to map BFM signals with the package procedure. */
                procedure read(address:in t_addr) is begin
                        read(readRequest,address);
                end procedure read;
 
                procedure write(data:in t_msg) is begin
                        write(request=>writeRequest, address=>(others=>'-'), data=>data);
                end procedure write;
 
                variable isPktError:boolean;
 
                /* Tester variables. */
                /* Synthesis-only randomisation. */
 
                /* Simulation-only randomisation. */
                /* synthesis translate_off */
                variable rv0:RandomPType;
                /* synthesis translate_on */
 
--              variable trigger:boolean;
        begin
--              if reset then
                        /* simulation only. */
                        /* synthesis translate_off */
--                      rv0.InitSeed(rv0'instance_name);
                        /* synthesis translate_on */
                if falling_edge(irq_write) then
                        case txFSM is
                                when transmitting=>
                                        if trigger then
                                                /* synthesis translate_off */
                                                write(rv0.RandSigned(axiMaster_out.tData'length));
                                                /* synthesis translate_on */
 
                                                --write(prbs);
 
                                                case selTxn is
                                                        when x"1"=> write(32x"12ab34cd");
                                                        when x"2"=> write(32x"12345678");
                                                        when x"3"=> write(32x"87654321");
                                                        when x"4"=> write(32x"abcd1234");
                                                        when others=> write(prbs);
                                                end case;
                                        end if;
                                when others=>null;
                        end case;
                end if;
        end process sequencer_op;
 
        sequencer_regs: process(irq_write) is begin
        if falling_edge(irq_write) then
            i_txFSM<=txFSM;
        end if;
    end process sequencer_regs;
 
    /* Transaction counter. */
        process(reset,symbolsPerTransfer,irq_write) is begin
                /* TODO close timing for asynchronous reset. */
                if reset then outstandingTransactions<=symbolsPerTransfer;
                elsif rising_edge(irq_write) then
                        if not axiMaster_out.tLast then
                                if outstandingTransactions<1 then
                                        outstandingTransactions<=symbolsPerTransfer;
                                        report "No more pending transactions." severity note;
                                elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
                                end if;
                        end if;
 
                        /* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */
                        if reset then outstandingTransactions<=symbolsPerTransfer; end if;
                end if;
        end process;
 
        /* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
        process(reset,irq_write) is
                /* synthesis translate_off */
                variable rv0:RandomPType;
                /* synthesis translate_on */
        begin
                if reset then
                        /* synthesis translate_off */
                        rv0.InitSeed(rv0'instance_name);
                        symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
                        report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
                        /* synthesis translate_on */
 
                        symbolsPerTransfer<=128x"fc";
                elsif rising_edge(irq_write) then
                        if axiMaster_out.tLast then
                                /* synthesis only. */
                                /* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
                                --symbolsPerTransfer<=(others=>'0');
 
                                /* Testcase 2: number of symbols per transfer is randomised. */
                                --uniform(seed0,seed1,rand0);
                                --symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8);  --symbolsPerTransfer'length
                                --report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8));       --axiMaster_out.tData'length));
 
 
                                /* synthesis translate_off */
                                symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
                                report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
                                /* synthesis translate_on */
 
                                symbolsPerTransfer<=128x"0f";           --128x"ffffffff_ffffffff_ffffffff_ffffffff";
                        end if;
                end if;
        end process;
 
--    outstandingTransactions<=128x"fc";      --symbolsPerTransfer;
end architecture rtl;

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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] [tester.vhdl] - Blame information for rev 31

Line No.	Rev	Author	Line
1	18	daniel.kho	`/*`
2			`This file is part of the AXI4 Transactor and Bus Functional Model`
3			`(axi4_tlm_bfm) project:`
4			`http://www.opencores.org/project,axi4_tlm_bfm`
5
6			`Description`
7			`Synthesisable use case for AXI4 on-chip messaging.`
8
9			`To Do:`
10
11			`Author(s):`
12			`- Daniel C.K. Kho, daniel.kho@opencores.org \| daniel.kho@tauhop.com`
13
14			`Copyright (C) 2012-2013 Authors and OPENCORES.ORG`
15
16			`This source file may be used and distributed without`
17			`restriction provided that this copyright statement is not`
18			`removed from the file and that any derivative work contains`
19			`the original copyright notice and the associated disclaimer.`
20
21			`This source file is free software; you can redistribute it`
22			`and/or modify it under the terms of the GNU Lesser General`
23			`Public License as published by the Free Software Foundation;`
24			`either version 2.1 of the License, or (at your option) any`
25			`later version.`
26
27			`This source is distributed in the hope that it will be`
28			`useful, but WITHOUT ANY WARRANTY; without even the implied`
29			`warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
30			`PURPOSE. See the GNU Lesser General Public License for more`
31			`details.`
32
33			`You should have received a copy of the GNU Lesser General`
34			`Public License along with this source; if not, download it`
35			`from http://www.opencores.org/lgpl.shtml.`
36			`*/`
37			`library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;`
38			`--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.`
39
40			`/* TODO remove once generic packages are supported. */`
41			`library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;`
42
43			`/* synthesis translate_off */`
44			`library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;`
45			`/* synthesis translate_on */`
46
47			`library altera; use altera.stp;`
48
49
50			`entity tester is port(`
51			`/* Comment-out for simulation. */`
52			`clk,reset:in std_ulogic;`
53
54			`/* AXI Master interface */`
55			`axiMaster_in:buffer t_axi4StreamTransactor_s2m;`
56			`axiMaster_out:in t_axi4StreamTransactor_m2s;`
57
58			`/* BFM signalling. */`
59			`-- readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);`
60			`-- readResponse,writeResponse:t_bfm;`
61			`readRequest,writeRequest:buffer t_bfm;`
62			`readResponse,writeResponse:in t_bfm;`
63
64			`irq_write:buffer std_ulogic; -- clock gating.`
65
66			`symbolsPerTransfer:buffer t_cnt;`
67			`outstandingTransactions:buffer t_cnt;`
68
69			`/* Debug ports. */`
70			`-- dataIn:in t_msg;`
71			`selTxn:in unsigned(3 downto 0)`
72			`);`
73			`end entity tester;`
74
75			`architecture rtl of tester is`
76			`-- signal reset:std_ulogic:='0';`
77			`signal locked:std_ulogic;`
78			`signal porCnt:unsigned(3 downto 0);`
79			`signal trigger:boolean;`
80
81			`/* Global counters. */`
82			`constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.`
83			`-- signal symbolsPerTransfer:t_cnt;`
84			`-- signal outstandingTransactions:t_cnt;`
85
86			`-- /* BFM signalling. */`
87			`-- signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);`
88			`-- signal readResponse,writeResponse:t_bfm;`
89
90			`type txStates is (idle,transmitting);`
91			`signal txFSM,i_txFSM:txStates;`
92
93			`/* Tester signals. */`
94			`/* synthesis translate_off */`
95			`signal clk,nReset:std_ulogic:='0';`
96			`attribute period:time; attribute period of clk:signal is 10 ps;`
97			`/* synthesis translate_on */`
98
99			`signal testerClk:std_ulogic;`
100			`signal dbg_axiTxFSM:axiBfmStatesTx;`
101			`signal anlysr_dataIn:std_logic_vector(127 downto 0);`
102			`signal anlysr_trigger:std_ulogic;`
103
104			`-- signal axiMaster_in:t_axi4StreamTransactor_s2m;`
105			`-- signal irq_write:std_ulogic; -- clock gating.`
106
107			`signal prbs:t_msg;`
108
109			`begin`
110			`/* PLL to generate tester's clock. */`
111			`f100MHz: entity altera.pll(syn) port map(`
112			`areset=>'0', --not nReset,`
113			`inclk0=>clk,`
114			`c0=>testerClk,`
115			`locked=>locked`
116			`);`
117
118			`/* Interrupt-request generator. */`
119			`trigger<=txFSM/=i_txFSM or writeResponse.trigger;`
120			`irq_write<=clk when not reset else '0';`
121
122			`/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */`
123			`--anlysr_trigger<='1' when writeRequest.trigger else '0';`
124			`anlysr_trigger<='1' when reset else '0';`
125
126			`/* Disable this for synthesis as this is not currently synthesisable.`
127			`Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.`
128			`*/`
129			`/* synthesis translate_off */`
130			`--framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);`
131			`/* synthesis translate_on */`
132
133			`anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));`
134			`anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));`
135			`--anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>;`
136			`anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);`
137			`anlysr_dataIn(18)<='1' when clk else '0';`
138			`anlysr_dataIn(19)<='1' when reset else '0';`
139			`anlysr_dataIn(20)<='1' when irq_write else '0';`
140			`anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';`
141			`anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';`
142			`anlysr_dataIn(54 downto 23)<=std_logic_vector(axiMaster_out.tData);`
143			`anlysr_dataIn(86 downto 55)<=std_logic_vector(prbs);`
144			`anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);`
145			`anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);`
146			`anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';`
147			`anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';`
148			`anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';`
149			`--anlysr_dataIn(99 downto 98)<=to_std_logic_vector(txFSM);`
150			`anlysr_dataIn(101 downto 98)<=std_logic_vector(porCnt);`
151			`-- anlysr_dataIn(102)<='1' when locked else '0';`
152			`-- anlysr_dataIn(102)<=locked;`
153
154			`anlysr_dataIn(anlysr_dataIn'high downto 102)<=(others=>'0');`
155
156
157			`/* Simulate only if you have compiled Altera's simulation libraries. */`
158			`i_bist_logicAnalyser: entity altera.stp(syn) port map(`
159			`acq_clk=>testerClk,`
160			`acq_data_in=>anlysr_dataIn,`
161			`acq_trigger_in=>"1",`
162			`trigger_in=>anlysr_trigger`
163			`);`
164
165
166
167			`/* Stimuli sequencer. TODO move to tester/stimuli.`
168			`This emulates the AXI4-Stream Slave.`
169			`*/`
170			`/* Simulation-only stimuli sequencer. */`
171			`/* synthesis translate_off */`
172			`process is begin`
173			`report "Performing fast read..." severity note;`
174
175			`/* Fast read. */`
176			`while not axiMaster_out.tLast loop`
177			`/* Wait for tValid to assert. */`
178			`while not axiMaster_out.tValid loop`
179			`wait until falling_edge(clk);`
180			`end loop;`
181
182			`axiMaster_in.tReady<=true;`
183
184			`wait until falling_edge(clk);`
185			`axiMaster_in.tReady<=false;`
186			`end loop;`
187
188			`wait until falling_edge(clk);`
189			`report "Performing normal read..." severity note;`
190
191			`/* Normal read. */`
192			`while not axiMaster_out.tLast loop`
193			`/* Wait for tValid to assert. */`
194			`while not axiMaster_out.tValid loop`
195			`wait until falling_edge(clk);`
196			`end loop;`
197
198			`wait until falling_edge(clk);`
199			`wait until falling_edge(clk);`
200			`axiMaster_in.tReady<=true;`
201
202			`wait until falling_edge(clk);`
203			`axiMaster_in.tReady<=false;`
204
205			`wait until falling_edge(clk);`
206			`end loop;`
207
208			`report "Completed normal read." severity note;`
209
210			`for i in 0 to 10 loop`
211			`wait until falling_edge(clk);`
212			`end loop;`
213
214			`/* One-shot read. */`
215			`axiMaster_in.tReady<=true;`
216
217			`wait until falling_edge(clk);`
218			`axiMaster_in.tReady<=false;`
219
220			`report "Completed one-shot read." severity note;`
221
222			`wait;`
223			`end process;`
224			`/* synthesis translate_on */`
225
226			`/* Synthesisable stimuli sequencer. */`
227			`process(clk) is begin`
228			`if falling_edge(clk) then`
229			`axiMaster_in.tReady<=false;`
230			`--if axiMaster_out.tValid and not axiMaster_out.tLast then`
231			`if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then`
232			`axiMaster_in.tReady<=true;`
233			`end if;`
234			`end if;`
235			`end process;`
236
237
238			`/* Data transmitter. */`
239			`i_prbs: entity tauhop.prbs31(rtl)`
240			`generic map(`
241			`isParallelLoad=>true,`
242			`tapVector=>(`
243			`/* Example polynomial from Wikipedia:`
244			`http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks`
245			`*/`
246			`0\|3\|31=>true, 1\|2\|30 downto 4=>false`
247			`)`
248			`)`
249			`port map(`
250			`/* Comment-out for simulation. */`
251			`clk=>irq_write, reset=>reset,`
252			`en=>trigger,`
253			`seed=>32x"ace1", --9x"57",`
254			`prbs=>prbs`
255			`);`
256
257			`sequencer_ns: process(all) is begin`
258			`txFSM<=i_txFSM;`
259			`if reset then txFSM<=idle;`
260			`else`
261			`case i_txFSM is`
262			`when idle=>`
263			`if outstandingTransactions>0 then txFSM<=transmitting; end if;`
264			`when transmitting=>`
265			`if axiMaster_out.tLast then`
266			`txFSM<=idle;`
267			`end if;`
268			`when others=> null;`
269			`end case;`
270			`end if;`
271			`end process sequencer_ns;`
272
273			`sequencer_op: process(reset,irq_write) is`
274			`/* Local procedures to map BFM signals with the package procedure. */`
275			`procedure read(address:in t_addr) is begin`
276			`read(readRequest,address);`
277			`end procedure read;`
278
279			`procedure write(data:in t_msg) is begin`
280			`write(request=>writeRequest, address=>(others=>'-'), data=>data);`
281			`end procedure write;`
282
283			`variable isPktError:boolean;`
284
285			`/* Tester variables. */`
286			`/* Synthesis-only randomisation. */`
287
288			`/* Simulation-only randomisation. */`
289			`/* synthesis translate_off */`
290			`variable rv0:RandomPType;`
291			`/* synthesis translate_on */`
292
293			`-- variable trigger:boolean;`
294			`begin`
295			`-- if reset then`
296			`/* simulation only. */`
297			`/* synthesis translate_off */`
298			`-- rv0.InitSeed(rv0'instance_name);`
299			`/* synthesis translate_on */`
300			`if falling_edge(irq_write) then`
301			`case txFSM is`
302			`when transmitting=>`
303			`if trigger then`
304			`/* synthesis translate_off */`
305			`write(rv0.RandSigned(axiMaster_out.tData'length));`
306			`/* synthesis translate_on */`
307
308			`--write(prbs);`
309
310			`case selTxn is`
311			`when x"1"=> write(32x"12ab34cd");`
312			`when x"2"=> write(32x"12345678");`
313			`when x"3"=> write(32x"87654321");`
314			`when x"4"=> write(32x"abcd1234");`
315			`when others=> write(prbs);`
316			`end case;`
317			`end if;`
318			`when others=>null;`
319			`end case;`
320			`end if;`
321			`end process sequencer_op;`
322
323			`sequencer_regs: process(irq_write) is begin`
324			`if falling_edge(irq_write) then`
325			`i_txFSM<=txFSM;`
326			`end if;`
327			`end process sequencer_regs;`
328
329			`/* Transaction counter. */`
330			`process(reset,symbolsPerTransfer,irq_write) is begin`
331			`/* TODO close timing for asynchronous reset. */`
332			`if reset then outstandingTransactions<=symbolsPerTransfer;`
333			`elsif rising_edge(irq_write) then`
334			`if not axiMaster_out.tLast then`
335			`if outstandingTransactions<1 then`
336			`outstandingTransactions<=symbolsPerTransfer;`
337			`report "No more pending transactions." severity note;`
338			`elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;`
339			`end if;`
340			`end if;`
341
342			`/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */`
343			`if reset then outstandingTransactions<=symbolsPerTransfer; end if;`
344			`end if;`
345			`end process;`
346
347			`/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */`
348			`process(reset,irq_write) is`
349			`/* synthesis translate_off */`
350			`variable rv0:RandomPType;`
351			`/* synthesis translate_on */`
352			`begin`
353			`if reset then`
354			`/* synthesis translate_off */`
355			`rv0.InitSeed(rv0'instance_name);`
356			`symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);`
357			`report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;`
358			`/* synthesis translate_on */`
359
360			`symbolsPerTransfer<=128x"fc";`
361			`elsif rising_edge(irq_write) then`
362			`if axiMaster_out.tLast then`
363			`/* synthesis only. */`
364			`/* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */`
365			`--symbolsPerTransfer<=(others=>'0');`
366
367			`/* Testcase 2: number of symbols per transfer is randomised. */`
368			`--uniform(seed0,seed1,rand0);`
369			`--symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length`
370			`--report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));`
371
372
373			`/* synthesis translate_off */`
374			`symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);`
375			`report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;`
376			`/* synthesis translate_on */`
377
378			`symbolsPerTransfer<=128x"0f"; --128x"ffffffff_ffffffff_ffffffff_ffffffff";`
379			`end if;`
380			`end if;`
381			`end process;`
382
383			`-- outstandingTransactions<=128x"fc"; --symbolsPerTransfer;`
384			`end architecture rtl;`