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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] [user.vhdl] - Blame information for rev 11

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/*
        This file is part of the AXI4 Transactor and Bus Functional Model
        (axi4_tlm_bfm) project:
                http://www.opencores.org/project,axi4_tlm_bfm
 
        Description
        Synthesisable use case for AXI4 on-chip messaging.
 
        To Do:
 
        Author(s):
        - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
 
        Copyright (C) 2012-2013 Authors and OPENCORES.ORG
 
        This source file may be used and distributed without
        restriction provided that this copyright statement is not
        removed from the file and that any derivative work contains
        the original copyright notice and the associated disclaimer.
 
        This source file is free software; you can redistribute it
        and/or modify it under the terms of the GNU Lesser General
        Public License as published by the Free Software Foundation;
        either version 2.1 of the License, or (at your option) any
        later version.
 
        This source is distributed in the hope that it will be
        useful, but WITHOUT ANY WARRANTY; without even the implied
        warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
        PURPOSE. See the GNU Lesser General Public License for more
        details.
 
        You should have received a copy of the GNU Lesser General
        Public License along with this source; if not, download it
        from http://www.opencores.org/lgpl.shtml.
*/
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all;          --TODO just use axiTransactor here as transactor should already be wrapped up.
 
/* TODO remove once generic packages are supported. */
library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
 
/* synthesis translate_off */
library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
/* synthesis translate_on */
 
library altera; use altera.stp;
 
 
entity user is port(
        /* Comment-out for simulation. */
        clk,nReset:in std_ulogic;
 
        /* AXI Master interface */
--      axiMaster_in:in t_axi4StreamTransactor_s2m;
        axiMaster_out:buffer t_axi4StreamTransactor_m2s
 
        /* Debug ports. */
);
end entity user;
 
architecture rtl of user is
        /* Global counters. */
        constant maxSymbols:positive:=2048;             --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width. 
        signal symbolsPerTransfer:t_cnt;
        signal outstandingTransactions:t_cnt;
 
        /* BFM signalling. */
        signal readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
        signal writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
        signal readResponse:t_bfm;
        signal writeResponse:t_bfm;
 
        type txStates is (idle,transmitting);
        signal txFSM,i_txFSM:txStates;
 
        /* Tester signals. */
        /* synthesis translate_off */
        signal clk,nReset:std_ulogic:='0';
        /* synthesis translate_on */
        --signal trigger:boolean;
        signal anlysr_dataIn:std_logic_vector(127 downto 0);
        signal anlysr_trigger:std_ulogic;
 
        /* Signal preservations for SignalTap II probing. */
        --attribute keep:boolean;
        --attribute keep of trigger:signal is true;
 
        signal axiMaster_in:t_axi4StreamTransactor_s2m;
        signal irq_write:std_ulogic;            -- clock gating.
 
begin
        /* Bus functional models. */
        axiMaster: entity work.axiBfmMaster(rtl)
                port map(
                        aclk=>irq_write, n_areset=>nReset,
 
                        readRequest=>readRequest,       writeRequest=>writeRequest,
                        readResponse=>readResponse,     writeResponse=>writeResponse,
                        axiMaster_in=>axiMaster_in,
                        axiMaster_out=>axiMaster_out,
 
                        symbolsPerTransfer=>symbolsPerTransfer,
                        outstandingTransactions=>outstandingTransactions
        );
 
        /* Interrupt-request generator. */
        irq_write<=clk when nReset else '0';
 
        /* Simulation Tester. */
        /* synthesis translate_off */
        clk<=not clk after 10 ps;
        process is begin
                nReset<='1'; wait for 1 ps;
                nReset<='0'; wait for 500 ps;
                nReset<='1';
                wait;
        end process;
        /* synthesis translate_on */
 
        /* Hardware tester. */
        /* directly instantiated if configurations is not used.
                component-instantiated if configurations are used.
        */
--      i_bist: entity work.framer_bist(tc1)
        /*i_bist: entity work.framer_bist(tc2_randomised)
                generic map(interPktGap=>3, pktSize=>pktSize)
                port map(nReset=>nReset, clk=>clk,
                        trigger=>trigger,
                        txDataIn=>txDataIn,
                        txOut=>data(0),
                        dataFault=>dataFault, crcFault=>crcFault
        );
        */
 
        /* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
        --trigger<=clk='1';
        --anlysr_trigger<='1' when trigger else '0';
        anlysr_trigger<='1' when writeRequest.trigger else '0';
 
        /* Disable this for synthesis as this is not currently synthesisable.
                Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
        */
        /* synthesis translate_off */
        --framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);
        /* synthesis translate_on */
 
        anlysr_dataIn(0)<='1' when nReset else '0';
        anlysr_dataIn(1)<='1' when irq_write else '0';
        anlysr_dataIn(2)<='1' when axiMaster_in.tReady else '0';
        anlysr_dataIn(3)<='1' when axiMaster_out.tValid else '0';
        anlysr_dataIn(67 downto 4)<=std_logic_vector(axiMaster_out.tData);
        anlysr_dataIn(71 downto 68)<=std_logic_vector(axiMaster_out.tStrb);
        anlysr_dataIn(75 downto 72)<=std_logic_vector(axiMaster_out.tKeep);
        anlysr_dataIn(76)<='1' when axiMaster_out.tLast else '0';
        --anlysr_dataIn(2)<='1' when axiMaster_out.tValid else '0';
        anlysr_dataIn(77)<='1' when writeRequest.trigger else '0';
 
        anlysr_dataIn(anlysr_dataIn'high downto 78)<=(others=>'0');
 
 
        /* Simulate only if you have compiled Altera's simulation libraries. */
        i_bistFramer_stp_analyser: entity altera.stp(syn) port map(
                acq_clk=>clk,
                acq_data_in=>anlysr_dataIn,
                acq_trigger_in=>"1",
                trigger_in=>anlysr_trigger
        );
 
 
 
        /* Stimuli sequencer. TODO move to tester/stimuli.
                This emulates the AXI4-Stream Slave.
        */
        /* Simulation-only stimuli sequencer. */
        /* synthesis translate_off */
        process is begin
                /* Fast read. */
                while not axiMaster_out.tLast loop
                        /* Wait for tValid to assert. */
                        while not axiMaster_out.tValid loop
                                wait until falling_edge(clk);
                        end loop;
 
                        axiMaster_in.tReady<=true;
 
                        wait until falling_edge(clk);
                        axiMaster_in.tReady<=false;
                end loop;
 
                wait until falling_edge(clk);
 
                /* Normal read. */
                while not axiMaster_out.tLast loop
                        /* Wait for tValid to assert. */
                        while not axiMaster_out.tValid loop
                                wait until falling_edge(clk);
                        end loop;
 
                        wait until falling_edge(clk);
                        axiMaster_in.tReady<=true;
 
                        wait until falling_edge(clk);
                        axiMaster_in.tReady<=false;
                end loop;
 
                for i in 0 to 10 loop
                        wait until falling_edge(clk);
                end loop;
 
                /* One-shot read. */
                axiMaster_in.tReady<=true;
 
                wait until falling_edge(clk);
                axiMaster_in.tReady<=false;
 
                wait;
        end process;
        /* synthesis translate_on */
 
        /* Synthesisable stimuli sequencer. */
        axiMaster_in.tReady<=true when axiMaster_out.tValid and falling_edge(clk);
 
        /* Data transmitter. */
        sequencer: process(nReset,irq_write) is
                /* Local procedures to map BFM signals with the package procedure. */
                procedure read(address:in t_addr) is begin
                        read(readRequest,address);
                end procedure read;
 
                procedure write(data:in t_msg) is begin
                        write(request=>writeRequest, address=>(others=>'-'), data=>data);
                end procedure write;
 
                variable isPktError:boolean;
 
                /* Tester variables. */
                /* Synthesis-only randomisation. */
                variable rand0:signed(63 downto 0);
                /* Simulation-only randomisation. */
                /* synthesis translate_off */
                variable rv0:RandomPType;
                /* synthesis translate_on */
 
        begin
                if not nReset then
                        /* synthesis only. */
                        rand0:=(others=>'0');
 
                        /* simulation only. */
                        /* synthesis translate_off */
                        rv0.InitSeed(rv0'instance_name);
                        /* synthesis translate_on */
 
                        txFSM<=idle;
                elsif falling_edge(irq_write) then
                        case txFSM is
                                when idle=>
                                        if outstandingTransactions>0 then
                                                /* synthesis translate_off */
                                                write(rv0.RandSigned(axiMaster_out.tData'length));
                                                /* synthesis translate_on */
                                                write(rand0);
 
                                                txFSM<=transmitting;
                                        end if;
                                when transmitting=>
                                        if writeResponse.trigger then
                                                /* synthesis translate_off */
                                                write(rv0.RandSigned(axiMaster_out.tData'length));
                                                /* synthesis translate_on */
                                                write(rand0);
                                                rand0:=rand0+1;
                                        end if;
 
                                        if axiMaster_out.tLast then
                                                txFSM<=idle;
                                        end if;
                                when others=>null;
                        end case;
                end if;
        end process sequencer;
 
        /* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
        process(nReset,irq_write) is
                /* synthesis translate_off */
                variable rv0:RandomPType;
                /* synthesis translate_on */
        begin
                if not nReset then
                        /* synthesis translate_off */
                        rv0.InitSeed(rv0'instance_name);
                        symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
                        report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
                        /* synthesis translate_on */
 
                        symbolsPerTransfer<=128x"8";
                elsif rising_edge(irq_write) then
                        if axiMaster_out.tLast then
                                /* synthesis only. */
                                /* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
                                --symbolsPerTransfer<=(others=>'0');
 
                                /* Testcase 2: number of symbols per transfer is randomised. */
                                --uniform(seed0,seed1,rand0);
                                --symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8);  --symbolsPerTransfer'length
                                --report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8));       --axiMaster_out.tData'length));
 
 
                                /* synthesis translate_off */
                                symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
                                report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
                                /* synthesis translate_on */
 
                                symbolsPerTransfer<=128x"8";
                        end if;
                end if;
        end process;
end architecture rtl;

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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] [user.vhdl] - Blame information for rev 11

Line No.	Rev	Author	Line
1	9	daniel.kho	`/*`
2			`This file is part of the AXI4 Transactor and Bus Functional Model`
3			`(axi4_tlm_bfm) project:`
4			`http://www.opencores.org/project,axi4_tlm_bfm`
5
6			`Description`
7			`Synthesisable use case for AXI4 on-chip messaging.`
8
9			`To Do:`
10
11			`Author(s):`
12			`- Daniel C.K. Kho, daniel.kho@opencores.org \| daniel.kho@tauhop.com`
13
14			`Copyright (C) 2012-2013 Authors and OPENCORES.ORG`
15
16			`This source file may be used and distributed without`
17			`restriction provided that this copyright statement is not`
18			`removed from the file and that any derivative work contains`
19			`the original copyright notice and the associated disclaimer.`
20
21			`This source file is free software; you can redistribute it`
22			`and/or modify it under the terms of the GNU Lesser General`
23			`Public License as published by the Free Software Foundation;`
24			`either version 2.1 of the License, or (at your option) any`
25			`later version.`
26
27			`This source is distributed in the hope that it will be`
28			`useful, but WITHOUT ANY WARRANTY; without even the implied`
29			`warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
30			`PURPOSE. See the GNU Lesser General Public License for more`
31			`details.`
32
33			`You should have received a copy of the GNU Lesser General`
34			`Public License along with this source; if not, download it`
35			`from http://www.opencores.org/lgpl.shtml.`
36			`*/`
37			`library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;`
38			`--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.`
39
40			`/* TODO remove once generic packages are supported. */`
41			`library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;`
42
43			`/* synthesis translate_off */`
44			`library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;`
45			`/* synthesis translate_on */`
46
47			`library altera; use altera.stp;`
48
49
50			`entity user is port(`
51			`/* Comment-out for simulation. */`
52			`clk,nReset:in std_ulogic;`
53
54			`/* AXI Master interface */`
55			`-- axiMaster_in:in t_axi4StreamTransactor_s2m;`
56			`axiMaster_out:buffer t_axi4StreamTransactor_m2s`
57
58			`/* Debug ports. */`
59			`);`
60			`end entity user;`
61
62			`architecture rtl of user is`
63			`/* Global counters. */`
64			`constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.`
65			`signal symbolsPerTransfer:t_cnt;`
66			`signal outstandingTransactions:t_cnt;`
67
68			`/* BFM signalling. */`
69	11	daniel.kho	`signal readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);`
70			`signal writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);`
71			`signal readResponse:t_bfm;`
72			`signal writeResponse:t_bfm;`
73	9	daniel.kho
74	11	daniel.kho	`type txStates is (idle,transmitting);`
75			`signal txFSM,i_txFSM:txStates;`
76	9	daniel.kho
77			`/* Tester signals. */`
78			`/* synthesis translate_off */`
79			`signal clk,nReset:std_ulogic:='0';`
80			`/* synthesis translate_on */`
81	11	daniel.kho	`--signal trigger:boolean;`
82	9	daniel.kho	`signal anlysr_dataIn:std_logic_vector(127 downto 0);`
83			`signal anlysr_trigger:std_ulogic;`
84
85			`/* Signal preservations for SignalTap II probing. */`
86	11	daniel.kho	`--attribute keep:boolean;`
87			`--attribute keep of trigger:signal is true;`
88	9	daniel.kho
89			`signal axiMaster_in:t_axi4StreamTransactor_s2m;`
90			`signal irq_write:std_ulogic; -- clock gating.`
91
92			`begin`
93			`/* Bus functional models. */`
94			`axiMaster: entity work.axiBfmMaster(rtl)`
95			`port map(`
96			`aclk=>irq_write, n_areset=>nReset,`
97
98			`readRequest=>readRequest, writeRequest=>writeRequest,`
99			`readResponse=>readResponse, writeResponse=>writeResponse,`
100			`axiMaster_in=>axiMaster_in,`
101			`axiMaster_out=>axiMaster_out,`
102
103			`symbolsPerTransfer=>symbolsPerTransfer,`
104			`outstandingTransactions=>outstandingTransactions`
105			`);`
106
107			`/* Interrupt-request generator. */`
108			`irq_write<=clk when nReset else '0';`
109
110			`/* Simulation Tester. */`
111			`/* synthesis translate_off */`
112			`clk<=not clk after 10 ps;`
113			`process is begin`
114			`nReset<='1'; wait for 1 ps;`
115			`nReset<='0'; wait for 500 ps;`
116			`nReset<='1';`
117			`wait;`
118			`end process;`
119			`/* synthesis translate_on */`
120
121			`/* Hardware tester. */`
122			`/* directly instantiated if configurations is not used.`
123			`component-instantiated if configurations are used.`
124			`*/`
125			`-- i_bist: entity work.framer_bist(tc1)`
126			`/*i_bist: entity work.framer_bist(tc2_randomised)`
127			`generic map(interPktGap=>3, pktSize=>pktSize)`
128			`port map(nReset=>nReset, clk=>clk,`
129			`trigger=>trigger,`
130			`txDataIn=>txDataIn,`
131			`txOut=>data(0),`
132			`dataFault=>dataFault, crcFault=>crcFault`
133			`);`
134			`*/`
135
136			`/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */`
137			`--trigger<=clk='1';`
138			`--anlysr_trigger<='1' when trigger else '0';`
139			`anlysr_trigger<='1' when writeRequest.trigger else '0';`
140
141			`/* Disable this for synthesis as this is not currently synthesisable.`
142			`Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.`
143			`*/`
144			`/* synthesis translate_off */`
145			`--framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);`
146			`/* synthesis translate_on */`
147
148			`anlysr_dataIn(0)<='1' when nReset else '0';`
149			`anlysr_dataIn(1)<='1' when irq_write else '0';`
150			`anlysr_dataIn(2)<='1' when axiMaster_in.tReady else '0';`
151			`anlysr_dataIn(3)<='1' when axiMaster_out.tValid else '0';`
152			`anlysr_dataIn(67 downto 4)<=std_logic_vector(axiMaster_out.tData);`
153			`anlysr_dataIn(71 downto 68)<=std_logic_vector(axiMaster_out.tStrb);`
154			`anlysr_dataIn(75 downto 72)<=std_logic_vector(axiMaster_out.tKeep);`
155			`anlysr_dataIn(76)<='1' when axiMaster_out.tLast else '0';`
156			`--anlysr_dataIn(2)<='1' when axiMaster_out.tValid else '0';`
157			`anlysr_dataIn(77)<='1' when writeRequest.trigger else '0';`
158
159			`anlysr_dataIn(anlysr_dataIn'high downto 78)<=(others=>'0');`
160
161
162			`/* Simulate only if you have compiled Altera's simulation libraries. */`
163			`i_bistFramer_stp_analyser: entity altera.stp(syn) port map(`
164			`acq_clk=>clk,`
165			`acq_data_in=>anlysr_dataIn,`
166			`acq_trigger_in=>"1",`
167			`trigger_in=>anlysr_trigger`
168			`);`
169
170
171
172	11	daniel.kho	`/* Stimuli sequencer. TODO move to tester/stimuli.`
173			`This emulates the AXI4-Stream Slave.`
174			`*/`
175			`/* Simulation-only stimuli sequencer. */`
176			`/* synthesis translate_off */`
177			`process is begin`
178			`/* Fast read. */`
179			`while not axiMaster_out.tLast loop`
180			`/* Wait for tValid to assert. */`
181			`while not axiMaster_out.tValid loop`
182			`wait until falling_edge(clk);`
183			`end loop;`
184
185			`axiMaster_in.tReady<=true;`
186
187			`wait until falling_edge(clk);`
188			`axiMaster_in.tReady<=false;`
189			`end loop;`
190
191			`wait until falling_edge(clk);`
192
193			`/* Normal read. */`
194			`while not axiMaster_out.tLast loop`
195			`/* Wait for tValid to assert. */`
196			`while not axiMaster_out.tValid loop`
197			`wait until falling_edge(clk);`
198			`end loop;`
199
200			`wait until falling_edge(clk);`
201			`axiMaster_in.tReady<=true;`
202
203			`wait until falling_edge(clk);`
204			`axiMaster_in.tReady<=false;`
205			`end loop;`
206
207			`for i in 0 to 10 loop`
208			`wait until falling_edge(clk);`
209			`end loop;`
210
211			`/* One-shot read. */`
212			`axiMaster_in.tReady<=true;`
213
214			`wait until falling_edge(clk);`
215			`axiMaster_in.tReady<=false;`
216
217			`wait;`
218			`end process;`
219			`/* synthesis translate_on */`
220
221			`/* Synthesisable stimuli sequencer. */`
222	9	daniel.kho	`axiMaster_in.tReady<=true when axiMaster_out.tValid and falling_edge(clk);`
223
224	11	daniel.kho	`/* Data transmitter. */`
225	9	daniel.kho	`sequencer: process(nReset,irq_write) is`
226			`/* Local procedures to map BFM signals with the package procedure. */`
227			`procedure read(address:in t_addr) is begin`
228			`read(readRequest,address);`
229			`end procedure read;`
230
231			`procedure write(data:in t_msg) is begin`
232			`write(request=>writeRequest, address=>(others=>'-'), data=>data);`
233			`end procedure write;`
234
235			`variable isPktError:boolean;`
236
237			`/* Tester variables. */`
238			`/* Synthesis-only randomisation. */`
239			`variable rand0:signed(63 downto 0);`
240			`/* Simulation-only randomisation. */`
241			`/* synthesis translate_off */`
242	11	daniel.kho	`variable rv0:RandomPType;`
243	9	daniel.kho	`/* synthesis translate_on */`
244
245			`begin`
246			`if not nReset then`
247			`/* synthesis only. */`
248			`rand0:=(others=>'0');`
249
250			`/* simulation only. */`
251			`/* synthesis translate_off */`
252			`rv0.InitSeed(rv0'instance_name);`
253	11	daniel.kho	`/* synthesis translate_on */`
254
255			`txFSM<=idle;`
256			`elsif falling_edge(irq_write) then`
257			`case txFSM is`
258			`when idle=>`
259			`if outstandingTransactions>0 then`
260			`/* synthesis translate_off */`
261			`write(rv0.RandSigned(axiMaster_out.tData'length));`
262			`/* synthesis translate_on */`
263			`write(rand0);`
264
265			`txFSM<=transmitting;`
266			`end if;`
267			`when transmitting=>`
268			`if writeResponse.trigger then`
269			`/* synthesis translate_off */`
270			`write(rv0.RandSigned(axiMaster_out.tData'length));`
271			`/* synthesis translate_on */`
272			`write(rand0);`
273			`rand0:=rand0+1;`
274			`end if;`
275
276			`if axiMaster_out.tLast then`
277			`txFSM<=idle;`
278			`end if;`
279			`when others=>null;`
280			`end case;`
281			`end if;`
282			`end process sequencer;`
283
284			`/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */`
285			`process(nReset,irq_write) is`
286			`/* synthesis translate_off */`
287			`variable rv0:RandomPType;`
288			`/* synthesis translate_on */`
289			`begin`
290			`if not nReset then`
291			`/* synthesis translate_off */`
292			`rv0.InitSeed(rv0'instance_name);`
293	9	daniel.kho	`symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);`
294	11	daniel.kho	`report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));`
295	9	daniel.kho	`/* synthesis translate_on */`
296	11	daniel.kho
297			`symbolsPerTransfer<=128x"8";`
298			`elsif rising_edge(irq_write) then`
299			`if axiMaster_out.tLast then`
300	9	daniel.kho	`/* synthesis only. */`
301			`/* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */`
302			`--symbolsPerTransfer<=(others=>'0');`
303
304			`/* Testcase 2: number of symbols per transfer is randomised. */`
305			`--uniform(seed0,seed1,rand0);`
306			`--symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length`
307			`--report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));`
308
309	11	daniel.kho
310	9	daniel.kho	`/* synthesis translate_off */`
311	11	daniel.kho	`symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);`
312	9	daniel.kho	`report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));`
313			`/* synthesis translate_on */`
314	11	daniel.kho
315			`symbolsPerTransfer<=128x"8";`
316	9	daniel.kho	`end if;`
317			`end if;`
318	11	daniel.kho	`end process;`
319	9	daniel.kho	`end architecture rtl;`