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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] [user.vhdl] - Blame information for rev 9

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1 9 daniel.kho
/*
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        This file is part of the AXI4 Transactor and Bus Functional Model
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        (axi4_tlm_bfm) project:
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                http://www.opencores.org/project,axi4_tlm_bfm
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        Description
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        Synthesisable use case for AXI4 on-chip messaging.
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        To Do:
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        Author(s):
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        - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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        Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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        This source file may be used and distributed without
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        restriction provided that this copyright statement is not
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        removed from the file and that any derivative work contains
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        the original copyright notice and the associated disclaimer.
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        This source file is free software; you can redistribute it
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        and/or modify it under the terms of the GNU Lesser General
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        Public License as published by the Free Software Foundation;
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        either version 2.1 of the License, or (at your option) any
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        later version.
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        This source is distributed in the hope that it will be
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        useful, but WITHOUT ANY WARRANTY; without even the implied
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        warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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        PURPOSE. See the GNU Lesser General Public License for more
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        details.
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        You should have received a copy of the GNU Lesser General
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        Public License along with this source; if not, download it
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        from http://www.opencores.org/lgpl.shtml.
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
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--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all;          --TODO just use axiTransactor here as transactor should already be wrapped up.
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/* TODO remove once generic packages are supported. */
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library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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/* synthesis translate_off */
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library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
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/* synthesis translate_on */
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library altera; use altera.stp;
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entity user is port(
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        /* Comment-out for simulation. */
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        clk,nReset:in std_ulogic;
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        /* AXI Master interface */
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--      axiMaster_in:in t_axi4StreamTransactor_s2m;
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        axiMaster_out:buffer t_axi4StreamTransactor_m2s
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        /* Debug ports. */
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);
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end entity user;
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architecture rtl of user is
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        /* Global counters. */
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        constant maxSymbols:positive:=2048;             --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width. 
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        signal symbolsPerTransfer:t_cnt;
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        signal outstandingTransactions:t_cnt;
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        /* BFM signalling. */
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        signal readRequest,next_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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        signal writeRequest,next_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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        signal readResponse,next_readResponse:t_bfm;
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        signal writeResponse,next_writeResponse:t_bfm;
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        /* Tester signals. */
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        /* synthesis translate_off */
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        signal clk,nReset:std_ulogic:='0';
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        /* synthesis translate_on */
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        signal trigger:boolean;
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        signal anlysr_dataIn:std_logic_vector(127 downto 0);
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        signal anlysr_trigger:std_ulogic;
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        /* Signal preservations for SignalTap II probing. */
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        attribute keep:boolean;
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        attribute keep of trigger:signal is true;
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        signal axiMaster_in:t_axi4StreamTransactor_s2m;
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        signal irq_write:std_ulogic;            -- clock gating.
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begin
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        /* pipelines. */
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        process(clk) is begin
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                if rising_edge(clk) then
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                        next_readRequest<=readRequest;
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                        next_writeRequest<=writeRequest;
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                        next_readResponse<=readResponse;
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                        next_writeResponse<=writeResponse;
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                end if;
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        end process;
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        /* Bus functional models. */
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        axiMaster: entity work.axiBfmMaster(rtl)
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--              generic map(maxTransactions=>maxSymbols)
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                port map(
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                        aclk=>irq_write, n_areset=>nReset,
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                        trigger=>irq_write='1',
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                        readRequest=>readRequest,       writeRequest=>writeRequest,
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                        readResponse=>readResponse,     writeResponse=>writeResponse,
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                        axiMaster_in=>axiMaster_in,
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                        axiMaster_out=>axiMaster_out,
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                        symbolsPerTransfer=>symbolsPerTransfer,
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                        outstandingTransactions=>outstandingTransactions
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        );
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        /* Interrupt-request generator. */
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        irq_write<=clk when nReset else '0';
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        /* Simulation Tester. */
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        /* synthesis translate_off */
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        clk<=not clk after 10 ps;
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        process is begin
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                nReset<='1'; wait for 1 ps;
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                nReset<='0'; wait for 500 ps;
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                nReset<='1';
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                wait;
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        end process;
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        /* synthesis translate_on */
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        /* Hardware tester. */
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        /* directly instantiated if configurations is not used.
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                component-instantiated if configurations are used.
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        */
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--      i_bist: entity work.framer_bist(tc1)
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        /*i_bist: entity work.framer_bist(tc2_randomised)
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                generic map(interPktGap=>3, pktSize=>pktSize)
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                port map(nReset=>nReset, clk=>clk,
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                        trigger=>trigger,
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                        txDataIn=>txDataIn,
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                        txOut=>data(0),
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                        dataFault=>dataFault, crcFault=>crcFault
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        );
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        */
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        /* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
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        --trigger<=clk='1';
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        --anlysr_trigger<='1' when trigger else '0';
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        anlysr_trigger<='1' when writeRequest.trigger else '0';
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        /* Disable this for synthesis as this is not currently synthesisable.
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                Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
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        */
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        /* synthesis translate_off */
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        --framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);
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        /* synthesis translate_on */
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        anlysr_dataIn(0)<='1' when nReset else '0';
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        anlysr_dataIn(1)<='1' when irq_write else '0';
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        anlysr_dataIn(2)<='1' when axiMaster_in.tReady else '0';
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        anlysr_dataIn(3)<='1' when axiMaster_out.tValid else '0';
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        anlysr_dataIn(67 downto 4)<=std_logic_vector(axiMaster_out.tData);
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        anlysr_dataIn(71 downto 68)<=std_logic_vector(axiMaster_out.tStrb);
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        anlysr_dataIn(75 downto 72)<=std_logic_vector(axiMaster_out.tKeep);
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        anlysr_dataIn(76)<='1' when axiMaster_out.tLast else '0';
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        --anlysr_dataIn(2)<='1' when axiMaster_out.tValid else '0';
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        anlysr_dataIn(77)<='1' when writeRequest.trigger else '0';
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        anlysr_dataIn(anlysr_dataIn'high downto 78)<=(others=>'0');
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        /* Simulate only if you have compiled Altera's simulation libraries. */
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        i_bistFramer_stp_analyser: entity altera.stp(syn) port map(
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                acq_clk=>clk,
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                acq_data_in=>anlysr_dataIn,
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                acq_trigger_in=>"1",
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                trigger_in=>anlysr_trigger
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        );
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        /* Stimuli sequencer. */
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        axiMaster_in.tReady<=true when axiMaster_out.tValid and falling_edge(clk);
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186
        sequencer: process(nReset,irq_write) is
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                /* Local procedures to map BFM signals with the package procedure. */
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                procedure read(address:in t_addr) is begin
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                        read(readRequest,address);
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                end procedure read;
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                procedure write(data:in t_msg) is begin
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                        write(request=>writeRequest, address=>(others=>'-'), data=>data);
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                end procedure write;
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                variable isPktError:boolean;
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                /* Tester variables. */
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                /* Synthesis-only randomisation. */
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                variable seed0,seed1:positive:=1;
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                --variable rand0:real;
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                variable rand0:signed(63 downto 0);
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                /* Simulation-only randomisation. */
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                /* synthesis translate_off */
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                variable rv0,rv1:RandomPType;
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                /* synthesis translate_on */
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        begin
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                if not nReset then
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                        /* synthesis only. */
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                        seed0:=1; seed1:=1;
212
                        --uniform(seed0,seed1,rand0);
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                        rand0:=(others=>'0');
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                        --symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8);
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                        symbolsPerTransfer<=128x"8";
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                        /* simulation only. */
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                        /* synthesis translate_off */
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                        rv0.InitSeed(rv0'instance_name);
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                        rv1.InitSeed(rv1'instance_name);
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                        symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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                        /* synthesis translate_on */
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                elsif falling_edge(irq_write) then
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                        --write(64x"abcd1234");
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                        if outstandingTransactions>0 then
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                                /* synthesis only. */
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                                --uniform(seed0,seed1,rand0);
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                                --write(to_signed(integer(rand0 * 2.0**31),64));
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                                write(rand0);
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                                rand0:=rand0+1;
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234
                                /* simulation only. */
235
                                /* synthesis translate_off */
236
                                write(rv1.RandUnsigned(axiMaster_out.tData'length));
237
                                /* synthesis translate_on */
238
                        else
239
                                /* synthesis only. */
240
                                /* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
241
                                --symbolsPerTransfer<=(others=>'0');
242
 
243
                                /* Testcase 2: number of symbols per transfer is randomised. */
244
                                --uniform(seed0,seed1,rand0);
245
                                --symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8);  --symbolsPerTransfer'length
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                                --report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8));       --axiMaster_out.tData'length));
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                                symbolsPerTransfer<=128x"8";
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249
 
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                                /* Truncate symbolsPerTransfer to 8 bits, so that it uses a "small" value for simulation. */
251
                                /* simulation only. */
252
                                /* synthesis translate_off */
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                                symbolsPerTransfer<=120x"0" & rv0.RandSigned(64);
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                                report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
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                                /* synthesis translate_on */
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                        end if;
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                end if;
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        end process sequencer;
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end architecture rtl;

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