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/*
        This file is part of the AXI4 Transactor and Bus Functional Model
        (axi4_tlm_bfm) project:
                http://www.opencores.org/project,axi4_tlm_bfm
 
        Description
        Synthesisable use case for AXI4 on-chip messaging.
 
        To Do:
 
        Author(s):
        - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
 
        Copyright (C) 2012-2013 Authors and OPENCORES.ORG
 
        This source file may be used and distributed without
        restriction provided that this copyright statement is not
        removed from the file and that any derivative work contains
        the original copyright notice and the associated disclaimer.
 
        This source file is free software; you can redistribute it
        and/or modify it under the terms of the GNU Lesser General
        Public License as published by the Free Software Foundation;
        either version 2.1 of the License, or (at your option) any
        later version.
 
        This source is distributed in the hope that it will be
        useful, but WITHOUT ANY WARRANTY; without even the implied
        warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
        PURPOSE. See the GNU Lesser General Public License for more
        details.
 
        You should have received a copy of the GNU Lesser General
        Public License along with this source; if not, download it
        from http://www.opencores.org/lgpl.shtml.
*/
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
library tauhop; use tauhop.axiTransactor.all;
 
/* TODO remove once generic packages are supported. */
--library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
 
/* synthesis translate_off */
library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
/* synthesis translate_on */
 
entity user is port(
        /* Comment-out for simulation. */
--      clk,nReset:in std_ulogic;
 
        /* AXI Master interface */
--      axiMaster_in:in t_axi4StreamTransactor_s2m;
        axiMaster_out:buffer t_axi4StreamTransactor_m2s
 
        /* Debug ports. */
);
end entity user;
 
architecture rtl of user is
        signal reset:std_ulogic:='0';
        signal porCnt:unsigned(3 downto 0);
        signal trigger:boolean;
 
        /* Global counters. */
        constant maxSymbols:positive:=2048;             --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width. 
        signal symbolsPerTransfer:i_transactor.t_cnt;
        signal outstandingTransactions:i_transactor.t_cnt;
 
        /* BFM signalling. */
        signal readRequest,writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
        signal readResponse,writeResponse:i_transactor.t_bfm;
 
        type txStates is (idle,transmitting);
        signal txFSM,i_txFSM:txStates;
 
        /* Tester signals. */
        /* synthesis translate_off */
        signal clk,nReset:std_ulogic:='0';
        attribute period:time; attribute period of clk:signal is 10 ps;
        /* synthesis translate_on */
 
        signal axiMaster_in:t_axi4StreamTransactor_s2m;
        signal irq_write:std_ulogic;            -- clock gating.
 
        signal prbs:i_transactor.t_msg;
 
begin
        /* Bus functional models. */
        axiMaster: entity tauhop.axiBfmMaster(rtl)
        --axiMaster: entity work.axiBfmMaster(simulation)
                port map(
                        aclk=>irq_write, n_areset=>not reset,
 
                        readRequest=>readRequest,       writeRequest=>writeRequest,
                        readResponse=>readResponse,     writeResponse=>writeResponse,
                        axiMaster_in=>axiMaster_in,
                        axiMaster_out=>axiMaster_out,
 
                        symbolsPerTransfer=>symbolsPerTransfer,
                        outstandingTransactions=>outstandingTransactions
        );
 
        /* Interrupt-request generator. */
        trigger<=txFSM/=i_txFSM or writeResponse.trigger;
        irq_write<=clk when not reset else '0';
 
        /* Simulation Tester. */
        /* synthesis translate_off */
        clk<=not clk after clk'period/2;
        process is begin
                nReset<='1'; wait for 1 ps;
                nReset<='0'; wait for 500 ps;
                nReset<='1';
                wait;
        end process;
        /* synthesis translate_on */
 
 
        /* Hardware tester. */
        /* Power-on Reset circuitry. */
        por: process(nReset,clk) is begin
                if not nReset then reset<='1'; porCnt<=(others=>'1');
                elsif rising_edge(clk) then
                        reset<='0';
 
                        if porCnt>0 then reset<='1'; porCnt<=porCnt-1; end if;
                end if;
        end process por;
 
/*
        process is
                alias trigger is <<signal axiMaster.trigger:boolean>>;
                alias axiTxState is <<signal axiMaster.next_axiTxState:axiBfmStatesTx>>;
        begin
                -- Remove this assertion once request queue has been implemented.
                if trigger then
                        assert axiTxState=idle or axiTxState=payload report "[Error]: Trigger occurs when FSM is not in IDLE or PAYLOAD state." severity error;
                end if;
                wait for clk'period/10;
        end process;
*/
 
        /* Stimuli sequencer. TODO move to tester/stimuli.
                This emulates the AXI4-Stream Slave.
        */
        /* Simulation-only stimuli sequencer. */
        /* synthesis translate_off */
        process is begin
                report "Performing fast read..." severity note;
 
                /* Fast read. */
                while not axiMaster_out.tLast loop
                        /* Wait for tValid to assert. */
                        while not axiMaster_out.tValid loop
                                wait until falling_edge(clk);
                        end loop;
 
                        axiMaster_in.tReady<=true;
 
                        wait until falling_edge(clk);
                        axiMaster_in.tReady<=false;
                end loop;
 
                report "Completed fast read..." severity note;
 
 
                wait until falling_edge(clk);
                report "Performing normal read..." severity note;
 
                /* Normal read. */
                while not axiMaster_out.tLast loop
                        /* Wait for tValid to assert. */
                        while not axiMaster_out.tValid loop
                                wait until falling_edge(clk);
                        end loop;
 
                        wait until falling_edge(clk);
                        axiMaster_in.tReady<=true;
 
                        wait until falling_edge(clk);
                        axiMaster_in.tReady<=false;
 
                        wait until falling_edge(clk);
                end loop;
 
                report "Completed normal read." severity note;
 
 
                wait until falling_edge(clk);
                report "Performing slow read..." severity note;
 
                /* Slow read. */
                while not axiMaster_out.tLast loop
                        /* Wait for tValid to assert. */
                        while not axiMaster_out.tValid loop
                                wait until falling_edge(clk);
                        end loop;
 
                        wait until falling_edge(clk);
                        wait until falling_edge(clk);
                        axiMaster_in.tReady<=true;
 
                        wait until falling_edge(clk);
                        axiMaster_in.tReady<=false;
 
                        wait until falling_edge(clk);
                end loop;
 
                report "Completed slow read." severity note;
 
 
                for i in 0 to 10 loop
                        wait until falling_edge(clk);
                end loop;
                report "Performing one-shot read..." severity note;
 
                /* One-shot read. */
                axiMaster_in.tReady<=true;
 
                wait until falling_edge(clk);
                axiMaster_in.tReady<=false;
 
                report "Completed one-shot read." severity note;
 
                wait;
        end process;
        /* synthesis translate_on */
 
        /* Synthesisable stimuli sequencer. */
 
 
        /* Data transmitter. */
        i_prbs: entity tauhop.prbs31(rtl)
                generic map(
                        isParallelLoad=>true,
                        tapVector=>(
                                /* Example polynomial from Wikipedia:
                                        http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
                                */
                                0|3|31=>true, 1|2|30 downto 4=>false
                        )
                )
                port map(
                        /* Comment-out for simulation. */
                        clk=>irq_write, reset=>reset,
                        en=>trigger,
                        seed=>32x"ace1",        --9x"57",
                        prbs=>prbs
                );
 
        sequencer_ns: process(all) is begin
                txFSM<=i_txFSM;
                if reset then txFSM<=idle;
                else
                        case i_txFSM is
                                when idle=>
                                        if outstandingTransactions>0 then txFSM<=transmitting; end if;
                                when transmitting=>
                                        if axiMaster_out.tLast then
                                                txFSM<=idle;
                                        end if;
                                when others=> null;
                        end case;
                end if;
        end process sequencer_ns;
 
        sequencer_op: process(reset,irq_write) is
                /* Local procedures to map BFM signals with the package procedure. */
                procedure read(address:in i_transactor.t_addr) is begin
                        i_transactor.read(readRequest,address);
                end procedure read;
 
                procedure write(data:in i_transactor.t_msg) is begin
                        i_transactor.write(request=>writeRequest, address=>(others=>'-'), data=>data);
                end procedure write;
 
                variable isPktError:boolean;
 
                /* Tester variables. */
                /* Synthesis-only randomisation. */
 
                /* Simulation-only randomisation. */
                /* synthesis translate_off */
                variable rv0:RandomPType;
                /* synthesis translate_on */
 
        begin
--              if reset then
                        /* simulation only. */
                        /* synthesis translate_off */
--                      rv0.InitSeed(rv0'instance_name);
                        /* synthesis translate_on */
--              elsif falling_edge(irq_write) then
                if falling_edge(irq_write) then
                        case txFSM is
                                when transmitting=>
                                        if trigger then
                                                /* synthesis translate_off */
--                                              write(rv0.RandSigned(axiMaster_out.tData'length));
                                                /* synthesis translate_on */
                                                write(prbs);
                                        end if;
                                when others=>null;
                        end case;
                end if;
        end process sequencer_op;
 
        sequencer_regs: process(irq_write) is begin
                if falling_edge(irq_write) then
                        i_txFSM<=txFSM;
                end if;
        end process sequencer_regs;
 
        /* Transaction counter. */
        process(reset,symbolsPerTransfer,irq_write) is begin
                if reset then outstandingTransactions<=symbolsPerTransfer;
                elsif rising_edge(irq_write) then
                        if not axiMaster_out.tLast then
                                if outstandingTransactions<1 then
                                        outstandingTransactions<=symbolsPerTransfer;
                                        report "No more pending transactions." severity note;
                                elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
                                end if;
                        end if;
 
                        /* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */
                        if reset then outstandingTransactions<=symbolsPerTransfer; end if;
                end if;
        end process;
 
        /* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
        process(reset,irq_write) is
                /* synthesis translate_off */
                variable rv0:RandomPType;
                /* synthesis translate_on */
        begin
                if reset then
                        /* synthesis translate_off */
                        rv0.InitSeed(rv0'instance_name);
                        symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
                        report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
                        /* synthesis translate_on */
                elsif rising_edge(irq_write) then
                        if axiMaster_out.tLast then
                                /* synthesis translate_off */
                                symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
                                report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
                                /* synthesis translate_on */
                        end if;
                end if;
        end process;
end architecture rtl;

Line No.	Rev	Author	Line
1	2	daniel.kho	`/*`
2			`This file is part of the AXI4 Transactor and Bus Functional Model`
3			`(axi4_tlm_bfm) project:`
4			`http://www.opencores.org/project,axi4_tlm_bfm`
5
6			`Description`
7			`Synthesisable use case for AXI4 on-chip messaging.`
8
9			`To Do:`
10
11			`Author(s):`
12			`- Daniel C.K. Kho, daniel.kho@opencores.org \| daniel.kho@tauhop.com`
13
14			`Copyright (C) 2012-2013 Authors and OPENCORES.ORG`
15
16			`This source file may be used and distributed without`
17			`restriction provided that this copyright statement is not`
18			`removed from the file and that any derivative work contains`
19			`the original copyright notice and the associated disclaimer.`
20
21			`This source file is free software; you can redistribute it`
22			`and/or modify it under the terms of the GNU Lesser General`
23			`Public License as published by the Free Software Foundation;`
24			`either version 2.1 of the License, or (at your option) any`
25			`later version.`
26
27			`This source is distributed in the hope that it will be`
28			`useful, but WITHOUT ANY WARRANTY; without even the implied`
29			`warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
30			`PURPOSE. See the GNU Lesser General Public License for more`
31			`details.`
32
33			`You should have received a copy of the GNU Lesser General`
34			`Public License along with this source; if not, download it`
35			`from http://www.opencores.org/lgpl.shtml.`
36			`*/`
37	3	daniel.kho	`library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;`
38	12	daniel.kho	`library tauhop; use tauhop.axiTransactor.all;`
39	11	daniel.kho
40			`/* TODO remove once generic packages are supported. */`
41			`--library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;`
42
43	9	daniel.kho	`/* synthesis translate_off */`
44			`library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;`
45			`/* synthesis translate_on */`
46	2	daniel.kho
47			`entity user is port(`
48			`/* Comment-out for simulation. */`
49	11	daniel.kho	`-- clk,nReset:in std_ulogic;`
50	2	daniel.kho
51			`/* AXI Master interface */`
52	5	daniel.kho	`-- axiMaster_in:in t_axi4StreamTransactor_s2m;`
53			`axiMaster_out:buffer t_axi4StreamTransactor_m2s`
54	2	daniel.kho
55			`/* Debug ports. */`
56			`);`
57			`end entity user;`
58
59			`architecture rtl of user is`
60	17	daniel.kho	`signal reset:std_ulogic:='0';`
61			`signal porCnt:unsigned(3 downto 0);`
62			`signal trigger:boolean;`
63
64	2	daniel.kho	`/* Global counters. */`
65			`constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.`
66	12	daniel.kho	`signal symbolsPerTransfer:i_transactor.t_cnt;`
67			`signal outstandingTransactions:i_transactor.t_cnt;`
68	2	daniel.kho
69			`/* BFM signalling. */`
70	15	daniel.kho	`signal readRequest,writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);`
71			`signal readResponse,writeResponse:i_transactor.t_bfm;`
72	2	daniel.kho
73	10	daniel.kho	`type txStates is (idle,transmitting);`
74			`signal txFSM,i_txFSM:txStates;`
75	2	daniel.kho
76			`/* Tester signals. */`
77			`/* synthesis translate_off */`
78	11	daniel.kho	`signal clk,nReset:std_ulogic:='0';`
79	17	daniel.kho	`attribute period:time; attribute period of clk:signal is 10 ps;`
80	2	daniel.kho	`/* synthesis translate_on */`
81
82	11	daniel.kho	`signal axiMaster_in:t_axi4StreamTransactor_s2m;`
83	2	daniel.kho	`signal irq_write:std_ulogic; -- clock gating.`
84
85	17	daniel.kho	`signal prbs:i_transactor.t_msg;`
86
87	2	daniel.kho	`begin`
88			`/* Bus functional models. */`
89	17	daniel.kho	`axiMaster: entity tauhop.axiBfmMaster(rtl)`
90			`--axiMaster: entity work.axiBfmMaster(simulation)`
91	2	daniel.kho	`port map(`
92	17	daniel.kho	`aclk=>irq_write, n_areset=>not reset,`
93	2	daniel.kho
94			`readRequest=>readRequest, writeRequest=>writeRequest,`
95			`readResponse=>readResponse, writeResponse=>writeResponse,`
96			`axiMaster_in=>axiMaster_in,`
97			`axiMaster_out=>axiMaster_out,`
98
99			`symbolsPerTransfer=>symbolsPerTransfer,`
100	8	daniel.kho	`outstandingTransactions=>outstandingTransactions`
101	2	daniel.kho	`);`
102
103	9	daniel.kho	`/* Interrupt-request generator. */`
104	17	daniel.kho	`trigger<=txFSM/=i_txFSM or writeResponse.trigger;`
105			`irq_write<=clk when not reset else '0';`
106	9	daniel.kho
107	2	daniel.kho	`/* Simulation Tester. */`
108			`/* synthesis translate_off */`
109	17	daniel.kho	`clk<=not clk after clk'period/2;`
110	2	daniel.kho	`process is begin`
111	11	daniel.kho	`nReset<='1'; wait for 1 ps;`
112			`nReset<='0'; wait for 500 ps;`
113			`nReset<='1';`
114	2	daniel.kho	`wait;`
115			`end process;`
116			`/* synthesis translate_on */`
117
118	17	daniel.kho
119	2	daniel.kho	`/* Hardware tester. */`
120	17	daniel.kho	`/* Power-on Reset circuitry. */`
121			`por: process(nReset,clk) is begin`
122			`if not nReset then reset<='1'; porCnt<=(others=>'1');`
123			`elsif rising_edge(clk) then`
124			`reset<='0';`
125
126			`if porCnt>0 then reset<='1'; porCnt<=porCnt-1; end if;`
127			`end if;`
128			`end process por;`
129	2	daniel.kho
130	17	daniel.kho	`/*`
131			`process is`
132			`alias trigger is <<signal axiMaster.trigger:boolean>>;`
133			`alias axiTxState is <<signal axiMaster.next_axiTxState:axiBfmStatesTx>>;`
134			`begin`
135			`-- Remove this assertion once request queue has been implemented.`
136			`if trigger then`
137			`assert axiTxState=idle or axiTxState=payload report "[Error]: Trigger occurs when FSM is not in IDLE or PAYLOAD state." severity error;`
138			`end if;`
139			`wait for clk'period/10;`
140			`end process;`
141			`*/`
142	2	daniel.kho
143	10	daniel.kho	`/* Stimuli sequencer. TODO move to tester/stimuli.`
144			`This emulates the AXI4-Stream Slave.`
145			`*/`
146	11	daniel.kho	`/* Simulation-only stimuli sequencer. */`
147	10	daniel.kho	`/* synthesis translate_off */`
148			`process is begin`
149	17	daniel.kho	`report "Performing fast read..." severity note;`
150
151	10	daniel.kho	`/* Fast read. */`
152			`while not axiMaster_out.tLast loop`
153			`/* Wait for tValid to assert. */`
154			`while not axiMaster_out.tValid loop`
155			`wait until falling_edge(clk);`
156			`end loop;`
157
158			`axiMaster_in.tReady<=true;`
159
160			`wait until falling_edge(clk);`
161			`axiMaster_in.tReady<=false;`
162			`end loop;`
163
164	17	daniel.kho	`report "Completed fast read..." severity note;`
165
166
167	10	daniel.kho	`wait until falling_edge(clk);`
168	17	daniel.kho	`report "Performing normal read..." severity note;`
169	10	daniel.kho
170			`/* Normal read. */`
171			`while not axiMaster_out.tLast loop`
172			`/* Wait for tValid to assert. */`
173			`while not axiMaster_out.tValid loop`
174			`wait until falling_edge(clk);`
175			`end loop;`
176
177			`wait until falling_edge(clk);`
178			`axiMaster_in.tReady<=true;`
179
180			`wait until falling_edge(clk);`
181			`axiMaster_in.tReady<=false;`
182	17	daniel.kho
183			`wait until falling_edge(clk);`
184	10	daniel.kho	`end loop;`
185
186	17	daniel.kho	`report "Completed normal read." severity note;`
187
188
189			`wait until falling_edge(clk);`
190			`report "Performing slow read..." severity note;`
191
192			`/* Slow read. */`
193			`while not axiMaster_out.tLast loop`
194			`/* Wait for tValid to assert. */`
195			`while not axiMaster_out.tValid loop`
196			`wait until falling_edge(clk);`
197			`end loop;`
198
199			`wait until falling_edge(clk);`
200			`wait until falling_edge(clk);`
201			`axiMaster_in.tReady<=true;`
202
203			`wait until falling_edge(clk);`
204			`axiMaster_in.tReady<=false;`
205
206			`wait until falling_edge(clk);`
207			`end loop;`
208
209			`report "Completed slow read." severity note;`
210
211
212	10	daniel.kho	`for i in 0 to 10 loop`
213			`wait until falling_edge(clk);`
214			`end loop;`
215	17	daniel.kho	`report "Performing one-shot read..." severity note;`
216	10	daniel.kho
217			`/* One-shot read. */`
218			`axiMaster_in.tReady<=true;`
219
220			`wait until falling_edge(clk);`
221			`axiMaster_in.tReady<=false;`
222
223	17	daniel.kho	`report "Completed one-shot read." severity note;`
224
225	10	daniel.kho	`wait;`
226			`end process;`
227			`/* synthesis translate_on */`
228	9	daniel.kho
229	11	daniel.kho	`/* Synthesisable stimuli sequencer. */`
230
231
232	10	daniel.kho	`/* Data transmitter. */`
233	17	daniel.kho	`i_prbs: entity tauhop.prbs31(rtl)`
234			`generic map(`
235			`isParallelLoad=>true,`
236			`tapVector=>(`
237			`/* Example polynomial from Wikipedia:`
238			`http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks`
239			`*/`
240			`0\|3\|31=>true, 1\|2\|30 downto 4=>false`
241			`)`
242			`)`
243			`port map(`
244			`/* Comment-out for simulation. */`
245			`clk=>irq_write, reset=>reset,`
246			`en=>trigger,`
247			`seed=>32x"ace1", --9x"57",`
248			`prbs=>prbs`
249			`);`
250
251	13	daniel.kho	`sequencer_ns: process(all) is begin`
252			`txFSM<=i_txFSM;`
253	17	daniel.kho	`if reset then txFSM<=idle;`
254	13	daniel.kho	`else`
255			`case i_txFSM is`
256			`when idle=>`
257			`if outstandingTransactions>0 then txFSM<=transmitting; end if;`
258			`when transmitting=>`
259			`if axiMaster_out.tLast then`
260			`txFSM<=idle;`
261			`end if;`
262			`when others=> null;`
263			`end case;`
264			`end if;`
265			`end process sequencer_ns;`
266
267	17	daniel.kho	`sequencer_op: process(reset,irq_write) is`
268	2	daniel.kho	`/* Local procedures to map BFM signals with the package procedure. */`
269	12	daniel.kho	`procedure read(address:in i_transactor.t_addr) is begin`
270			`i_transactor.read(readRequest,address);`
271	2	daniel.kho	`end procedure read;`
272
273	12	daniel.kho	`procedure write(data:in i_transactor.t_msg) is begin`
274			`i_transactor.write(request=>writeRequest, address=>(others=>'-'), data=>data);`
275	2	daniel.kho	`end procedure write;`
276
277			`variable isPktError:boolean;`
278
279	11	daniel.kho	`/* Tester variables. */`
280	17	daniel.kho	`/* Synthesis-only randomisation. */`
281	11	daniel.kho
282	2	daniel.kho	`/* Simulation-only randomisation. */`
283	11	daniel.kho	`/* synthesis translate_off */`
284	10	daniel.kho	`variable rv0:RandomPType;`
285	11	daniel.kho	`/* synthesis translate_on */`
286	2	daniel.kho
287			`begin`
288	17	daniel.kho	`-- if reset then`
289			`/* simulation only. */`
290	11	daniel.kho	`/* synthesis translate_off */`
291	17	daniel.kho	`-- rv0.InitSeed(rv0'instance_name);`
292	11	daniel.kho	`/* synthesis translate_on */`
293	17	daniel.kho	`-- elsif falling_edge(irq_write) then`
294			`if falling_edge(irq_write) then`
295	10	daniel.kho	`case txFSM is`
296			`when transmitting=>`
297	17	daniel.kho	`if trigger then`
298	11	daniel.kho	`/* synthesis translate_off */`
299	17	daniel.kho	`-- write(rv0.RandSigned(axiMaster_out.tData'length));`
300	11	daniel.kho	`/* synthesis translate_on */`
301	17	daniel.kho	`write(prbs);`
302	10	daniel.kho	`end if;`
303			`when others=>null;`
304			`end case;`
305			`end if;`
306	13	daniel.kho	`end process sequencer_op;`
307	10	daniel.kho
308	13	daniel.kho	`sequencer_regs: process(irq_write) is begin`
309			`if falling_edge(irq_write) then`
310			`i_txFSM<=txFSM;`
311			`end if;`
312			`end process sequencer_regs;`
313
314	16	daniel.kho	`/* Transaction counter. */`
315	17	daniel.kho	`process(reset,symbolsPerTransfer,irq_write) is begin`
316			`if reset then outstandingTransactions<=symbolsPerTransfer;`
317			`elsif rising_edge(irq_write) then`
318			`if not axiMaster_out.tLast then`
319	16	daniel.kho	`if outstandingTransactions<1 then`
320			`outstandingTransactions<=symbolsPerTransfer;`
321			`report "No more pending transactions." severity note;`
322			`elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;`
323			`end if;`
324			`end if;`
325	17	daniel.kho
326			`/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */`
327			`if reset then outstandingTransactions<=symbolsPerTransfer; end if;`
328			`end if;`
329			`end process;`
330	16	daniel.kho
331	10	daniel.kho	`/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */`
332	17	daniel.kho	`process(reset,irq_write) is`
333	11	daniel.kho	`/* synthesis translate_off */`
334	10	daniel.kho	`variable rv0:RandomPType;`
335	11	daniel.kho	`/* synthesis translate_on */`
336	10	daniel.kho	`begin`
337	17	daniel.kho	`if reset then`
338	11	daniel.kho	`/* synthesis translate_off */`
339	10	daniel.kho	`rv0.InitSeed(rv0'instance_name);`
340	9	daniel.kho	`symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);`
341	17	daniel.kho	`report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;`
342	11	daniel.kho	`/* synthesis translate_on */`
343	10	daniel.kho	`elsif rising_edge(irq_write) then`
344			`if axiMaster_out.tLast then`
345	11	daniel.kho	`/* synthesis translate_off */`
346	9	daniel.kho	`symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);`
347	17	daniel.kho	`report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;`
348	11	daniel.kho	`/* synthesis translate_on */`
349	2	daniel.kho	`end if;`
350			`end if;`
351	10	daniel.kho	`end process;`
352	9	daniel.kho	`end architecture rtl;`

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