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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [user.vhdl] - Blame information for rev 9

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1 2 daniel.kho
/*
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        This file is part of the AXI4 Transactor and Bus Functional Model
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        (axi4_tlm_bfm) project:
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                http://www.opencores.org/project,axi4_tlm_bfm
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        Description
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        Synthesisable use case for AXI4 on-chip messaging.
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        To Do:
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        Author(s):
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        - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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        Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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        This source file may be used and distributed without
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        restriction provided that this copyright statement is not
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        removed from the file and that any derivative work contains
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        the original copyright notice and the associated disclaimer.
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        This source file is free software; you can redistribute it
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        and/or modify it under the terms of the GNU Lesser General
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        Public License as published by the Free Software Foundation;
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        either version 2.1 of the License, or (at your option) any
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        later version.
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        This source is distributed in the hope that it will be
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        useful, but WITHOUT ANY WARRANTY; without even the implied
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        warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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        PURPOSE. See the GNU Lesser General Public License for more
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        details.
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        You should have received a copy of the GNU Lesser General
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        Public License along with this source; if not, download it
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        from http://www.opencores.org/lgpl.shtml.
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*/
37 3 daniel.kho
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
38 9 daniel.kho
library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all;            --TODO just use axiTransactor here as transactor should already be wrapped up.
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/* synthesis translate_off */
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library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
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/* synthesis translate_on */
42 2 daniel.kho
 
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entity user is port(
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        /* Comment-out for simulation. */
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--      clk,reset:in std_ulogic;
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        /* AXI Master interface */
48 5 daniel.kho
--      axiMaster_in:in t_axi4StreamTransactor_s2m;
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        axiMaster_out:buffer t_axi4StreamTransactor_m2s
50 2 daniel.kho
 
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        /* Debug ports. */
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);
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end entity user;
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architecture rtl of user is
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        /* Global counters. */
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        constant maxSymbols:positive:=2048;             --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width. 
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        signal symbolsPerTransfer:t_cnt;
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        signal outstandingTransactions:t_cnt;
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        /* BFM signalling. */
62 5 daniel.kho
        signal readRequest,next_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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        signal writeRequest,next_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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        signal readResponse,next_readResponse:t_bfm;
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        signal writeResponse,next_writeResponse:t_bfm;
66 2 daniel.kho
 
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        /* Tester signals. */
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        /* synthesis translate_off */
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        signal clk,reset:std_ulogic:='0';
71 5 daniel.kho
        signal axiMaster_in:t_axi4StreamTransactor_s2m;
72 2 daniel.kho
        /* synthesis translate_on */
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        signal irq_write:std_ulogic;            -- clock gating.
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begin
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        /* pipelines. */
78 9 daniel.kho
        process(clk) is begin
79 2 daniel.kho
                if rising_edge(clk) then
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                        next_readRequest<=readRequest;
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                        next_writeRequest<=writeRequest;
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                        next_readResponse<=readResponse;
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                        next_writeResponse<=writeResponse;
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                end if;
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        end process;
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        /* Bus functional models. */
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        axiMaster: entity work.axiBfmMaster(rtl)
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--              generic map(maxTransactions=>maxSymbols)
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                port map(
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                        aclk=>irq_write, n_areset=>not reset,
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                        trigger=>irq_write='1',
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                        readRequest=>readRequest,       writeRequest=>writeRequest,
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                        readResponse=>readResponse,     writeResponse=>writeResponse,
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                        axiMaster_in=>axiMaster_in,
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                        axiMaster_out=>axiMaster_out,
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                        symbolsPerTransfer=>symbolsPerTransfer,
101 8 daniel.kho
                        outstandingTransactions=>outstandingTransactions
102 2 daniel.kho
        );
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104 9 daniel.kho
        /* Interrupt-request generator. */
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        irq_write<=clk when not reset else '0';
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107 2 daniel.kho
        /* Simulation Tester. */
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        /* synthesis translate_off */
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        clk<=not clk after 10 ps;
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        process is begin
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                reset<='0'; wait for 1 ps;
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                reset<='1'; wait for 500 ps;
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                reset<='0';
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                wait;
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        end process;
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        /* synthesis translate_on */
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        /* Hardware tester. */
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        /* Stimuli sequencer. */
122 9 daniel.kho
        axiMaster_in.tReady<=true when axiMaster_out.tValid and falling_edge(clk);
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124 2 daniel.kho
        sequencer: process(reset,irq_write) is
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                /* Local procedures to map BFM signals with the package procedure. */
126 8 daniel.kho
                procedure read(address:in t_addr) is begin
127 2 daniel.kho
                        read(readRequest,address);
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                end procedure read;
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130 8 daniel.kho
                procedure write(data:in t_msg) is begin
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                        write(request=>writeRequest, address=>(others=>'-'), data=>data);
132 2 daniel.kho
                end procedure write;
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                variable isPktError:boolean;
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                /* Simulation-only randomisation. */
137 9 daniel.kho
                variable rv0,rv1:RandomPType;
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--              variable seed0,seed1:positive:=1;
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--              variable rand0:real;
140 2 daniel.kho
 
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        begin
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                if reset then
143 9 daniel.kho
--                      seed0:=1; seed1:=1;
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--                      uniform(seed0,seed1,rand0);
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--                      
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--                      symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8);
147 3 daniel.kho
 
148 9 daniel.kho
                        rv0.InitSeed(rv0'instance_name);
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                        rv1.InitSeed(rv1'instance_name);
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                        symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
151 2 daniel.kho
                elsif falling_edge(irq_write) then
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                        if outstandingTransactions>0 then
153 9 daniel.kho
--                              uniform(seed0,seed1,rand0);
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--                              write(to_signed(integer(rand0 * 2.0**31),64));
155 2 daniel.kho
 
156 9 daniel.kho
                                write(rv1.RandSigned(axiMaster_out.tData'length));
157 2 daniel.kho
                        else
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                                /* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
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                                --symbolsPerTransfer<=(others=>'0');
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                                /* Testcase 2: number of symbols per transfer is randomised. */
162 9 daniel.kho
--                              uniform(seed0,seed1,rand0);
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--                              symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8);    --symbolsPerTransfer'length
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--                              report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));
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                                /* Truncate symbolsPerTransfer to 8 bits, so that it uses a "small" value for simulation. */
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                                symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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                                report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
169 2 daniel.kho
                        end if;
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                end if;
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        end process sequencer;
172 9 daniel.kho
end architecture rtl;

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