Subversion Repositories axi4_tlm_bfm

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2012 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors.  Please refer to the

# applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus II 32-bit

# Version 12.1 Build 177 11/07/2012 SJ Full Version

# Date created = 23:27:13  September 06, 2013

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               axi4-tlm_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus II software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone IV E"

set_global_assignment -name DEVICE EP4CE115F29C7

set_global_assignment -name TOP_LEVEL_ENTITY "user"

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1

set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:27:13  SEPTEMBER 06, 2013"

set_global_assignment -name LAST_QUARTUS_VERSION 12.1

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008

set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF

set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to reset

set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk

# DE2-115

set_location_assignment PIN_M23 -to nReset

set_location_assignment PIN_Y2 -to clk

set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tauhop-types.vhdl"

set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-fsm.vhdl"

set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tlm.vhdl"

set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-axi-tlm.vhdl"

set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/ddr.vhdl"

set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl"

set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pll.vhd"

set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/stp.vhd"

set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/prbs-31.vhdl"

set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/galois-lfsr.vhdl"

set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/tester.vhdl"

set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/tester-cdcrv.vhdl"

set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user.vhdl"

#set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user-hw-tlm-paper.vhdl"

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top