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<##//////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
//////////////////////////////////////////////////////////////////##>
 
//////////////////////////////////////
//
// General:
//   The AXI master has an internal master per ID. 
//   These internal masters work simultaniously and an interconnect matrix connets them. 
// 
//
// I/F :
//   idle - all internal masters emptied their command FIFOs
//   scrbrd_empty - all scoreboard checks have been completed (for random testing)
//
//
// Tasks:
//
// enable(input master_num)
//   Description: Enables master
//   Parameters: master_num - number of internal master
//
// enable_all()  
//   Description: Enables all masters
//
// write_single(input master_num, input addr, input wdata)
//   Description: write a single AXI burst (1 data cycle)
//   Parameters: master_num - number of internal master
//           addr  - address
//           wdata - write data
// 
// read_single(input master_num, input addr, output rdata)
//   Description: read a single AXI burst (1 data cycle)
//   Parameters: master_num - number of internal master
//               addr  - address
//               rdata - return read data
//
// check_single(input master_num, input addr, input expected)
//   Description: read a single AXI burst and gives an error if the data read does not match expected
//   Parameters: master_num - number of internal master
//               addr  - address
//               expected - expected read data
//
// write_and_check_single(input master_num, input addr, input data)
//   Description: write a single AXI burst read it back and compare the write and read data
//   Parameters: master_num - number of internal master
//               addr  - address
//               data - data to write and expect on read
//
// insert_wr_cmd(input master_num, input addr, input len, input size)
//   Description: add an AXI write burst to command FIFO
//   Parameters: master_num - number of internal master
//               addr - address
//               len - AXI LEN (data strobe number)
//               size - AXI SIZE (data width)
//  
// insert_rd_cmd(input master_num, input addr, input len, input size)
//   Description: add an AXI read burst to command FIFO
//   Parameters: master_num - number of internal master
//               addr - address
//               len - AXI LEN (data strobe number)
//               size - AXI SIZE (data width)
//  
// insert_wr_data(input master_num, input wdata)
//   Description: add a single data to data FIFO (to be used in write bursts)
//   Parameters: master_num - number of internal master
//               wdata - write data
//  
// insert_wr_incr_data(input master_num, input addr, input len, input size)
//   Description: add an AXI write burst to command FIFO will use incremental data (no need to use insert_wr_data)
//   Parameters: master_num - number of internal master
//               addr - address
//               len - AXI LEN (data strobe number)
//               size - AXI SIZE (data width)
//  
// insert_rand_chk(input master_num, input burst_num)
//   Description: add multiple commands to command FIFO. Each command writes incremental data to a random address, reads the data back and checks the data. Useful for random testing.
//   Parameters: master_num - number of internal master
//               burst_num - total number of bursts to check
//  
// insert_rand(input burst_num)
//   Description: disperces burst_num between internal masters and calls insert_rand_chk for each master
//   Parameters:  burst_num - total number of bursts to check (combined)
//
//  
//  Parameters:
//  
//    For random testing: (changing these values automatically update interanl masters)
//      ahb_bursts - if set, bursts will only be of length 1, 4, 8 or 16.
//      len_min  - minimum burst AXI LEN (length)
//      len_max  - maximum burst AXI LEN (length)
//      size_min - minimum burst AXI SIZE (width)
//      size_max - maximum burst AXI SIZE (width)
//      addr_min - minimum address (in bytes)
//      addr_max - maximum address (in bytes)
//  
//////////////////////////////////////
 
OUTFILE PREFIX.v
 
INCLUDE def_axi_master.txt
 
ITER IDX ID_NUM
module PREFIX(PORTS);
 
`include "prgen_rand.v"
 
   input                               clk;
   input                               reset;
 
   port                                GROUP_STUB_AXI;
 
   output                              idle;
   output                              scrbrd_empty;
 
 
   //random parameters
   integer                             GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
 
   wire                                GROUP_STUB_AXI_IDX;
   wire                                idle_IDX;
   wire                                scrbrd_empty_IDX;
 
 
   always @(*)
     begin
        #FFD;
        PREFIX_singleIDX.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND;
     end
 
   assign                              idle = CONCAT(idle_IDX &);
   assign                              scrbrd_empty = CONCAT(scrbrd_empty_IDX &);
 
 
   CREATE axi_master_single.v
 
     LOOP IDX ID_NUM
   PREFIX_single #(IDX, ID_BITS'bGROUP_AXI_ID[IDX], CMD_DEPTH)
   PREFIX_singleIDX(
                   .clk(clk),
                   .reset(reset),
                   .GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
                   .idle(idle_IDX),
                   .scrbrd_empty(scrbrd_empty_IDX)
                   );
 
   ENDLOOP IDX
 
     IFDEF TRUE(ID_NUM==1)
 
   assign GROUP_STUB_AXI.OUT = GROUP_STUB_AXI_0.OUT;
   assign GROUP_STUB_AXI_0.IN = GROUP_STUB_AXI.IN;
 
     ELSE TRUE(ID_NUM==1)
 
CREATE ic.v \\
DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX) \\
DEFCMD(SWAP.GLOBAL MASTER_NUM ID_NUM) \\
DEFCMD(SWAP.GLOBAL SLAVE_NUM 1) \\
DEFCMD(SWAP.GLOBAL CONST(MSTR_ID_BITS) ID_BITS) \\
DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) \\
DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\
DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\
DEFCMD(DEFINE.GLOBAL UNIQUE_ID) \\
DEFCMD(SWAP.GLOBAL CONST(USER_BITS) 0)
LOOP IDX ID_NUM
  STOMP NEWLINE
  DEFCMD(GROUP.GLOBAL MIDX_ID overrides { ) \\
  DEFCMD(GROUP_AXI_ID[IDX]) \\
  DEFCMD(})
ENDLOOP IDX
 
 
    PREFIX_ic PREFIX_ic(
                       .clk(clk),
                       .reset(reset),
                       .MIDX_GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
                       .S0_GROUP_STUB_AXI(GROUP_STUB_AXI),
                       STOMP ,
 
      );
 
     ENDIF TRUE(ID_NUM==1)
 
 
 
   task check_master_num;
      input [24*8-1:0] task_name;
      input [31:0] master_num;
      begin
         if (master_num >= ID_NUM)
           begin
              $display("FATAL ERROR: task %0s called for master %0d that does not exist.\tTime: %0d ns.", task_name, master_num, $time);
           end
      end
   endtask
 
   task enable;
      input [31:0] master_num;
      begin
         check_master_num("enable", master_num);
         case (master_num)
           IDX : PREFIX_singleIDX.enable = 1;
         endcase
      end
   endtask
 
   task enable_all;
      begin
         PREFIX_singleIDX.enable = 1;
      end
   endtask
 
   task write_single;
      input [31:0] master_num;
      input [ADDR_BITS-1:0]  addr;
      input [DATA_BITS-1:0]  wdata;
      begin
         check_master_num("write_single", master_num);
         case (master_num)
           IDX : PREFIX_singleIDX.write_single(addr, wdata);
         endcase
      end
   endtask
 
   task read_single;
      input [31:0] master_num;
      input [ADDR_BITS-1:0]  addr;
      output [DATA_BITS-1:0]  rdata;
      begin
         check_master_num("read_single", master_num);
         case (master_num)
           IDX : PREFIX_singleIDX.read_single(addr, rdata);
         endcase
      end
   endtask
 
   task check_single;
      input [31:0] master_num;
      input [ADDR_BITS-1:0]  addr;
      input [DATA_BITS-1:0]  expected;
      begin
         check_master_num("check_single", master_num);
         case (master_num)
           IDX : PREFIX_singleIDX.check_single(addr, expected);
         endcase
      end
   endtask
 
   task write_and_check_single;
      input [31:0] master_num;
      input [ADDR_BITS-1:0]  addr;
      input [DATA_BITS-1:0]  data;
      begin
         check_master_num("write_and_check_single", master_num);
         case (master_num)
           IDX : PREFIX_singleIDX.write_and_check_single(addr, data);
         endcase
      end
   endtask
 
   task insert_wr_cmd;
      input [31:0] master_num;
      input [ADDR_BITS-1:0]  addr;
      input [LEN_BITS-1:0]   len;
      input [SIZE_BITS-1:0]  size;
      begin
         check_master_num("insert_wr_cmd", master_num);
         case (master_num)
           IDX : PREFIX_singleIDX.insert_wr_cmd(addr, len, size);
         endcase
      end
   endtask
 
   task insert_rd_cmd;
      input [31:0] master_num;
      input [ADDR_BITS-1:0]  addr;
      input [LEN_BITS-1:0]   len;
      input [SIZE_BITS-1:0]  size;
      begin
         check_master_num("insert_rd_cmd", master_num);
         case (master_num)
           IDX : PREFIX_singleIDX.insert_rd_cmd(addr, len, size);
         endcase
      end
   endtask
 
   task insert_wr_data;
      input [31:0] master_num;
      input [DATA_BITS-1:0]  wdata;
      begin
         check_master_num("insert_wr_data", master_num);
         case (master_num)
           IDX : PREFIX_singleIDX.insert_wr_data(wdata);
         endcase
      end
   endtask
 
   task insert_wr_incr_data;
      input [31:0] master_num;
      input [ADDR_BITS-1:0]  addr;
      input [LEN_BITS-1:0]   len;
      input [SIZE_BITS-1:0]  size;
      begin
         check_master_num("insert_wr_incr_data", master_num);
         case (master_num)
           IDX : PREFIX_singleIDX.insert_wr_incr_data(addr, len, size);
         endcase
      end
   endtask
 
   task insert_rand_chk;
      input [31:0] master_num;
      input [31:0] burst_num;
      begin
         check_master_num("insert_rand_chk", master_num);
         case (master_num)
           IDX : PREFIX_singleIDX.insert_rand_chk(burst_num);
         endcase
      end
   endtask
 
   task insert_rand;
      input [31:0] burst_num;
 
      reg [31:0] burst_numIDX;
      integer remain;
      begin
         remain = burst_num;
         LOOP IDX ID_NUM
         if (remain > 0)
           begin
              burst_numIDX = rand(1, remain);
              remain = remain - burst_numIDX;
              insert_rand_chk(IDX, burst_numIDX);
           end
         ENDLOOP IDX
      end
   endtask
 
 
endmodule
 
 

Line No.	Rev	Author	Line
1	21	eyalhoc	`<##//////////////////////////////////////////////////////////////////`
2	2	eyalhoc	`//// ////`
3			`//// Author: Eyal Hochberg ////`
4			`//// eyal@provartec.com ////`
5			`//// ////`
6			`//// Downloaded from: http://www.opencores.org ////`
7			`/////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// Copyright (C) 2010 Provartec LTD ////`
10			`//// www.provartec.com ////`
11			`//// info@provartec.com ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer.////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation.////`
21			`//// ////`
22			`//// This source is distributed in the hope that it will be ////`
23			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
24			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
25			`//// PURPOSE. See the GNU Lesser General Public License for more////`
26			`//// details. http://www.gnu.org/licenses/lgpl.html ////`
27			`//// ////`
28	21	eyalhoc	`//////////////////////////////////////////////////////////////////##>`
29	6	eyalhoc
30			`//////////////////////////////////////`
31			`//`
32			`// General:`
33			`// The AXI master has an internal master per ID.`
34			`// These internal masters work simultaniously and an interconnect matrix connets them.`
35			`//`
36			`//`
37			`// I/F :`
38			`// idle - all internal masters emptied their command FIFOs`
39			`// scrbrd_empty - all scoreboard checks have been completed (for random testing)`
40			`//`
41			`//`
42			`// Tasks:`
43			`//`
44			`// enable(input master_num)`
45			`// Description: Enables master`
46			`// Parameters: master_num - number of internal master`
47			`//`
48			`// enable_all()`
49			`// Description: Enables all masters`
50			`//`
51			`// write_single(input master_num, input addr, input wdata)`
52			`// Description: write a single AXI burst (1 data cycle)`
53			`// Parameters: master_num - number of internal master`
54			`// addr - address`
55			`// wdata - write data`
56			`//`
57			`// read_single(input master_num, input addr, output rdata)`
58			`// Description: read a single AXI burst (1 data cycle)`
59			`// Parameters: master_num - number of internal master`
60			`// addr - address`
61			`// rdata - return read data`
62			`//`
63			`// check_single(input master_num, input addr, input expected)`
64			`// Description: read a single AXI burst and gives an error if the data read does not match expected`
65			`// Parameters: master_num - number of internal master`
66			`// addr - address`
67			`// expected - expected read data`
68			`//`
69			`// write_and_check_single(input master_num, input addr, input data)`
70			`// Description: write a single AXI burst read it back and compare the write and read data`
71			`// Parameters: master_num - number of internal master`
72			`// addr - address`
73			`// data - data to write and expect on read`
74			`//`
75			`// insert_wr_cmd(input master_num, input addr, input len, input size)`
76			`// Description: add an AXI write burst to command FIFO`
77			`// Parameters: master_num - number of internal master`
78			`// addr - address`
79			`// len - AXI LEN (data strobe number)`
80			`// size - AXI SIZE (data width)`
81			`//`
82			`// insert_rd_cmd(input master_num, input addr, input len, input size)`
83			`// Description: add an AXI read burst to command FIFO`
84			`// Parameters: master_num - number of internal master`
85			`// addr - address`
86			`// len - AXI LEN (data strobe number)`
87			`// size - AXI SIZE (data width)`
88			`//`
89			`// insert_wr_data(input master_num, input wdata)`
90			`// Description: add a single data to data FIFO (to be used in write bursts)`
91			`// Parameters: master_num - number of internal master`
92			`// wdata - write data`
93			`//`
94			`// insert_wr_incr_data(input master_num, input addr, input len, input size)`
95			`// Description: add an AXI write burst to command FIFO will use incremental data (no need to use insert_wr_data)`
96			`// Parameters: master_num - number of internal master`
97			`// addr - address`
98			`// len - AXI LEN (data strobe number)`
99			`// size - AXI SIZE (data width)`
100			`//`
101			`// insert_rand_chk(input master_num, input burst_num)`
102			`// Description: add multiple commands to command FIFO. Each command writes incremental data to a random address, reads the data back and checks the data. Useful for random testing.`
103			`// Parameters: master_num - number of internal master`
104			`// burst_num - total number of bursts to check`
105			`//`
106	9	eyalhoc	`// insert_rand(input burst_num)`
107			`// Description: disperces burst_num between internal masters and calls insert_rand_chk for each master`
108			`// Parameters: burst_num - total number of bursts to check (combined)`
109			`//`
110	6	eyalhoc	`//`
111			`// Parameters:`
112			`//`
113			`// For random testing: (changing these values automatically update interanl masters)`
114	10	eyalhoc	`// ahb_bursts - if set, bursts will only be of length 1, 4, 8 or 16.`
115	6	eyalhoc	`// len_min - minimum burst AXI LEN (length)`
116			`// len_max - maximum burst AXI LEN (length)`
117			`// size_min - minimum burst AXI SIZE (width)`
118			`// size_max - maximum burst AXI SIZE (width)`
119			`// addr_min - minimum address (in bytes)`
120			`// addr_max - maximum address (in bytes)`
121			`//`
122			`//////////////////////////////////////`
123
124			`OUTFILE PREFIX.v`
125
126			`INCLUDE def_axi_master.txt`
127
128	14	eyalhoc	`ITER IDX ID_NUM`
129	6	eyalhoc	`module PREFIX(PORTS);`
130
131	9	eyalhoc	`include "prgen_rand.v"
132
133	6	eyalhoc	`input clk;`
134			`input reset;`
135
136			`port GROUP_STUB_AXI;`
137
138			`output idle;`
139			`output scrbrd_empty;`
140
141
142			`//random parameters`
143			`integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;`
144
145	14	eyalhoc	`wire GROUP_STUB_AXI_IDX;`
146			`wire idle_IDX;`
147			`wire scrbrd_empty_IDX;`
148	6	eyalhoc
149
150			`always @(*)`
151			`begin`
152			`#FFD;`
153	14	eyalhoc	`PREFIX_singleIDX.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND;`
154	6	eyalhoc	`end`
155
156	14	eyalhoc	`assign idle = CONCAT(idle_IDX &);`
157			`assign scrbrd_empty = CONCAT(scrbrd_empty_IDX &);`
158	6	eyalhoc
159
160			`CREATE axi_master_single.v`
161
162	14	eyalhoc	`LOOP IDX ID_NUM`
163	17	eyalhoc	`PREFIX_single #(IDX, ID_BITS'bGROUP_AXI_ID[IDX], CMD_DEPTH)`
164	14	eyalhoc	`PREFIX_singleIDX(`
165	6	eyalhoc	`.clk(clk),`
166			`.reset(reset),`
167	14	eyalhoc	`.GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),`
168			`.idle(idle_IDX),`
169			`.scrbrd_empty(scrbrd_empty_IDX)`
170	6	eyalhoc	`);`
171	9	eyalhoc
172	14	eyalhoc	`ENDLOOP IDX`
173	6	eyalhoc
174			`IFDEF TRUE(ID_NUM==1)`
175
176			`assign GROUP_STUB_AXI.OUT = GROUP_STUB_AXI_0.OUT;`
177			`assign GROUP_STUB_AXI_0.IN = GROUP_STUB_AXI.IN;`
178
179			`ELSE TRUE(ID_NUM==1)`
180
181	14	eyalhoc	`CREATE ic.v \\`
182			`DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX) \\`
183	9	eyalhoc	`DEFCMD(SWAP.GLOBAL MASTER_NUM ID_NUM) \\`
184			`DEFCMD(SWAP.GLOBAL SLAVE_NUM 1) \\`
185	20	eyalhoc	`DEFCMD(SWAP.GLOBAL CONST(MSTR_ID_BITS) ID_BITS) \\`
186	9	eyalhoc	`DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) \\`
187			`DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\`
188	14	eyalhoc	`DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\`
189	17	eyalhoc	`DEFCMD(DEFINE.GLOBAL UNIQUE_ID) \\`
190	14	eyalhoc	`DEFCMD(SWAP.GLOBAL CONST(USER_BITS) 0)`
191			`LOOP IDX ID_NUM`
192			`STOMP NEWLINE`
193			`DEFCMD(GROUP.GLOBAL MIDX_ID overrides { ) \\`
194			`DEFCMD(GROUP_AXI_ID[IDX]) \\`
195			`DEFCMD(})`
196			`ENDLOOP IDX`
197	6	eyalhoc
198	14	eyalhoc
199	6	eyalhoc	`PREFIX_ic PREFIX_ic(`
200			`.clk(clk),`
201			`.reset(reset),`
202	14	eyalhoc	`.MIDX_GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),`
203	6	eyalhoc	`.S0_GROUP_STUB_AXI(GROUP_STUB_AXI),`
204			`STOMP ,`
205
206			`);`
207
208			`ENDIF TRUE(ID_NUM==1)`
209
210
211
212			`task check_master_num;`
213			`input [24*8-1:0] task_name;`
214			`input [31:0] master_num;`
215			`begin`
216			`if (master_num >= ID_NUM)`
217			`begin`
218			`$display("FATAL ERROR: task %0s called for master %0d that does not exist.\tTime: %0d ns.", task_name, master_num, $time);`
219			`end`
220			`end`
221			`endtask`
222
223			`task enable;`
224			`input [31:0] master_num;`
225			`begin`
226			`check_master_num("enable", master_num);`
227			`case (master_num)`
228	14	eyalhoc	`IDX : PREFIX_singleIDX.enable = 1;`
229	6	eyalhoc	`endcase`
230			`end`
231			`endtask`
232
233			`task enable_all;`
234			`begin`
235	14	eyalhoc	`PREFIX_singleIDX.enable = 1;`
236	6	eyalhoc	`end`
237			`endtask`
238
239			`task write_single;`
240			`input [31:0] master_num;`
241			`input [ADDR_BITS-1:0] addr;`
242			`input [DATA_BITS-1:0] wdata;`
243			`begin`
244			`check_master_num("write_single", master_num);`
245			`case (master_num)`
246	14	eyalhoc	`IDX : PREFIX_singleIDX.write_single(addr, wdata);`
247	6	eyalhoc	`endcase`
248			`end`
249			`endtask`
250
251			`task read_single;`
252			`input [31:0] master_num;`
253			`input [ADDR_BITS-1:0] addr;`
254			`output [DATA_BITS-1:0] rdata;`
255			`begin`
256			`check_master_num("read_single", master_num);`
257			`case (master_num)`
258	14	eyalhoc	`IDX : PREFIX_singleIDX.read_single(addr, rdata);`
259	6	eyalhoc	`endcase`
260			`end`
261			`endtask`
262
263			`task check_single;`
264			`input [31:0] master_num;`
265			`input [ADDR_BITS-1:0] addr;`
266			`input [DATA_BITS-1:0] expected;`
267			`begin`
268			`check_master_num("check_single", master_num);`
269			`case (master_num)`
270	14	eyalhoc	`IDX : PREFIX_singleIDX.check_single(addr, expected);`
271	6	eyalhoc	`endcase`
272			`end`
273			`endtask`
274
275			`task write_and_check_single;`
276			`input [31:0] master_num;`
277			`input [ADDR_BITS-1:0] addr;`
278			`input [DATA_BITS-1:0] data;`
279			`begin`
280			`check_master_num("write_and_check_single", master_num);`
281			`case (master_num)`
282	14	eyalhoc	`IDX : PREFIX_singleIDX.write_and_check_single(addr, data);`
283	6	eyalhoc	`endcase`
284			`end`
285			`endtask`
286
287			`task insert_wr_cmd;`
288			`input [31:0] master_num;`
289			`input [ADDR_BITS-1:0] addr;`
290			`input [LEN_BITS-1:0] len;`
291			`input [SIZE_BITS-1:0] size;`
292			`begin`
293			`check_master_num("insert_wr_cmd", master_num);`
294			`case (master_num)`
295	14	eyalhoc	`IDX : PREFIX_singleIDX.insert_wr_cmd(addr, len, size);`
296	6	eyalhoc	`endcase`
297			`end`
298			`endtask`
299
300			`task insert_rd_cmd;`
301			`input [31:0] master_num;`
302			`input [ADDR_BITS-1:0] addr;`
303			`input [LEN_BITS-1:0] len;`
304			`input [SIZE_BITS-1:0] size;`
305			`begin`
306			`check_master_num("insert_rd_cmd", master_num);`
307			`case (master_num)`
308	14	eyalhoc	`IDX : PREFIX_singleIDX.insert_rd_cmd(addr, len, size);`
309	6	eyalhoc	`endcase`
310			`end`
311			`endtask`
312
313			`task insert_wr_data;`
314			`input [31:0] master_num;`
315			`input [DATA_BITS-1:0] wdata;`
316			`begin`
317			`check_master_num("insert_wr_data", master_num);`
318			`case (master_num)`
319	14	eyalhoc	`IDX : PREFIX_singleIDX.insert_wr_data(wdata);`
320	6	eyalhoc	`endcase`
321			`end`
322			`endtask`
323
324			`task insert_wr_incr_data;`
325			`input [31:0] master_num;`
326			`input [ADDR_BITS-1:0] addr;`
327			`input [LEN_BITS-1:0] len;`
328			`input [SIZE_BITS-1:0] size;`
329			`begin`
330			`check_master_num("insert_wr_incr_data", master_num);`
331			`case (master_num)`
332	14	eyalhoc	`IDX : PREFIX_singleIDX.insert_wr_incr_data(addr, len, size);`
333	6	eyalhoc	`endcase`
334			`end`
335			`endtask`
336
337			`task insert_rand_chk;`
338			`input [31:0] master_num;`
339			`input [31:0] burst_num;`
340			`begin`
341			`check_master_num("insert_rand_chk", master_num);`
342			`case (master_num)`
343	14	eyalhoc	`IDX : PREFIX_singleIDX.insert_rand_chk(burst_num);`
344	6	eyalhoc	`endcase`
345			`end`
346			`endtask`
347
348	9	eyalhoc	`task insert_rand;`
349			`input [31:0] burst_num;`
350
351			`reg [31:0] burst_numIDX;`
352			`integer remain;`
353			`begin`
354			`remain = burst_num;`
355			`LOOP IDX ID_NUM`
356			`if (remain > 0)`
357			`begin`
358			`burst_numIDX = rand(1, remain);`
359			`remain = remain - burst_numIDX;`
360			`insert_rand_chk(IDX, burst_numIDX);`
361			`end`
362			`ENDLOOP IDX`
363			`end`
364			`endtask`
365	6	eyalhoc
366
367			`endmodule`
368
369

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